This application note was developed to demonstrate the capabilities of the Siemens CAPCOM unit, as used on the 80C537, C505C and C515C 8-bit microcontrollers. The same basic approach would be used on the similar 16-channel CAPCOM unit on the 16-bit C167 family.

In a Manchester encoded bitstream the actual binary data to be transmitted over the cable is not sent as a sequence of logic 1's and 0's. Instead, the bits are translated into a slightly different format that has a number of advantages over using straight binary encoding (i.e. NRZ).

Manchester encoding follows the rules shown below:

The following diagram shows a typical Manchester encoded signal with the corresponding binary representation of the data (0,0,1,0,1,1) being sent.

In the Manchester encoding shown, a logic 1 is indicated by a 1 to 0 transition at the centre of the bit and a logic 0 is indicated by a 0 to 1 transition at the centre of the bit. Note that signal transitions do not always occur at the 'bit boundaries' (the division between one bit and another), but that there is always a transition at the centre of each bit.

This application note describes a method for decoding a Manchester encoded bitstream with using the capture compare unit of a SABC505C microcontroller. The bitstream to be decoded consists of a start of frame consisting of 8 logic 1's followed by 28 data bits. Decoding of a data packet has two distinct phases, detection of the start of frame and synchronization to the bit period and then sampling of the data bits. Both of these functions can be achieved with the compare compare unit of the C505C with minimal CPU overhead. The following code was run on a C505C controller with an 8MHz oscillator. Thus the bit period of the bitstream was 208 micro seconds and the instruction cycle of the processor was 750 nano seconds with an interrupt latency of between 3 and 9 oscillator cycles. In practice the runtime of the sync detect routine was found to be 50 micro seconds and the sample routine took 30 microseconds. It was also found that the design of the capture compare unit allowed very precise control of the pulse width measurement and of the data sampling point without any nasty software compromises or "magic numbers".

The start of frame detector uses the capture function to measure the time between falling edges of received data. Since it is impossible to tell the logic state of a received bit until synchronization has occurred it is assumed that eight bits of the same logic level will be a start of frame.

In compare mode the CC1 registers are compared against the current value of Timer2. If there is a match an interrupt is generated and the current value of the CC0 pin is read and stored. The sample period is synchronized against the final falling edge of the start of frame. The first sample is taken at three quarter bit period to locate it at a suitable sampling point. The remaining samples are taken at one bit period. A more rigorous algorithm would take two samples per bit period to read a logic level and then its compliment to ensure a correctly formatted bit. It would also be possible to use the bit period calculated during the start of frame as the basis for the sample period. This would allow the receiver to make small adjustments for oscillator drift between the transmitter and receiver.

Since the C505C has four fully independent orthogonal capture compare channels a second channel could be implemented to run in parallel with the first.using the method described above.

C505C Manchester decoding program

The following functions implement a manchester decoder for the C505C microcontroller. The code has been written in C using the Keil C51 compiler version 5.50. apart from startup code no assembler is used in the application. The diagram below shows the calling hierarchy.

The Main function configures the microcontroller and then sits in a background loop which processes the decoded data.

Init capture configures the capture compare unit and timer2. It then enables the CC0 interrupt.

The sync detect function runs off the CC0 interrupt and will detect 8 consecutive pulses of the same logic level ie the start of frame. Once the start of frame is detected the start sample function is called.

Start sample configures the starts the CC1 compare function at 3/4 bit period for the first sample and disables the CC0 interrupt.

Sample runs off the CC1 interrupt and performs 28 samples, one for each of the bit periods in the message. The first sample is at 3/4 bit period with all the subsequent samples at one bit period. After the last sample the CC1 interrupt is disabled and the CC0 interrupt is enabled to restart the sync detect for the next message. Finally the data ready flag is set to start processing in the background loop. For every 8 bit received the byte ready flag is set. The first address byte is compared against a table of 64 bytes and the array address of any matches are stored in an index array. When subsequent address bytes are received this index array is used as a linked list to matching addresses in the address array table. If a match fails the address is weeded out of the index table until a final byte corresponding to the matching address is in position zero of the index array when the final nibble is received. If no match is found the message will be rejected and a second channel can be enabled.

If you would like us to send you the program for the above Manchester decoder, compiled for the Keil C51 compiler... [get more info]

Note: Some illustrations are included courtesy of Siemens Plc