1. Getting Started With The 166

1.1 Basic Considerations

1.1.1 Family Overview

The 166 family now includes the C161, 163, 165 and 167, which amounts to around 20 different microcontrollers when all the variants are considered. It is an original core design and so is not directly related to any previous architecture. The first family member was the 166, available in masked ROM, FLASH EPROM and ROMless versions. The second member was the 167 which had an expanded addressing capability, integral chip selects plus many more peripherals and introduced some new assembler instructions. In fact, all the subsequent versions have been based on the 167 core. This includes the C161, C164, 163 and 165.

In this guide, the original 166 cored-versions will be referred to as the "166" while the 167 and its derivatives that share the enhanced core will be known as the "167". Unless specific peripherals are being referred to, what is appropriate to the 167 will apply equally to its derivatives.

1.1.2 Fundamental Design Factors

When starting out on a 166 family design, there are a number of basic things you must decide. Wrong decisions here can have expensive consequences later in the project. There are a good many features of the architecture which can be a bit puzzling to those used to conventional devices. What follows is a simple guide to what you really need to know to get best from this ingenious and powerful microcontroller family!

* What clock speed is required to acheive the necessary CPU processing power?

* What sort of clock source is suitable?

* What sort of reset circuit should be used?

* What CPU sockets are available?

* How is the on-chip ROM or FLASH EPROM to be programmed?

* How is external FLASH EPROM to be programmed?

* Is a full 16 bit bus necessary or will an 8-bit bus be sufficient?

* Will there be some external peripheral chips that will require different bus modes?

* How much IO is required to implement the application?

* Should WRH/WRL be used?

* Should the chip selects be used?

* Which peripheral pins are best allocated to the various different signal processing or generation functions in

the application?

And others...

1.2.1 Setting The CPU Hardware Configuration Options (166)

While in reset, the 166 reads the EBC0, EBC1 and /BUSACT pins to determine which bus mode is to be used. This information is then written into the appropriate fields in the SYSCON special function register.

1.2.2 Setting The CPU Hardware Configuration Options (167)

In common with many modern microcontrollers, between the /RESIN pin going high and the rising edge of the first ALE pulse, the 167 reads the bit pattern on Port 0 to determine the following fundamental settings:

* What the default bus mode is

* How many pins on port 6 should be used as chip selects

* How many address lines should be used

* Whether the on-circuit emulation mode is be entered

* Whether the WRITEHIGH/WRITELOW mode required

* Whether the BOOTSTRAP mode is to be activated

The pattern is placed onto the port by the user attaching pull-down resistors to the appropriate P0 pins. For example, to set 16 bit non-multiplexed bus mode, a pull-down resistor is added to P0.7, while P0.6 floats high. The values of the pull-down resistors should be calculated with reference to the overall loading on Port 0, from external memory devices etc., using the formulae given in section 1.3. The value required for a typical 1 EPROM + 1 RAM

166 Designer's Guide - Page

system is 8K0, this representing the stated maximum value and covers 90% of all designs seen to date. In extreme cases, as little as 1K8 can be used but this is exceptional as the leakage currents from modern memory devices are extremely small. Overall, the user is simply advised to check the situation in the design and not to just to blindly accept the usual 8K0 value!

Note: The databooks frequently refer to port 0 either as a 16-bit port or as two 8-bit ports, made up of P0L (LOW) and P0H (HIGH). Thus P0.15 is bit-16 on port 0 which is also P0H.7. By the same convention, P0.7 is also known as P0L.7.

1.3 Calculating The Pull-Down Resistor Values

Finding the value of the pull-down resistors for your design is fairly straightforward. You will need to know the leakage current from the devices such as RAMs, ROMs etc that are attached to the bus.

VILMAX = Highest voltage that will be accepted as a `0'

ISYSL = Leakage current from RAMs, ROMs etc.

IP0L = Current flow from 167's Port 0 when pin is at VILMAX

RPD = Pull down resistor on Port 0

From 167 Databook:

VILMAX = (0.2 x Vcc) - 0.1V => 0.8V <= VILMAX =< 1.0V

Vcc = 5V +/-10% => 4.5V =< Vcc =< 5.5V

Pull Down Resistor Calculation

RPD < VILMAX = VILMAX

IPD IP0L + ISYSL

Example Without System Leakage Current, ISYSL:

RPD < VILMAX = 0.8V = 8K0

IP0L 100uA

Thus the maximum recommended value is RPD = 8K0. In practice, 8K2 is almost always used.

1.4 Pull-Up Resistor Calculations

In some designs, the loading on the bus can be such that there is a net flow of current into the external devices to ground, i.e. the bus sinks current. In extreme cases, this can cause the port 0 pattern read by the 167 to be incorrect. It must be stressed that this very rare but can easily be compensated for by using a high-value pull-up resistor. Such measures are only required if the current sunk into the external device ISYSH, is greater or equal to 10uA. Before finalising any design the condition should be checked for and a pull-up resistor added if necessary. The procedure for calculating the pull-up resistor is as follows:

Pull-Down Resistor Current Flow

166 Designer's Guide - Page

VIHMIN = Lowest voltage on pin that will be accepted as a `1'

ISYSH = Current sunk into bus devices etc.

IP0H = Current that can be drawn from 167's Port 0 at VIHMIN

RPU = Pull up resistor on P0

From 167 Databook:

VIHMIN = 0.2 x Vcc + 0.9v - 0,1V => 1.8V <= VIHMIN =< 2.0V

Vcc = 5V +/-10% => 4.5V =< VCC =< 5.5V

Pull Up Resistor Calculation

RPu < VPU = VCCMIN - VIHMIN

IPD ISYSH - IP0H

Example: ISYSL = 50uA

RPU < 4.5v - 1.8v = 67.6K

50uA - 10uA

1.4 Setting The Configuration Without Pulldown Resistors

It is possible to use a simple analog-type switch to set the pattern on port 0 in external bus designs. Here, the links to ground are only applied to the port 0 pins when the /RESIN signal is low, i.e. the 166 is in reset. The D-type latch powers up with the Q output low so that the link pattern is applied to port 0. When the RESET signal goes high to release the CPU, the switch is kept active until the first rising edge of ALE at the start of the first bus cycle. At this point the CLK signal forces the latch to set Q high so that the link pattern is removed and the bus operates normally. Waiting until the first ALE is essential - controlling the switches from /RESIN alone could result in the CPU reading the pattern after it has been removed!

Pull-Up Resistors

On Port 0

Active Port 0

Configuration Scheme

166 Designer's Guide - Page

1.5 Port 0 Configuration Functions

This diagram gives the individual configuration functions of the port 0 pins when CPU is between the end of reset and the rising edge of the first ALE:

EMU - Emulation mode allows the XBUS peripherals to be accessed by an external 167 core. This

is used on the DPROBE167 bondout in-circuit emulator to allow the C167E-BA emulation chip to

access the CAN peripheral and XRAM on the slave 167 processor on the EP167-Y. DO NOT FIT A PULL DOWN RESISTOR ON THIS PIN!

ADP - On-circuit emulation mode puts all the 167 pins into a high-impedance tristate condition so

that an emulator's clip-over adaptor can be attached to a soldered-in device. Note that if the

clock source is a crystal, pin XTAL2 must be disconnected from the processor so that the

emulator's CPU can pick up the clock. DO NOT FIT A PULL DOWN RESISTOR ON THIS PIN!

R - Reserved, do not use!

BSL - Enables the bootstrap loader mode for on- and off-chip FLASH-programming etc..

See section 9.3.

BUSTYP - The external bus type can be set as shown below. These two pins form the BUSTYP field

in the BUSCON0 special function register, where it can be modified by software.

P0.7 P0.6 External Bus Mode

0 0 8-bit non-multiplexed

0 1 8-bit multiplexed

1 0 16-bit non-multiplexed

1 1 16-bit multiplexed (DEFAULT - no pull-down)

WRC - Cause the /WR pin to become /WRH (write high) and /BHE to become /WRL (write low) to make

the use of 8-bit RAMs in a 16-bit system easier. See section 5.1.

CSSEL - The number of chip selects that are to be enabled on port 6 - see section 4.1.

CSSEL Chip Select Lines On Port 6

1 1 Five: /CS4, /CS3, /CS2, /CS1, /CS0 (DEFAULT - no pull-down)

1 0 None:

0 1 Two: /CS1, /CS0

0 0 Three: /CS2, /CS1, /CS0

166 Designer's Guide - Page

SALSEL - Number of "segment address" lines, i.e. how many additional address lines above A15 will

be enabled.

SALSEL Segment Address Lines On Port 4

1 1 Two: A16, A17 (DEFAULT - no pull-down)

1 0 Eight: A16 - A23

0 1 None: ("NONSEGMENTED" or "TINY Model" - very rare!)

0 0 Four: A16 - A19

CLKCFG - Programming for processor clock input, with optional phase lock loop (PLL) clock multiplier.

CLKCFG . Clock Generator Frequency Multiplier Control

1 1 1 x4 (DEFAULT - no pull-down)

1 1 0 x3

1 0 1 x2

1 0 0 x5

0 X X Direct Drive

1.6 Reset Control

The 166 family has two reset pins, /RESIN and /RESOUT. The former is a conventional active-low reset input while /RESOUT is an output pin which stays low until the CPU executes the EINIT (end-of-initialisation) instruction. /RESOUT is thus a means of keeping peripheral devices in a reset state until the CPU is fully initialised.

The /RESIN input must be kept low for the duration of the startup phase of the clock oscillator or crystal - the latter requires up to 50ms. Once stable, any low level on /RESIN of more than two state times (100ns @ 20MHz) will reset the CPU. Low times of less than this must be avoided.

The pin has an internal pull-up resistance of between 50k and 150k, so the simplest reset circuit is just a capacitor to ground. The value must be chosen to give a time constant of at least equal to the clock stabilisation time. 22uF is a common choice.

However, such a simple arrangement is not suitable for use in those situations where the power supply could suffer from instability or brown-outs. In most commercial products, the use of a proper microprocessor power supply and RESET manager such as the MAX691 is highly recommended. This low-cost device will hold the CPU in RESET if the power supply is less than 4.5v.

Simple Reset Scheme

166 Designer's Guide - Page

2. Clock Speeds And Sources

2.1 166 Variants

The original 166 has a divide by two prescaler so that a 40MHz crystal or oscillator is required to yield the maximum possible 20MHz CPU clock. The basic unit of time in the 166 core is a single state time, corresponding to 50ns at 20MHz. Most 166 instructions execute in two state times, i.e. 100ns.

The `W'-suffixed 166 parts have no divide-by-two and thus can use a 20MHz clock source directly. These parts must be used with a crystal as they demand a 50% duty cycle clock, which cannot be guaranteed with an oscillator module. If an oscillator module is used, it must have a rise and fall time of <5ns. Such devices are readily available at a few pounds each.

2.2 165 And Basic 167 Variants

From stepping level BA, the 165 versions can run with either 40 or 20MHz clock sources. The presence of a pull-down resistor on P0.15 will cause the CPU to expect a 1:1 clock rather than a 2:1.

2.3 167SR & CR Variants

The 167CR and 167SR are all of the `W' type in that they can use a 20MHz crystal. They can also use a 5MHz crystal and use the on-chip phase-lock loop (PLL) to perform a programmable frequency multiplication up to the usual 20MHz or newer 25MHz. The PLL is disabled by a pull-down resistor on Port P0.15. From C167CR BA step onwards, the PLL can provide frequency multipliers of x1, x2, x3, x4 and x5, so that in the latter case, a 5MHz crystal will yield a 25MHz clock. The exact multiplier is set via pull-down resistors on P0.14 & P0.13 (P0H.6 & 5). The default multiplier is x4, corresponding to no pull-down resistors.

2.4 Generating The Clock

2.4.1 Designing Clock Circuits

There are two basic choices of clock source, the crystal or a self-contained oscillator module. The design of a traditional clock circuit is not a trivial task and requires some care to get reliable start-up when production tolerances and component ageing is taken into account. The 166 is family is no more demanding in this area than any other microcontroller so the hints given in the following section should be considered for any clock circuit design.

2.4.2 Oscillator Modules

Using an oscillator module is very simple as the operating point calculations will have been taken care of by the manufacturer. The EMC emissions are also less as the metal case is always grounded and there will be a shorter signal path. The only critical factor is that the rise and fall time should be less than 5ns. There is a small price

Test Configuration

Fundamental Mode

166 Designer's Guide - Page

premium over the conventional crystal-plus-capacitors approach but this is not great. Indeed, it is only if the microcontroller is going to be used in a 25k+ per annum quantity that the extra cost of a module is going to become significant. The oscillator output should be connected to the 166's XTAL1 pin.

2.4.3 Designing Crystal Oscillator Circuits

The traditional clock circuit usually comprises a parallel resonant fundamental crystal plus two capacitors and a resistor to limit the current through the resonant device.

The selection of the series resistor value Rx must be made so that the oscillator is guaranteed to start within 0.1ms to 5ms, even after mass production tolerances and ageing effects are taken into account. It must also be chosen to keep the power drive level of the crystal between typically 50uW to 800uW, although the device's datasheet should be consulted.

The process of defining RX and the "load capacitors", CX1 and CX2, is aimed at making sure that there is sufficient current flowing through crystal to drive the on-chip inverter that produces the oscillation. The crystal has a characteristic resistance known as the "equivalent series resistance" or "load resonant resistance", which is a combination of its typical resistance (R1typ) and residual capacitance (C0typ), as stated by the manufacturer, plus reactive effects due to the oscillation and the load capacitors CX1 and CX2. This equivalent resistance is given by:

RL = R1typ x (1 + (C0typ/CL)²)

Where: CL = (CX1 x CX2)/(CX1 + CX2) + CS (CS = the stray capacitance of clock circuit)

During this Rx definition phase, a small value resistor, Rq, should be inserted in series with the crystal. The temporary resistor, Rq, must be increased until the oscillator does not start automatically when the 166 is powered up for different values of load capacitor. This value will be Rqmax. For ease of adjustment, an RF potentiometer can be used but you must bear in mind that this is RF engineering and the value of Rq so arrived at must be verified by replacing the potentiometer with an equivalent SMD or RF resistor and repeating the test. The ratio of Rqmax to the equivalent series resistance is the "Safety Factor" and is a measure of how much spare capacity there is in the circuit to overcome tolerance and ageing effects:

Safety Factor (SF) = Rqmax/RL

A current probe should be used to measure the peak-to-peak current (Ipp), converted to drive power with:

Pw = (Ipp x Ipp x RL)/8

The resulting relationships between safety factor and power drive versus load capacitor value should be plotted on graph paper. From both curves, a value of load capacitors that gives the best combination of safety factor and power consumption can be chosen.

2.4.4 Crystal Oscillator Components Test Procedure

1. Select a value for Rx

2. Fit load capacitors, CX1 and CX2 of the value given in the table

3. Adjust Rq until oscillation will not self-start in less than 5ms when the 166 is powered-on. Record this resistance in a table, similar to than given below:

Test Record For Rx = 680R

CX1 = CX2 Ipp Pw Rqmax

0.0pF 0.002075 25.27 150

2.2pF 0.002300 26.09 500

4.7pF 0.002550 27.48 750

10pF 0.003100 32.17 600

22pF 0.004550 51.59 250

47pF 0.008000 122.50 60

4. Select the next value of load capacitors and repeat steps 2 to 4

Now pick another value for Rx and repeat the procedure.

166 Designer's Guide - Page

After a number of Rx values have been tested in this way, the resulting curves should be examined for the resistor and load capacitor values that give the best safety factor at a power level of 50uW-800uW. Having selected the values, the resistor Rq should be removed and the current and start-up times rechecked.

If an adequate safety factor cannot be achieved, particularly above 20MHz, it is possible to add a series 1-10M resistor to increase the feedback to the XTAL1 input pin. Otherwise, a third-overtone mode must be used. Unfortunately, the component selection process is more complex and when it is considered that an extra inductor and capacitor will be required to damp-out the fundamental frequency, it might prove more cost-effective to use an oscillator module!

To simplify the selection process, Hitex can provide an EXCEL spreadsheet template that automates the conversion of test results and characteristic curve plotting, as illustrated below:

The clock circuit will in fact produce two drive currents: until the RESOUT pin goes high, (after the EINIT instruction is executed), the current drive of the clock will be greater to ensure that the CPU is less likely to be upset during the potentially noisy initialisation phase. It also helps to overcome the initial high resistance of the crystal during the startup phase.

Typical load capacitor values are 22pF with Rx around 1K. However, you should not rely on these and for any serious project, the selection procedure given earlier should be followed.

2.4.5 Typical Component Values

The table gives typical values for a selection of commercially available crystals. These must not be used as they stand without testing - we deliberately have not given the brand names for this reason! It is recommended that you compare the characteristics C0typ, R1typ (in the shaded panels) and fundamental frequency of your device with the examples in the table and pick the one which is closest.

Make up a clock circuit using the load capacitors CX1 and CX2 plus series resistor Rx and perform the check of safety factor and drive power given in the previous section. The chances are that the results will be within limits but it would be very embarassing if reliability problems occur in production and you have to admit that you never verified the component values in the clock circuit....

Region Of Acceptable

Safety Factor

Excel Spreadsheet For Component Evaluation

Region Of Acceptable Power Level

166 Designer's Guide - Page

2.4.6 Laying Out Clock Circuits

The layout of the clock circuit can be critical in determining both the RF emissions and susceptibility of a 166 design. As with any high frequency system, the loop areas must but kept as small as possible, meaning in practice that all components must be located as close as practicable to each other and the XTAL1/XTAL2 pins on the CPU. With metal-canned crystals, the case should be soldered to a grounded area on the top surface plus be connected to the main ground layer in a multi-layer board. This will also improve the mechanical stability of the part.

Inductive and capacitive coupling can be reduced by eliminating parallel runs of tracks either on the same layer or between layers. The grounding of the load capacitors should have a generous track width and be connected directly to the ground layer to avoid ground loops which are a major source of RF emissions.

2.4.7 Symptoms Of A Poor Clock

It must be emphasised that the series resistor value must be chosen with care. An incorrect value is unlikely to result in a total CPU failure, or even erratic operation of the core, timers or A/D converter. However, the first

Typical Crystal

Characteristics

And Component

Values

Sample Oscillator

Circuit Layout

166 Designer's Guide - Page