3.4 External Memory Access Times (167 Derivatives Only)

As a potentially very fast CPU, the 167 can require fast memories to run at full speed, especially if the newer 25MHz versions are used. The minimum access times for EPROMs and RAMs is easily found via the formula:

ROM Access Time (ns) = 2000/Fcpu - 30 (Fcpu = CPU frequency in MHz = 20MHz)

At 20MHz, the minimum access time is 2000/20E6 -30 = 70ns. This assumes that there are no external signal delays through address decoders etc.. If the 167's own chip selects are being used to enable memory devices directly via their /CE pins, the 20ns delay due to the internal address decoding logic must be subracted from the minimum access time of 70ns. This means that when used as address chip selects, the memory access time is 50ns at 20MHz. If the integral chip selects are configured (by software) instead as READ or WRITE chip selects, the 20ns chip select delay does not influence the memory access time - see section 4.3 "Read/Write Chip Selects"

With common, low-cost FLASH EPROMs being 90ns, it can be seen that the maximum clock frequency is 16.67MHz. With a typical external memory decoder propagation delay of 5ns, the maximum clock frequency is a convenient 16MHz.

It is possible to make the 166 insert waitstates itself to allow slower memories to be used but this should generally be avoided. Tests have shown that it is more efficient to reduce the clock speed rather than insert waitstates. In the usual case of either 16MHz with no waitstates or 20MHz with a waitstate, there is a 3% processing performance advantage from choosing the former. Waitstates are the enemy of the 167!

If the PLL is being used to generate the CPU clock, the small jitter present in the frequency must be taken into account as it will tend to decrease the required access time for the memory devices. You are advised to refer to page 44 of the 167 data sheet for more information on this subject. If ALE lengthening, READ/WRITE delays or memory tristate times are being used, you must account for these also. However, in the majority of present-day designs, they are not used.

3.5 Expanding The Basic 166's Memory Space

The 256kb addressing capability of the 166 derivatives can be easily expanded using "bank-switching" so that 1MB can easily be reached - the 16MB of the 167 cannot realistically be duplicated! Here, some ordinary port pins, such as P2.14 and 2.15 can be used as additional address lines A18 and A19. The C compiler kits can be made to automatically drive these pins so that virtual addresses can be assigned to code and data. As far as the user is concerned, this is totally transparent and the 166 can be treated as a 1MB address space processor.

There are some side effects to this that must be taken into account: as 166 port pins are inputs after reset, the A18 and A19 "address" lines will be high, implying a virtual address of 0xC0000. The user must therefore make sure that there is a JMP vector to the program start at this address.

There is only a software overhead due to bank-switching when code or data is accessed in other than the current bank. This amounts to around 1us, every time a change is required. Careful software design, particularly in the linker input file, will make this a rare condition.

Bank-Switched 166 Memory Expansion

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4. Interfacing To External Devices

4.1 The Integral Chip Selects (167/5/4/3/1)

The 167 derivatives have IO pins on port 6 that can be used as chip selects, each with software-programmable registers that allow the user to set the address range over which the chip select will become active. In addition, the bus width, number of waitstates etc. can also be setup. There are five BUSCON registers that control the latter while there are four ADDRSEL registers that set the address range. Chip select 0 (/CS0) is port 6.0, /CS1 is port 6.1 and so on.

Chip Select Pin Name Control Register Address Range Register

/CS0 P6.0 BUSCON0 Not Applicable

/CS1 P6.1 BUSCON1 ADDRSEL1

/CS2 P6.2 BUSCON2 ADDRSEL2

/CS3 P6.3 BUSCON3 ADDRSEL3

/CS4 P6.4 BUSCON4 ADDRSEL4

Immediately after RESET on an external memory system, only chip select 0 is active and until programmed otherwise, will be active over the entire memory space of the processor. The CPU will have read the pull-down resistors on port 0 to determine how many further chip selects are required. In most designs, /CS0 will be connected to the chip enable of the EPROM. The bus type for this initial configuration is read from the pull-down resistors on port 0, outlined in section 3.2.2 . Before starting the program proper, the corresponding ADDRSEL and BUSCON registers for the chip select pin that is to be used must be set up. /CS0 is active over any memory address ranges not covered by chip selects 1-4 and thus sets the main bus mode.

The base address and range of a chip select are subject to the limitation that the base address must be an integer multiple of the range. For example, a chip select with a range of 128kb must start on a 128kb boundary and a chip select of 1MB must start at 0x100000 and so-on. The smallest range size is 4KB.

167 Integral Chip Selects

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From 167 stepping level "BA", the chip selects may overlap, i.e. /CS2 may define a range within that already allocated to /CS1. The chip selects are internally prioritised so that the chip select with the highest number will overrule any other chip select. Only certain combinations of chip selects are permitted and it is important that the user only configures /CS4 to coincide with /CS3, and /CS2 to coincide with /CS1. An overlap of a /CS4 region with /CS2, for example, will cause a bus error and incorrect operation. Section 8 in the 167 user manual gives further details on the chip selects.

4.2 Setting The Number Of Chip Selects

As with the number of segment address lines, the number of chip selects is set by the pull-down resistor pattern on P0.10 & P0.9. The user can select 5, 4, 3, 2 or none. Chip selects not enabled by this are available for use as simple port 6 IO pins.

4.3 READ/WRITE Chip Selects.

In cases where an external address decoder is being used in preference to the integral chips selects that have been disabled via the port 0 resistors, the ADDRSEL and BUSCON register associated with each chip select can still be used to control the bus width, waitstates etc. for each memory region externally created. Thus a 256KB block of 8-bit RAM at address 0x80000 could still be described by, for example, ADDRSEL2 and BUSCON2 but an external address decoder would provide the chip select signal; the chip select pin /CS2 remains inactive thoughout and carries on as a simple IO pin.

The chip selects can save a lot of glue logic but there is an internal delay between the address valid and the falling edge of the chip selects of up to 20ns. Thus if /CS0 is used to enable the EPROM via its /CE pin, an extra 20ns must be allowed for when calculating the required access time. This delay is relatively unimportant for RAMs as they are generally faster for a given price than EPROMs. The 90ns FLASH EPROM is cheap but 70ns are not, so the extra 20ns delay can increase cost. Fortunately, there are better ways of using the chip selects which do not require faster memories and these will be covered in the next section.

The default mode for the chip selects is to become active when the address range given by SFR "ADDRSEL1/2/3/4" is addressed. However, it is possible to program them from software to become active (low) when either a READ or WRITE access is made in the defined address range. As the /RD signal is much later in the bus cycle, the delay is not important and does not influence the memory access time. An example might be to connect the /CE for the EPROM to ground so that it is permanently enabled and taking the /CS0 signal to the /OE pin, where the /RD might usually be connected. One of the first actions of the program within the EPROM is to configure the BUSCON0 register to make /CS0 into a "READ" chip select. However due to possible bus contentions, it is recommend that this approach is used only with a demultiplexed bus.

Effectively, the chip select logic internally combines the address /CS signal with /RD so that the chip select pin only goes active when both address chip select and the /RD are asserted. The base address and range over which the READ chip select must be allowed to go active is still set by the ADDRSELx registers. The benefit of doing this is that as the /RD signal is later in the bus cycle, the calculated memory access time of 70ns at 20MHz need not account for any chip select delay.

Address Valid To Chip Select Timing

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It is also possible to configure a chip select as a /WRITE chip select so that the chip select signal is internally gated with the /WR signal. In the example, /CS1 might be connected to the /WR pin on the FLASH EPROM and only be enabled by software when the FLASH is to be reprogrammed. This helps prevent inadvertent writes to the FLASH. If the integral bootstrap loader is used to program external FLASH EPROM at the end of the production line, this trick can be useful.

4.4 Replacing Address Lines With Chip Selects

As has already been mentioned, the chip selects can be used as address lines so that not all of port 4 need be dedicated to use as segment address lines. This is particularly important for the 167CR where the CAN peripheral occupies A21 and A22.

The user need only provide enough segment address lines to allow the largest single memory device to be fully addressed. For example, in a system with a 256K FLASH EPROM and a 128kb RAM, only address lines A0-A17

READ & WRITE Chip Selects

Using Chip Selects As

Extra Address Lines

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are required to access any address in the 256KB range of the device. Here, lines above A17 are redundant and best used as port 4 IO pins. The 128KB RAM can be enabled by /CS1 which can be made to mimic A18, so mapping it to a programmable address above 256k (0x40000). In this case, ADDRSEL1 would be set to make /CS1 become active when the C167 internally generates address 0x40000. /CS2,3 & 4 can create further 256kb memory areas, mapped to any address above 512k that the user chooses, provided it is a multiple of the active chip select size.

A common example of chip select usage is to allow multiple 1MB areas to be created, each attched to a different chip select - hence the 5MB potential memory space of the 167CR when the CAN peripheral is used.

4.5 Generating Extra Chip Selects

A simple 74X138 can be used to give an extra 8 chip selects that are active over a 512kb range. The 167's /CS4 is used to enable a further 8 chip selects by decoding A19, 20, 21. The new selects are delayed by the propagation delay of the `138. They must all use the same bus mode, waitstates etc. as they are all controlled by BUSCON4.

If the upper address lines are not available, then simple port pins can be used. The user must then manually set the port pattern to enable the appropriate chip select. This type of IO-mapped chip select is best reserved for infrequently accessed devices.

74ACT138

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4.6 Confirming How The Pull-Down Resistors Are Configured

RP0 is a special read-only register at address 0xF108 that contains an image of port 0 when coming out of reset. In effect, it allows the programmer to check whether the pull-down resistor settings are correct. A simple bootstrap-loaded diagnostics program available from Hitex makes use of this to verify that new boards are correctly configured.

The fields have the following meanings:

Clock Mode Multiplier Comments

1 1 1 x4 Phase Lock Loop Multiplier

1 1 0 x3

1 0 1 x2

1 0 0 x5

0 X X x1 Direct Drive

Segment Address Lines

1 1 Two A17 - A16

1 0 Eight A23 - A16

0 1 None

0 0 Four A19 - A16

Number Of Chip Selects

1 1 Five /CS4-/CS0

1 0 None

0 1 Two /CS1-/CS0

0 0 Three /CS2-/CS0

4.7 Generating Waitstates And Controlling Bus Cycle Timings

In conventional processors, waitstates required for addressing external devices that cannot cope with the speed of normal bus cycles were generated by a READY signal. The CPU would effectively wait for the external device to signal via the /READY pin, that it was ready to put data onto the bus. This mechanism was and is a source of complexity and hardware debugging problems. To simplify system design, the 166 family can insert waitstates "at source" so that it can extend its own bus cycles in multiples of one state time (50ns at 20MHz) without any /READY. The "MTTC" field in the SYSCON register allows the user to set the waitstates in the 166 while the corresponding field in the BUSCONx registers on the 167 have the same effect. Up to 15 waitstates can be inserted.

Each address region defined by the on-board chip selects can have a different number of waistates programmed from software. The 166 can still use a traditional /READY signal via the dedicated /READY pin. In this case, the waitstates programmed from software will determine the point at which the 167 will start to check the hardware

/READY signal returned from the external device. If the signal is /READY before the software waitstates are completed, the bus cycle will terminate as soon as the waistates are completed. It should be noted that if the CPU is executing from a memory region which has waitstates applied, the worst case interrupt latency time will be extended by the number of waitstates inserted.

For older RAM and other devices, the data float time, i.e. the time for which the memory device drives the bus after the end of a READ cycle, may be extended by 1 waitstate. This will extend bus cycles, resulting the CPU losing around 10% of its performance over a typical instruction sequence. It is very easy to miss this! Modern RAMs are unlikely to require this and so this feature is best disabled. In a similar vein some memory-mapped IO devices such as LCD controllers require both the /READ and /WRITE signals to remain high for a fixed period after the end of a bus cycle. To prevent disturbance by PEC cycles that can occur without any previous instruction FETCH, the ALECTL ALE lengthening control can be used to delay the start of the next bus cycle by 0.5 waitstates.

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5. Interfacing To External Memory Devices

Despite the power of the 166 architecture, the additional hardware necessary to get a 166 up and running is very small. In many applications the large on-chip RAM is sufficient so that only an external EPROM needs to be added to hold the program. The following diagrams illustrate some simple examples of different configurations.

The first two schemes are still comparatively rare, probably due to relatively high cost of true 16-bit memory devices. However recent falls in cost of devices like the IDT71016 are bound to make this high performance and very simple design much more common. The third is an 8-bit non-multiplexed design using 8-bit ROMs and RAMs, much favoured by ex-8051 users.

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5.1 Using Byte-Wide Memory Devices In 16-bit 167 Systems

To successfully use 8-bit RAMs (or a single 16 bit one) the user must remember that the A0 pins on the RAMs go to A1 on the 167. One RAM has its data lines connected to the 167's D0-D7 (LOW) and the other is wired to D8-D15. A0 is effectively redundant in such a configuration. Failure to realise this before commiting to a PCB will result in a lot of track cutting and hand-wiring. You would be amazed at how often we see this mistake! When the CPU reads a word both RAMs are enabled simultaneously by /READ so that the CPU can read D0-D15 in one access across the bus. As the 166 is a 16-bit machine, all read accesses are word-wide, even byte ones - the unwanted byte is simply discarded.

For writes to RAM some means of only enabling one of the RAMs is required, as a byte write to an even location would corrupt the associated odd byte. The traditional method of preventing this is to create individual /WRITE signals for each RAM from /BHE and A0. The 166 does it this way via an external PLD. However the 167 has special /WRITEHIGH (/WRH) and /WRITELOW (/WRL) pins, which are connected to the corresponding /WR pins on the high and low RAMs. To enable this feature, the user must either put a pull-down resistor on P0.8 or write a `1' into the SYSCON, bit-8.

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5.2 Using The 166 With Byte-Wide Memories

The 166 has no WRITEHIGH (/WRH) or WRITELOW (/WRL) signal so a different approach is required to that used on the 167/5. If 8-bit memory devices are chosen that have two chip selects available, then the /BHE (BYTE HIGH ENABLE) and A0 lines can be used to enable either the high or low bank of memories.

Here the A0 and /BHE signals are connected to the active low chip selects on both RAMs. When an even byte is addressed the A0 is low and /BHE is high, so that the low RAM is enabled. On addressing an odd byte, A0 is high and /BHE is low, so that the high RAM is enabled.

A17 goes to the active high chip select so that the RAMs are enabled above 0x20000. It also goes to the active low ROM chip select, mapping it to address zero.

If the RAMs being used do not have two chip select inputs, the /WRL and /WRH can be derived from /WR, A0 and /BHE via the following scheme:

Generating Write High

And Write Low Signals On

The 166

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