CP). The special C166 compiler keyword "USING" performs this. On exit from the service routine the context (register bank) is restored. See the relevant section in the C166 C Language Introductory Guide for more details on handling the stacks.

8.5 Power Consumption

In many projects power consumption is critical, particularly in battery-powered applications. Ultimately it is the "processing power per milliamp" that is important in this situation. When comparing different processors for low-power applications this ratio can be quite difficult to arrive at and is often not taken into account. Most design engineers simply compare the maximum current consumption of competing processors and just choose the one with the lowest figure. However, as hardware engineers, they may not have considered the clock speed required to get the processor throughput needed by the application. Unfortunately this depends on other factors, such as the programmer's skill and the efficiency of the C-compiler. The 165 has a maximum current consumption related to the clock speed by the formula:

Icc = 10ma + 4 * Fosc

For example, if the 165 throughput is double that of another CPU, the clock can be reduced by a factor of two to get the same performance. The current will then reduce to 55% of the orginal figure. Thus the "C-lines per second per milliamp" of the 165 is better, making it a good choice for the application. In practice, the 165 is around 3 times as fast when programmed in C than most competitors, making it a very low current device, despite what the databooks seem to imply!

By way of an example, here are some run times for a benchmark program stated alongside the current consumption of the CPU at the time. Although we measured these with a current probe, we have taken the manufacturers' own maximum figures to make it fair.

CPU Speed Runtime Current Idle Current

——————————————————————————————————————————————————————

165: 16MHz 10.333s 74mA 21mA

80C188EB: 16MHz 32.718s 93mA 63mA

Assumptions: (i) 165 max current is 90mA at 20MHz (74mA at 16MHz)

(ii) 80C188EB max current is 93mA at 16MHz, as stated by the databook

The 165's typical current consumption is around 45mA when we measured it at 16MHz, despite what the databook says! It can be seen that although the current consumption of the two devices compared is similar, the CPU throughput of the 80C188EB is about 1/3rd of the 165's. If the clock speed is reduced by 1/3rd to compensate then the following is observed:

CPU Speed Runtime Current Idle mA

————————————————————————————————————————————————————

C165: 5.05MHz 32.718s 30mA 8mA

80C188EB: 16MHz 32.718s 93mA 63mA

To put this in perspective, if the clock of the 165 was reduced to 5.05MHz to yield approximately the same throughput as the 80C188EB, the current consumption would be around 30mA; less than 1/3 of the 188's. The 165's idle power consumption would be around 8mA. This rough calculation is valid as the 165's current consumption is approximately proportional to its clock speed, by the formula given above. It can be seen that it achieves a very good performance-per-milliamp - the fact that several battery-powered hand-held instruments already use the 166 family shows that other people have done these calculations as well!

8.6 Understanding The DPPs

8.6.1 166 Derivatives

The 166 uses the concept of 16KB long data "pages" to allow the accessing of data. Memory addresses that are within a page may be addressed by 2-byte (100ns) instructions like MOV R1,8000H. By limiting the addressing capability of individual assembler instructions to an address within a page, execution speed can be improved over other CPUs which allow 32-bit address accesses to be made in one instruction.

166 Designer's Guide - Page

The 166 actually only deals in 14-bit addresses that are in reality offsets from the base address of the current 16KB data page. The top two bits of any 16-bit address indicate to the CPU which DPP is to be used to form the physical address that will appear on the 166's address bus. For example, the assembler instructions below will use DPP2 to form the physical address as the top two bits of the number `#8002H' are `10', i.e. 2, indicating that the page number held in DPP2 must be used:

MOV            R4,#8002H  ;
MOV            R1,[R4]    ;  Access address indicated by the contents of R4

If DPP2 contains 2, the base address of the page will be 4000H x 2 = 8000H. Thus the address placed on the bus will be: 4000H x 2 + 0002H = 08002H. However if DPP2 = 8, the instruction sequence would access address: 4000H x 8 + 0002H = 020002H

Thus it can be seen that the page indicated by DPP2 can be placed anywhere in the 256KB memory space. In effect, the top two bits of the address cause an address translation. To use DPP1 for the access, the instruction sequence would look like:

MOV            R4,#4002H  ;
MOV            R1,[R4]    ;  Access address indicated by the contents of R4

Now the top two bits of `#4002H' are `01', indicating that DPP1 should be used. The precise mechanism that decides what the top two bits of the address are need not be of concern to the programmer, as they are calculated by the linker. Further information on using the DPPs can be found in the Hitex publication "An Introduction To Using The C Language On The 166 Family".

In the case where a check sum is to be performed over a 128KB EPROM, one of the DPPs - usually DPP0 - has to be incremented every time a page boundary (0x4000) is crossed.

It must be stressed that the use of the DPPs is totally transparent to the C programmer under normal circumstances and need only be taken into account when absolute maximum speed is required. It should not be confused with the simple paging schemes used on some smaller HC11/12/16 type processors! As far as the user is concerned, the DPP concept should be considered as a means of creating 16KB "islands" of very fast access in the 166 memory space.

8.6.2 167 Derivatives

When the 167 expanded the memory space to 16MB, a second data addressing mode was added that was more suitable to coping with potentially very large data objects. This allowed 32-bit addresses to be handled directly so that the 167 could be regarded as having a 32-bit linear address space. Inevitably the speed of access is reduced to a small extent but it must be borne in mind that the 166's native addressing mode is exceptionally fast! As an example, using the 167's linear addressing mode, a 128KB block copy can be performed in 66ms at 20MHz.

The DPP mechanism was retained to permit the user to create the 166's 16KB regions of very fast access within an overall linearly-addressable memory space. The programmer therefore has the option of being able to create variables that can be addressed by the optimal method - in simplistic terms "small and very fast" or "big and fast".

166 Designer's Guide - Page

9. Allocating Pins/Port Pins In Your Application

It is often the case that at the point when the user has the least knowledge of the capabilities of the peripherals, the most critical choices regarding pin allocation have to be made, i.e. at the beginning of the project! Frequently pin assignments have to be changed in light of experience gained. The following examines what sort of functions each peripheral and then port pin is suited to. This should allow you to make the right choice for the particular signals in your application

9.1 General Points About Parallel IO Ports

Each port (except P5) can be configured to be input or output, with any combination of inputs or outputs on the same port. After reset all the port pins are high-impedance inputs and it is up to the user to program the appropriate DPx registers to turn individual pins into outputs.

When configured as outputs, ports P2,3,6,7 and P8 can be either constructed from conventional push-pull drivers or open drain via the ODPx registers. The former can drive a pin either high or low, whereas the open drain type can only pull a pin low against an external pull-up resistor. This method allows an easy wired-AND and can save on external logic. The default mode is push-pull outputs.

Ports P2, P3, P7 and P8 can in addition be programmed as inputs with custom input characteristics. The default is TTL-like input thresholds but the PICON registers allow CMOS inputs with hysteresis to be chosen. This can be useful in noisy environments or where the input level changes very slowly. Where the pin has an alternate function, the default state of the pin is a high impedance input. The alternate function is only connected to the pin as a result of the user setting up the peripheral. If the peripheral is intended to, for example, drive a square wave onto a pin, it is always the user's responsibility to set that pin to be an output, using the appropriate DPx register. For example, P3.10 is the serial port 0 TX pin. It only assumes this function if the user has correctly configured the S0CON UART control register and then set DP3.10 to 1 to connect the UART output to the P3.10 pin..

9.2 Allocating Port Pins To Your Application

With a little ingenuity, it is possible to use 166 family peripherals to generate or measure any sort of digital signal. Most peripheral blocks are able to perform even quite complex tasks without any CPU intervention - the Peripheral Event Controller (PEC) is a great help in this area. The following survey of the available port pins can only suggest some basic peripheral configurations and functions. If you are trying to use a particular peripheral to solve a problem in your application, please feel free to email us with a description of what you want to do and we'll try to come up with something!

9.3 Port 0

In all ROMless 166 family designs this port forms the data bus in non-multiplexed configurations or the combined address/data bus in multiplexed systems. In the FLASH device this is a general purpose bi-directional IO port. As has already been said, single-chip users are strongly advised to leave this port free for use as an external bus. On the 166 the /BUSACT pin is low to enable port 0 as the bus.

When the external bus is active, port 0 hosts user-defined patterns of pull-down resistors to determine the characteristics of the bus, number of chip selects, PLL clock multiplier etc.. If an 8-bit data bus is being used in a non-multiplexed design, the 166 does not allow the upper 8-bits of port 0 to be used as IO. However the division of P0 into P0L (LOW) and P0H (HIGH) allows the spare upper 8-bits to be used as IO. Care should be taken that any IO device attached to P0.15 does not pull the pin down sufficiently to make the CPU think that the PLL clock multiplier is not to be used, when it reads the pin coming out of reset.

Port 0 Pin Allocations:

P0.0 - D0/AD0 : P0.15 - D15/AD15

9.4 Port 1

In ROMless 166 family designs using the non-multiplexed bus modes, this port forms the address bus in non-multiplexed configurations. In the FLASH device this is a general purpose bi-directional IO port.

166 Designer's Guide - Page

9.5 Port 2

9.5.1 The CAPCOM Unit

Besides being general purpose IO pins, port 2 is equipped with a 16 channel capture and compare (CAPCOM) unit, consisting of two 16-bit timers and 16 data registers. It is a means of either generating precisely-timed pulses or measuring times between events. It is analogous to the "time-processor units" found on some older CISC processors, except that it is integrated into the CPU core, rather than being bolted on as a separate processor. As the 166 core is very fast and able to react to real-time events very quickly, the entire CPU is effectively available to process data connected with the CAPCOM unit. This is in marked contrast to TPU-equipped processors where only a simple microcode-driven core is available.

It consists of two 16-bit timers and 16 data registers that can either "capture" the value of one of the timers or be made to toggle a pin when the contents of a particular register matches ("compares") that of the chosen timer. Each pin has one CAPCOM register allocated to it. Channel 0 is on P2.0, channel 1 is on P2.1 and so-on. The capture function allows the time at which an external port pin level transition occurred, referenced to a 16-bit timer. The edge-sensitivity can be +ve, -ve or both. Through this a wide variety of pulse measurement tasks can be realised. The compare function allows a pin to be toggled or put into a defined state when a timer reaches a defined value.

The input of the timers is a 0.4us - 51.2us (20MHz) clock, derived from the main CPU clock. Timer T0 can additionally be clocked by an external signal of the user's own choosing, applied to the T0IN pin. This gives rise to some interesting possibilities in applications such as engine management or motor drives, when pin transitions must be created at precisely defined angular positions of a shaft or rotor. Effectively, when compare registers are assigned to T0, being clocked by edges from an armature position sensor, the commutation of a DC motor function can be carried out automatically.

The creation of a software UART is very simple: the capture function for a partcular pin can be made to both detect the falling edge of the start bit and then clock the bit stream into a variable.

The simplest use of the compare capabilities is the generation of pulse-width modulation (PWM). When running in "edge-aligned" mode, 8-bits resolution at a 9.6kHz carrier can be produced, while an 8-bit "centre-aligned" PWM is possible at 4.8kHz. Applying modulation, usually sinewave, is very straightforward and a complete demonstration CAPCOM three-phase sinewave synthesiser driver is available from Hitex. By adding an external low-pass filter the CAPCOM PWM channels can also be made into very accurate digital to analog convertors.

The power and flexibility of the CAPCOM unit is considerable and it is unusual to find a signal measurement or generation task that it cannot be used for!

While the normal use of port 2 is the CAPCOM unit, the 16 I/O pins can be used as simple interrupt inputs of rising, falling, or both edge sensitivity. The port also hosts 8 very high speed interrupt inputs on P2.8-P2.15, which are sampled by the CPU every 50ns and can guarantee to cause an interrupt within 250ns. The CAPCOM-less 165, 163 and C161 also have these inputs. On the 167, P2.15 is also the optional count input for timer T7.

9.5.2 Time-Processor Unit Versus CAPCOM

A point that is often missed when comparing microcontrollers is that even with the overhead of servicing the CAPCOM unit, the overall throughput of the 166 is still large. If it is conservatively assumed that the 167 CPU is three times the performance of a CISC processor (in reality 3-5 times is usual, depending on the benchmark used) and the CAPCOM service requires 25% of the 166's capacity, the remaining processing power is still more than double that of the CISC. In a "properly" designed 166 system the CPU load due to the CAPCOM is rarely more than 15%.

9.5.3 32-bit Period Measurements

While the CAPCOM is essentially a 16-bit peripheral, it is possible to make a 32-bit period measurement that would ordinarily require 32-bit timers and capture registers. This is achieved by using both the CAPCOM's timers, running half a period out-of-phase to generate the upper 16-bits of the 32-bit value. An application note is available from Hitex to illustrate the techniques involved.

166 Designer's Guide - Page

9.5.4 Generating PWM With The 166 CAPCOM Unit

(i) Asymmetric PWM (edge aligned)

The PWM pin goes on when compare register matches the Timer0 value and goes off when the timer overflows. The PWM period is determined by the value in the T0REL register. A T0REL value of 0xff00 (-255) yields an 8-bit PWM of period 256 x 0.4us. The PWM on edge only moves when the PWM changes, resulting in an increase of harmonics in motor/transformer windings during duty ratio changes.

(ii) Symmetrical PWM (centre aligned)

The PWM pin goes on when compare register matches the Timer0 value. By using the double register compare mode the PWM pin can be made to go low again when the timer is equidistant from the reload start count. This yields a PWM waveform in which both the on and off edges move together. Thus a symmetrical PWM is created. This PWM format is to be preferred for driving inductive loads.

The PWM period is defined by the value in the T0REL register. A T0REL value of 0xff00 (-255) yields an 8-bit PWM of period 256 x 0.4us.

9.5.5 Sinewave Synthesis Using The CAPCOM

It is fairly easy to configure CAPCOM1 to produce the 6 output signals required to drive a three-phase AC induction motor. This is covered in detail in the Hitex application note, "The 166 Microcontroller As A Three Phase Induction Motor Controller", available on request. The 167 can drive two motors simultaneously by using CAPCOM2 as well.

The 164 version is intended specifically for motor drive applications, having three special CAPCOM channels with six outputs which make the implementation of high performance controllers easier. Each channel has a second pin which provides the complementary output for driving bridges with a programmable deadtime offset automatically added in hardware rather than via software, as in the 166/7. The maximum carrier frequency is similar to that found on the 167's dedicated PWM module. For safety trips, the special /CTRAP pin forces all outputs into an inactive state within a few hundred nanoseconds, essential for MOSFET drivers. The input to the unit is usually the CPU clock for 3-phase and stepper motors but can optionally be a position encoder to allow block commutation in DC brushless applications.

9.5.6 Automotive Applications Of CAPCOM1

The one-shot compare mode (mode 1) is useful for generating precisely timed pulses such as are required for fuel injection and ignition control. By driving timer 0 with edges originating from a crankshaft sensor, the compare registers become a means of generating pin transitions at user-defined crankshaft angles.

166 Designer's Guide - Page

Two application notes are available on request, that describe firstly how the CAPCOM can be used to produce 12 sequential fuel injection drives and secondly how it can be used to drive diesel unit injectors.

9.5.7 Digital To Analog Conversion Using The CAPCOM Unit

In PWM mode and with a suitable low-pass filter, the CAPCOM can be used to produce a very accurate A/D conversion. Where the load is inductive the load itself will average the voltage level automatically and no filter is required. In most cases a simple low pass filter, with a cut-off frequency well below the PWM switching frequency, will remove any noise and give a smooth DC level.

As might be expected, the resolution of the PWM-based A/D converter is related to the switching frequency. At 9.6kHz this would be 8-bits, while for 14-bits 152Hz results. In the latter case the cut-off frequency of the filter would need to be around 30Hz. The 167's PWM module can give even higher performance - see section 9.10 on port 7 for more details.

9.5.8 Timebase Generation

Besides being able to either drive port pins or measure incoming pulsetrains, the CAPCOM unit can simply generate interrupts at defined times. Either a conventional interrupt service routine can be called or, more often, a PEC data transfer made.

Scheme For 12 Cylinder

Sequential Fuel Injection

166 Designer's Guide - Page

9.5.9 Software UARTs

It is very easy to add extra UARTs to the 166 family using the CAPCOM unit. A typical single UART will represent approximately a 2% CPU load at 9600 baud, under worst-case conditions. Special software UARTs like a receiver for IRDA reduced duty-ratio infra-red links are very simple to implement. Here is a simple conventional NRZ receive routine in `C' on port 2.8:

/*** UARTA Receive Interrupt ***/
// Detects falling edge of start bit. Waits one and a half bit periods until centre of 
// bit 0, then waits one period. Sample input pin every bit period and count bits shifted
// in. After 8-bits revert to input capture mode for next start bit 
/***/ 

void uartA_rx_interrupt(void) interrupt 0x18 {

   if(!start_bit_detect_mode) { // If jump not taken, time is saved???

      /*** Now in centre of bit period so sample uartA pin ***/

    rxA_shift_reg_input = uartA_input_pin ;
      rxA_shift_reg = rxA_shift_reg >> 1 ;

      CC8 += SABRG ;   // Make interrupt one bit period later

      uartA_bit_count— ;
      if(Z) {
        uartA_bit_count = 9 ;
        start_bit_detect_mode = 1 ;  // Enable CC8, capture neg edge, T0, to
                                      // find next start bit
        SARBUF = rxA_shift_reg ;  
        SARIR = 1 ;     // Set dummy receive interrupt pending flag
         }
      }
   else {

      /*** Start bit detected... ***/

      CC8 += SABRG + SABRG/2 ;  // Wait 1+1/2 bits until 
                                // first input pin sampling point for bit 0
      start_bit_detect_mode = 0 ;  // Enable CC8, compare mode 0, T0                 
      }
   }

It should be stressed that even with 4 software UARTs running on the CAPCOM unit, this would represent a 10% CPU load. If the 166 is 20 times faster than a 12MHz 8032, then even with the overhead of software UARTs, you would still have 18 times the performance - hardly a big issue!

If 16 channels of CAPCOM are not enough, the 167 has another 16....

166 Designer's Guide - Page

9.6 Port 3

In addition to providing general purpose I/O, this port is connected to the GPT1 and GPT2 timer blocks. These 6 timers can be combined in various ways to implement gated timers, counters, input capture, output compare, PWM and pulsetrain generation, plus complex software timing functions. The 165/3/1 have no port 2 CAPCOM unit and so these general purpose timers are of special significance. They allow the 165/3/1 to generate and detect real-time events, despite their more microprocessor-like appearance. In essence the 165, 163 and 161 are very similar to an 8032 except they are 20 times faster and, indeed have proved to be popular with 8032 users as an easy performance upgrade.

P3.1 - CAPCOM Timer0 count input (166/7 only)

P3.2 - Timer 6 toggle latch output

P3.3 - Capture of timer5 input/reload of timer 6 input

P3.4 - Timer3 count direction control

P3.5 - Timer4 count/gating/reload/capture input

P3.6 - Timer3 count/gating input

P3.7 - Timer2 count/gating/reload/capture input

P3.8 - 166 Serial port1 transmit

P3.8 - 165/7/1 Synchronous serial port master receive/Slave transmit

P3.9 - Serial port1 receive

P3.9 - 165/7/1 Synchronous serial port master transmit/Slave receive

P3.10 - Serial port0 transmit

P3.11 - Serial port0 receive

P3.12 - Bus high enable or /WRH

P3.13 - Synchronous serial port clock

P3.14 - READY

P3.15 - System clock output

9.6.1 Using GPT1

GPT1 consists of three 16-bit timers (T2, T3 & T4) plus a number of I/O pins. It can be used to make period measurements, generate pulsetrains or PWM. Like the CAPCOM unit, it is based on a maximum input frequency of 2.5MHz. The T2IN, T3IN and T4IN input pins can be used as clock sources for their respective timers. T2IN and T4IN are also able to trigger a capture of the free running timer 3. If the timing functions are not required, the GPT1 input pins, T2IN, T4IN and T3IN, can be used to generate interrupts. There are dozens of different ways of using GPT1 but what follows are typical applications. Ones marked with an `*' are available as application notes from Hitex.

Some typical GPT1 applications are:

PWM driver for DC motor drives*

X-Y trackerball input position detector*

Timebase generator*

33-bit period measurement

Missing tooth detector*

Automatic baudrate detector up to 115.2kBaud*

Quadrature encoder input - provides speed and direction of quadrature input with zero CPU overhead*

void init_quad_decoder(void) {

   T3CON = 0 ; 
   T3UD = 1 ;       // If T3EUD pin high then T3 counts up
   T3UDE = 1 ;
   
   T2CON = 0x0029 ; // Capture T3 to T2 on T2IN channel A +ve edge   
                    
   T4 = 0x8000 ;    // Load T3 with 0x8000
   T4CON = 0x0023 ; // T4 reloads T3 on T4IN channel B +ve edge
                    // Channel A -> T4IN and T3EUD   
                   // T4 holds signed value of angular velocity
   T3R = 1 ;        // Start T3                                                                                                                           
   }

166 Designer's Guide - Page

9.6.2 Using GPT2

This is a block of two 16-bit timers that can operate at up to 5MHz on a 20MHz CPU. The input clock can be a prescaled version of the CPU clock or an external input signal, up to 5MHz. Like GPT2, the timers can be concatenated to produce a 32-bit timer. However it can do some very clever tricks, such as the multiplication of an input frequency applied to the CAPIN pin or period measurement with zero CPU intervention.

Some typical GPT2 applications are:

Timebase generation*

Pulse generation

Time-between-edge measurements*

Two-channel software UART*

TV line capture and buffering*

Automotive missing tooth filler*

Pulse position modulation receiver for TV remote control*

9.7 Port 4

A general purpose digital I/O port whose two bits are the A16 and A17 address lines in segmented designs. In the 165/7 it forms the upper 8 address lines, A16 - A23.

9.7.1 Interfacing To CAN Networks

The CAN peripheral's TX and RX alternate functions of P4.5 and P4.6 may appear to limit the addressing range of the 167 to A0-A19, i.e. 1MB. This is not the case as in fact up to 5MB can be addressed - see section 4.4 for details. A simple CAN drive chip such as the 82C250 is attached to the 167, as shown below:

This is a very simple interface and does not provide any significant galvanic isolation between the CAN physical layer and the 167. It assumes that the 167 system will provide the power for the entire network via the Vcc and GND pins on the 82C250. The potentiometer on the RS pin sets the rise and fall times of the CAN driver, so that at lower baud rates the RFI emissions can be reduced. For the fastest edges required for 1MB/s operation, the RS pin should be grounded.

Simple CAN

Interface

Opto-Isolated

CAN Interface

166 Designer's Guide - Page