Despite the genuine 10-bit resolution, the 167’s analog inputs can be easily protected against out-of-range voltage inputs as might occur under a fault condition in a real system. Clamping diodes allow a simple series resistor on each analog input to provide a good level protection against excessive voltage of either polarity.

Unlike many microcontroller A/D convertors, the total unadjusted error (TUE) on any input is guranteed even if an unselected channel has a fault condition voltage of over 5v or under 0v applied to it. Under these conditions, most convertors will start to give erroneous readings on other channels, which can have unsafe side-effects as from software, it is very difficult to detect a loss of accuracy. The channel with the fault will read as either 0x0000 or 0x03FF for under- and over-voltages respectively.

The only requirement that must be satisfied to allow the continued correct operation of the fault-free inputs is that the sum total of the fault current flowing into any two unselected analog channels must be less than 10mA. A simple current-limiting resistor can thus prevent the fault affecting other channels.

The series protection resistor (Rap) to be added to the analog inputs can be easily calculated by:

Rap =  (Vmax – Vcc)/Imax
   

Where: Vmax = maximum fault voltage & Imax = maximum permissible current flow

For an automotive application where a common fault condition voltage might be 14v, the series resistor would be around (14v – 5v)/0/010 = 1K0. Of course, this additional resistance will have to be added to the source resistance of the analog signal source itself and it is important to ensure that the sample time is long enough to guarantee a stable voltage on the sample-and-hold capacitor, as outlined in below.

The 167 has some additional modes such as “wait for ADDAT read-mode” and “channel injection” mode. The former inhibits further conversions until the last result is read so that unused conversion data is not accidently over-written. The channel injection feature is aimed at allowing analog conversions to be made coincident with some event which is asynchronous to the software execution or the normal operation of the convertor. With the ADC being able to automatically scan through a number of channels continuously, making a conversion of a specific channel that is not included in the sequence is taken care of by “Injecting” a conversion by setting the ADCRQ bit. The ADC will finish any conversion that was in progress due to the autoscan mode and make a fresh conversion of the channel specified in the top four bits of ADDAT2 and placing the result in the lower 10- bits of the same register. The autoscan process then resumes. The user must ensure that the wait-for ADDAT-read mode is activated.

The most important use of the injection mode is to make a conversion of a specified channel in response to a level transition on the CC31 port pin (P7.7). Typical examples of where this is useful are the crankshaft-synchronised reading of the inlet manifold pressure in an engine management system or the reading of current in the windings of a motor drive at a specific rotor angle.

It is possible to alter the apparent input resistance of the analog inputs to allow a better match to the internal resistance of the signal source that is driving them. Sources that change rapidly and that are to be read frequently require a fast conversion time but this will reduce the time available to charge the sample-and-hold (SAH) capacitor in the A/D convertor itself. Thus such signal sources must have a low internal resistance if the voltage level on the sample-and-hold capacitor is to be fully charged and stable by the time the conversion begins. If the signal can be converted more slowly this requirement is relaxed as the sampling time can be set to a larger value. Thus the internal resistance of the source can be greater without loss of accuracy.

Of course, extending the sampling time does not physically alter the input resistance as it is always several megohms. As the sample-and-hold appears to be a simple RC filter whose series resistor is the internal resistance of the source, it is just a matter of making sure that there is sufficient current drive in the signal source to charge up the sampling capacitor before the conversion begins.

The user must also consider the internal resistance of the analog reference voltage source applied to the Varef pin on the 167. Again, the reference voltage source must be able to fully charge the input capacitance of this pin within one conversion clock period.

Analog To Digital Convertor Voltage Sources And Resistances

The ADCTC and ADSTC bits in the ADCON A/D convertor control register allow the user to easily alter the rate at which the convertor hardware is clocked and thus the length of the sampling time (for SAH capacitor charging) and the conversion phase. The basic timing of the A/D unit is the conversion clock and as the sampling clock is derived from this, the choice of sampling and conversion time is not unlimited. The next table gives the possible legal combinations of conversion and sampling times with the maximum signal and reference internal resistances that are acceptable in each case.

Default Configuration At CPU Clock = 20MHz (highlighted cell)

It can be seen that at the (default) fastest combined sampling and conversion time of 9.7us, the signal source resistance must be less than 3K3 Ohms to ensure complete charging of the sampling capacitor. At the other extreme, with a sampling time of 38.4us (resulting in an overall conversion time of 72.1us), the source resistance can be up to 116K. If a series protection resistor is being used, the figure in the table for the signal source resistance must be reduced by the resistor’s value as it is effectively in series with the source’s own internal resistance.

As these timing characteristics are programmable on-the-fly in software, it is entirely possible to make special settings to the ADCTC and ADSTC bits prior to the conversion of any channel which has a much higher source internal resistance than the others. Note that all timings are reduced by 20% at a CPU clock of 25MHz.