166 Derivatives

The 166 uses the concept of 16kb long data “pages” to allow the accessing of data. Memory addresses that are within a page may be addressed by 2-byte (100ns) instructions like MOV R1,8000H. By limiting the addressing capability of individual assembler instructions to an address within a page, execution speed can be improved over other CPUs which allow 32-bit address accesses to be made in one instruction.
The 166 actually only deals in 14-bit addresses that are in reality offsets from the base address of the current 16kb data page. The top two bits of any 16-bit address indicate to the CPU which DPP is to be used to form the physical address that will appear on the 166’s address bus. For example, the assembler instructions below will use DPP2 to form the physical address as the top two bits of the number ‘#8002H’ are ‘10’, i.e. 2, indicating that the page number held in DPP2 must be used:

If DPP2 contains 2, the base address of the page will be 4000H * 2 = 8000H. Thus the address placed on the bus will be: 4000H * 2 + 0002H = 08002H. However if DPP2 = 8, the instruction sequence would access address: 4000H * 8 + 0002H = 020002H

Thus it can be seen that the page indicated by DPP2 can be placed anywhere in the 256kb memory space. In effect, the top two bits of the address cause an address translation. To use DPP1 for the access, the instruction sequence would look like:

Now the top two bits of ‘#4002H’ are ‘01’, indicating that DPP1 should be used. The precise mechanism that decides what the top two bits of the address are need not be of concern to the programmer, as they are calculated by the the linker. Further information on using the DPPs can be found in the Hitex publication “An Introduction To Using The C Language On The 166 Family”.

In the case where a check sum is to be performed over a 128KB EPROM, one of the DPPs - usually DPP0 - has to be incremented every time a page boundary (0x4000) is crossed.

It must be stressed that the use of the DPPs is totally transparent to the C programmer under normal circumstances and need only be taken into account when absolute maximum speed is required. It should not be confused with the simple paging schemes used on some smaller HC11/12/16 type processors! As far as the user is concerned, the DPP concept should be considered as a means of creating 16kb “islands” of very fast access in the 166 memory space.

167 Derivatives

When the 167 expanded the memory space to 16MB, a second data addressing mode was added that was more suitable to coping with potentially very large data objects. This allowed 32-bit addresses to be handled directly so that the 167 could be regarded as having a 32-bit linear address space. Inevitably the speed of access is reduced to a small extent but it must be borne in mind that the 166’s native addressing mode is exceptionally fast! As an example, using the 167’s linear addressing mode, a 128kb block copy can be performed in 66ms at 20MHz.

The DPP mechanism was retained to permit the user to create the 166’s 16kb regions of very fast access within an overall linearly-addressable memory space. The programmer therefore has the option of being able to create variables that can be addressed by the optimal method - in simplistic terms “small and very fast” or “big and fast”.