iLLD_TC27xC
1.0
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Asynchronous Block Configuration Register - Asynchronous Block Bypass
Definition in Ifx_MSC.ABC.B.ABB.
enum IfxMsc_ClockSelect |
Asynchronous Block Configuration Register - Clock Select
Definition in Ifx_MSC.ABC.B.CLKSEL.
Downstream Control Enhanced Register - Command-Data-Command in Data Repetition Mode
Definition in Ifx_MSC.DSCE.B.CDCM.
Enumerator | |
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IfxMsc_CommandDataCommandRepetitionMode_disabled |
Disables the automatic insertion of data. |
IfxMsc_CommandDataCommandRepetitionMode_enabled |
Enables the automatic insertion of data. |
Interrupt Control Register - Command Frame Interrupt Node Pointer
Definition in Ifx_MSC.ICR.B.ECIP.
Number of Bits shifted at command frames
Definition in Ifx_MSC.DSC.B.NBC.
Downstream Timing Extension Register - Passive Phase Length at Control Frames Extension
Definition in Ifx_MSC.DSTE.B.PPCE.
Downstream Timing Extension Register - Passive Phase Length at Data Frames Extension
Definition in Ifx_MSC.DSTE.B.PPDE.
Interrupt Control Register - Data Frame Interrupt Enable
Definition in Ifx_MSC.ICR.B.EDIE.
Interrupt Control Register - Data Frame Interrupt Node Pointer
Definition in Ifx_MSC.ICR.B.EDIP.
Number of SRx[] (x->SRL/SRH) Bits Shifted at Data Frames
Definition in Ifx_MSC.DSC.B.NDBH and Ifx_MSC.DSC.B.NDBL.
Passive Phase Length at Data Frames
Definition in Ifx_MSC.DSC.B.PPD.
enum IfxMsc_DividerMode |
enum IfxMsc_EmergencyStop |
enum IfxMsc_Extension |
Downstream Control Enhanced Register - Injection Position of the Pin 0 and 1 Signal
Definition in Ifx_MSC.DSCE.B.INJPOSP0 and Ifx_MSC.DSCE.B.INJPOSP1.
Downstream Control Enhanced Register - Injection Enable of the Pin 0 and 1 Signal
Definition in Ifx_MSC.DSCE.B.INJENP0 and Ifx_MSC.DSCE.B.INJENP1.
Enumerator | |
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IfxMsc_ExternalSignalInjection_disabled |
Disables the external signal injection in a data frame. |
IfxMsc_ExternalSignalInjection_enabled |
Enables the external signal injection in a data frame. |
enum IfxMsc_HardwareClock |
OCDS Control and Status - OCDS Suspend Control Definition in Ifx_MSC.OCS.B.SUS.
Downstream Control Enhanced Register - Number of SRL/SRH Bits Shifted at Data Frames Extension (NDBL/NDBH)
Definition in Ifx_MSC.DSCE.B.NDBLE and Ifx_MSC.DSCE.B.NDBHE.
enum IfxMsc_NDividerAbra |
Asynchronous Block Configuration Register - N Divider ABRA
Definition in Ifx_MSC.ABC.B.NDA.
Downstream Timing Extension Register - N Divider Downstream
Definition in Ifx_MSC.DSTE.B.NDD.
Asynchronous Block Configuration Register - Overflow Interrupt Enable
Definition in Ifx_MSC.ABC.B.OIE.
Asynchronous Block Configuration Register - Overflow Interrupt Node Pointer
Definition in Ifx_MSC.ABC.B.OIP.
enum IfxMsc_Parity |
Downstream Status Register - Number Of Passive Time Frames
Definition in Ifx_MSC.DSS.B.NPTF.
Interrupt Control Register - Receive Data Interrupt Enable
Definition in Ifx_MSC.ICR.B.RDIE.
Interrupt Control Register - Receive Data Interrupt Pointer
Definition in Ifx_MSC.ICR.B.RDIP.
Output Control Register - Serial Data Input Selection
Definition in Ifx_MSC.OCR.B.SDISEL.
Asynchronous Block Configuration Register - Duration of the Low/High Phase of the Shift Clock
Definition in Ifx_MSC.ABC.B.LOW and Ifx_MSC.ABC.B.HIGH.
enum IfxMsc_SleepMode |
enum IfxMsc_Source |
Downstream Select Data Source Low Register - Select Source for - SRL and SRHNumber Of Passive Time Frames
Definition in Ifx_MSC.DSDSL and Ifx_MSC.DSDSH.
enum IfxMsc_Target |
Interrupt Control Register - Time Frame Interrupt Pointer
Definition in Ifx_MSC.ICR.B.TFIP.
Asynchronous Block Configuration Register - Underflow Interrupt Enable
Definition in Ifx_MSC.ABC.B.UIE.
Asynchronous Block Configuration Register - Underflow Interrupt Node Pointer
Definition in Ifx_MSC.ABC.B.UIP.
Upstream Receiving Rate
Definition in Ifx_MSC.USR.B.URR.
Upstream Control Enhanced Register 1 - Upstream Timeout Interrupt Node Pointer
Definition in Ifx_MSC.USCE.B.USTOIP.
Upstream Control Enhanced Register 1 - Upstream Timeout Prescaler
Definition in Ifx_MSC.USCE.B.USTOPRE.
Upstream Control Enhanced Register 1 - Upstream Timeout Value
Definition in Ifx_MSC.USCE.B.USTOVAL.