iLLD_TC27xC  1.0
IfxMsc.h
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1 /**
2  * \file IfxMsc.h
3  * \brief MSC basic functionality
4  * \ingroup IfxLld_Msc
5  *
6  * \version iLLD_0_1_0_10
7  * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
8  *
9  *
10  * IMPORTANT NOTICE
11  *
12  *
13  * Infineon Technologies AG (Infineon) is supplying this file for use
14  * exclusively with Infineon's microcontroller products. This file can be freely
15  * distributed within development tools that are supporting such microcontroller
16  * products.
17  *
18  * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
19  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
20  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
21  * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
22  * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
23  *
24  * \defgroup IfxLld_Msc MSC
25  * \ingroup IfxLld
26  * \defgroup IfxLld_Msc_Std Standard Driver
27  * \ingroup IfxLld_Msc
28  * \defgroup IfxLld_Msc_Std_Enum Enumerations
29  * \ingroup IfxLld_Msc_Std
30  * \defgroup IfxLld_Msc_Std_Config_Flags Configure Flags
31  * \ingroup IfxLld_Msc_Std
32  * \defgroup IfxLld_Msc_Std_Set_Command_Target Set Command Target
33  * \ingroup IfxLld_Msc_Std
34  * \defgroup IfxLld_Msc_Std_Set_Data Set Data
35  * \ingroup IfxLld_Msc_Std
36  * \defgroup IfxLld_Msc_Std_Get_Data Get Data
37  * \ingroup IfxLld_Msc_Std
38  * \defgroup IfxLld_Msc_Std_Enable_Module Enable Module
39  * \ingroup IfxLld_Msc_Std
40  * \defgroup IfxLld_Msc_Std_Reset_Module Reset Module
41  * \ingroup IfxLld_Msc_Std
42  * \defgroup IfxLld_Msc_Std_Baud_Calculator Baud Calculator
43  * \ingroup IfxLld_Msc_Std
44  * \defgroup IfxLld_Msc_Std_IO IO Pin Configuration Functions
45  * \ingroup IfxLld_Msc_Std
46  */
47 
48 #ifndef IFXMSC_H
49 #define IFXMSC_H 1
50 
51 /******************************************************************************/
52 /*----------------------------------Includes----------------------------------*/
53 /******************************************************************************/
54 
55 #include "_Impl/IfxMsc_cfg.h"
56 #include "Scu/Std/IfxScuCcu.h"
57 #include "Scu/Std/IfxScuWdt.h"
58 #include "_PinMap/IfxMsc_PinMap.h"
59 
60 /******************************************************************************/
61 /*--------------------------------Enumerations--------------------------------*/
62 /******************************************************************************/
63 
64 /** \addtogroup IfxLld_Msc_Std_Enum
65  * \{ */
66 /** \brief Enable SRL/SRH Active Phase Selection Bit\n
67  * Definition in Ifx_MSC.DSC.B.ENSELH and Ifx_MSC.DSC.B.ENSELL
68  */
69 typedef enum
70 {
71  IfxMsc_ActivePhaseSelection_none = 0, /**< \brief No selection bit inserted */
72  IfxMsc_ActivePhaseSelection_lowLevel = 1 /**< \brief Low level selection bit inserted */
74 
75 /** \brief Asynchronous Block Configuration Register - Asynchronous Block Bypass\n
76  * Definition in Ifx_MSC.ABC.B.ABB
77  */
78 typedef enum
79 {
80  IfxMsc_AsynchronousBlock_bypassed = 0, /**< \brief Asynchronous block and the n-divider of the MSC downstream path are bypassed and are disabled */
81  IfxMsc_AsynchronousBlock_noBypassed = 1 /**< \brief Asynchronous block and the n-divider of the MSC downstream path are active */
83 
84 /** \brief Output Control Register - Chip Selection Line Polarity\n
85  * Definition in Ifx_MSC.OCR.B.CSLP
86  */
87 typedef enum
88 {
89  IfxMsc_ChipSelectActiveState_high = 0, /**< \brief EN[3:0] and ENL,ENH,ENC polarities are identical */
90  IfxMsc_ChipSelectActiveState_low = 1 /**< \brief EN[3:0] and ENL,ENH,ENC polarities are inverted */
92 
93 /** \brief Asynchronous Block Configuration Register - Clock Select\n
94  * Definition in Ifx_MSC.ABC.B.CLKSEL
95  */
96 typedef enum
97 {
98  IfxMsc_ClockSelect_noClock = 0, /**< \brief no clock source for the ABRA block */
99  IfxMsc_ClockSelect_fspb = 1, /**< \brief f_SPB is the clock source for the ABRA block */
100  IfxMsc_ClockSelect_fsri = 2, /**< \brief f_SRI is the clock source for the ABRA block */
101  IfxMsc_ClockSelect_feray = 4 /**< \brief f_ERAY is the clock source for the ABRA block */
103 
104 /** \brief Downstream Control Enhanced Register - Command-Data-Command in Data Repetition Mode\n
105  * Definition in Ifx_MSC.DSCE.B.CDCM
106  */
107 typedef enum
108 {
109  IfxMsc_CommandDataCommandRepetitionMode_disabled = 0, /**< \brief Disables the automatic insertion of data */
110  IfxMsc_CommandDataCommandRepetitionMode_enabled = 1 /**< \brief Enables the automatic insertion of data */
112 
113 /** \brief Interrupt Control Register - Command Frame Interrupt Enable\n
114  * Definition in Ifx_MSC.ICR.B.ECIE
115  */
116 typedef enum
117 {
118  IfxMsc_CommandFrameInterrupt_disabled = 0, /**< \brief Interrupt generation disabled */
119  IfxMsc_CommandFrameInterrupt_enabled = 1 /**< \brief Interrupt generation enabled */
121 
122 /** \brief Interrupt Control Register - Command Frame Interrupt Node Pointer\n
123  * Definition in Ifx_MSC.ICR.B.ECIP
124  */
125 typedef enum
126 {
127  IfxMsc_CommandFrameInterruptNode_SR0 = 0, /**< \brief Service request output SR0 selected */
128  IfxMsc_CommandFrameInterruptNode_SR1, /**< \brief Service request output SR1 selected */
129  IfxMsc_CommandFrameInterruptNode_SR2, /**< \brief Service request output SR2 selected */
130  IfxMsc_CommandFrameInterruptNode_SR3, /**< \brief Service request output SR3 selected */
132 
133 /** \brief Number of Bits shifted at command frames\n
134  * Definition in Ifx_MSC.DSC.B.NBC
135  */
136 typedef enum
137 {
138  IfxMsc_CommandFrameLength_0 = 0, /**< \brief No bit shifted */
139  IfxMsc_CommandFrameLength_1 = 1, /**< \brief SRL[0] Shifted */
140  IfxMsc_CommandFrameLength_2 = 2, /**< \brief SRL[1:0] Shifted */
141  IfxMsc_CommandFrameLength_3, /**< \brief SRL[2:0] Shifted */
142  IfxMsc_CommandFrameLength_4, /**< \brief SRL[3:0] Shifted */
143  IfxMsc_CommandFrameLength_5, /**< \brief SRL[4:0] Shifted */
144  IfxMsc_CommandFrameLength_6, /**< \brief SRL[5:0] Shifted */
145  IfxMsc_CommandFrameLength_7, /**< \brief SRL[6:0] Shifted */
146  IfxMsc_CommandFrameLength_8, /**< \brief SRL[7:0] Shifted */
147  IfxMsc_CommandFrameLength_9, /**< \brief SRL[8:0] Shifted */
148  IfxMsc_CommandFrameLength_10, /**< \brief SRL[9:0] Shifted */
149  IfxMsc_CommandFrameLength_11, /**< \brief SRL[10:0] Shifted */
150  IfxMsc_CommandFrameLength_12, /**< \brief SRL[11:0] Shifted */
151  IfxMsc_CommandFrameLength_13, /**< \brief SRL[12:0] Shifted */
152  IfxMsc_CommandFrameLength_14, /**< \brief SRL[13:0] Shifted */
153  IfxMsc_CommandFrameLength_15, /**< \brief SRL[14:0] Shifted */
154  IfxMsc_CommandFrameLength_16, /**< \brief SRL[15:0] Shifted */
155  IfxMsc_CommandFrameLength_17 = 17, /**< \brief SRL[15:0] and SRH[0] Shifted */
156  IfxMsc_CommandFrameLength_18 = 18, /**< \brief SRL[15:0] and SRH[1:0] Shifted */
157  IfxMsc_CommandFrameLength_19, /**< \brief SRL[15:0] and SRH[2:0] Shifted */
158  IfxMsc_CommandFrameLength_20, /**< \brief SRL[15:0] and SRH[3:0] Shifted */
159  IfxMsc_CommandFrameLength_21, /**< \brief SRL[15:0] and SRH[4:0] Shifted */
160  IfxMsc_CommandFrameLength_22, /**< \brief SRL[15:0] and SRH[5:0] Shifted */
161  IfxMsc_CommandFrameLength_23, /**< \brief SRL[15:0] and SRH[6:0] Shifted */
162  IfxMsc_CommandFrameLength_24, /**< \brief SRL[15:0] and SRH[7:0] Shifted */
163  IfxMsc_CommandFrameLength_25, /**< \brief SRL[15:0] and SRH[8:0] Shifted */
164  IfxMsc_CommandFrameLength_26, /**< \brief SRL[15:0] and SRH[9:0] Shifted */
165  IfxMsc_CommandFrameLength_27, /**< \brief SRL[15:0] and SRH[10:0] Shifted */
166  IfxMsc_CommandFrameLength_28, /**< \brief SRL[15:0] and SRH[11:0] Shifted */
167  IfxMsc_CommandFrameLength_29, /**< \brief SRL[15:0] and SRH[12:0] Shifted */
168  IfxMsc_CommandFrameLength_30, /**< \brief SRL[15:0] and SRH[13:0] Shifted */
169  IfxMsc_CommandFrameLength_31, /**< \brief SRL[15:0] and SRH[14:0] Shifted */
170  IfxMsc_CommandFrameLength_32, /**< \brief SRL[15:0] and SRH[15:0] Shifted */
172 
173 /** \brief Downstream Timing Extension Register - Passive Phase Length at Control Frames Extension\n
174  * Definition in Ifx_MSC.DSTE.B.PPCE
175  */
176 typedef enum
177 {
178  IfxMsc_ControlFrameExtensionPassivePhaseLength_0 = 0, /**< \brief Length of Command frames passive phase is 2 */
179  IfxMsc_ControlFrameExtensionPassivePhaseLength_1, /**< \brief Length of Command frames passive phase is 3 */
180  IfxMsc_ControlFrameExtensionPassivePhaseLength_2, /**< \brief Length of Command frames passive phase is 4 */
181  IfxMsc_ControlFrameExtensionPassivePhaseLength_3, /**< \brief Length of Command frames passive phase is 5 */
182  IfxMsc_ControlFrameExtensionPassivePhaseLength_4, /**< \brief Length of Command frames passive phase is 6 */
183  IfxMsc_ControlFrameExtensionPassivePhaseLength_5, /**< \brief Length of Command frames passive phase is 7 */
184  IfxMsc_ControlFrameExtensionPassivePhaseLength_6, /**< \brief Length of Command frames passive phase is 8 */
185  IfxMsc_ControlFrameExtensionPassivePhaseLength_7, /**< \brief Length of Command frames passive phase is 9 */
186  IfxMsc_ControlFrameExtensionPassivePhaseLength_8, /**< \brief Length of Command frames passive phase is 10 */
187  IfxMsc_ControlFrameExtensionPassivePhaseLength_9, /**< \brief Length of Command frames passive phase is 11 */
188  IfxMsc_ControlFrameExtensionPassivePhaseLength_10, /**< \brief Length of Command frames passive phase is 12 */
189  IfxMsc_ControlFrameExtensionPassivePhaseLength_11, /**< \brief Length of Command frames passive phase is 13 */
190  IfxMsc_ControlFrameExtensionPassivePhaseLength_12, /**< \brief Length of Command frames passive phase is 14 */
191  IfxMsc_ControlFrameExtensionPassivePhaseLength_13, /**< \brief Length of Command frames passive phase is 15 */
192  IfxMsc_ControlFrameExtensionPassivePhaseLength_14, /**< \brief Length of Command frames passive phase is 16 */
193  IfxMsc_ControlFrameExtensionPassivePhaseLength_15, /**< \brief Length of Command frames passive phase is 17 */
194  IfxMsc_ControlFrameExtensionPassivePhaseLength_16, /**< \brief Length of Command frames passive phase is 18 */
195  IfxMsc_ControlFrameExtensionPassivePhaseLength_17, /**< \brief Length of Command frames passive phase is 19 */
196  IfxMsc_ControlFrameExtensionPassivePhaseLength_18, /**< \brief Length of Command frames passive phase is 20 */
197  IfxMsc_ControlFrameExtensionPassivePhaseLength_19, /**< \brief Length of Command frames passive phase is 21 */
198  IfxMsc_ControlFrameExtensionPassivePhaseLength_20, /**< \brief Length of Command frames passive phase is 22 */
199  IfxMsc_ControlFrameExtensionPassivePhaseLength_21, /**< \brief Length of Command frames passive phase is 23 */
200  IfxMsc_ControlFrameExtensionPassivePhaseLength_22, /**< \brief Length of Command frames passive phase is 24 */
201  IfxMsc_ControlFrameExtensionPassivePhaseLength_23, /**< \brief Length of Command frames passive phase is 25 */
202  IfxMsc_ControlFrameExtensionPassivePhaseLength_24, /**< \brief Length of Command frames passive phase is 26 */
203  IfxMsc_ControlFrameExtensionPassivePhaseLength_25, /**< \brief Length of Command frames passive phase is 27 */
204  IfxMsc_ControlFrameExtensionPassivePhaseLength_26, /**< \brief Length of Command frames passive phase is 28 */
205  IfxMsc_ControlFrameExtensionPassivePhaseLength_27, /**< \brief Length of Command frames passive phase is 29 */
206  IfxMsc_ControlFrameExtensionPassivePhaseLength_28, /**< \brief Length of Command frames passive phase is 30 */
207  IfxMsc_ControlFrameExtensionPassivePhaseLength_29, /**< \brief Length of Command frames passive phase is 31 */
208  IfxMsc_ControlFrameExtensionPassivePhaseLength_30, /**< \brief Length of Command frames passive phase is 32 */
209  IfxMsc_ControlFrameExtensionPassivePhaseLength_31, /**< \brief Length of Command frames passive phase is 33 */
210  IfxMsc_ControlFrameExtensionPassivePhaseLength_32, /**< \brief Length of Command frames passive phase is 34 */
211  IfxMsc_ControlFrameExtensionPassivePhaseLength_33, /**< \brief Length of Command frames passive phase is 35 */
212  IfxMsc_ControlFrameExtensionPassivePhaseLength_34, /**< \brief Length of Command frames passive phase is 36 */
213  IfxMsc_ControlFrameExtensionPassivePhaseLength_35, /**< \brief Length of Command frames passive phase is 37 */
214  IfxMsc_ControlFrameExtensionPassivePhaseLength_36, /**< \brief Length of Command frames passive phase is 38 */
215  IfxMsc_ControlFrameExtensionPassivePhaseLength_37, /**< \brief Length of Command frames passive phase is 39 */
216  IfxMsc_ControlFrameExtensionPassivePhaseLength_38, /**< \brief Length of Command frames passive phase is 40 */
217  IfxMsc_ControlFrameExtensionPassivePhaseLength_39, /**< \brief Length of Command frames passive phase is 41 */
218  IfxMsc_ControlFrameExtensionPassivePhaseLength_40, /**< \brief Length of Command frames passive phase is 42 */
219  IfxMsc_ControlFrameExtensionPassivePhaseLength_41, /**< \brief Length of Command frames passive phase is 43 */
220  IfxMsc_ControlFrameExtensionPassivePhaseLength_42, /**< \brief Length of Command frames passive phase is 44 */
221  IfxMsc_ControlFrameExtensionPassivePhaseLength_43, /**< \brief Length of Command frames passive phase is 45 */
222  IfxMsc_ControlFrameExtensionPassivePhaseLength_44, /**< \brief Length of Command frames passive phase is 46 */
223  IfxMsc_ControlFrameExtensionPassivePhaseLength_45, /**< \brief Length of Command frames passive phase is 47 */
224  IfxMsc_ControlFrameExtensionPassivePhaseLength_46, /**< \brief Length of Command frames passive phase is 48 */
225  IfxMsc_ControlFrameExtensionPassivePhaseLength_47, /**< \brief Length of Command frames passive phase is 49 */
226  IfxMsc_ControlFrameExtensionPassivePhaseLength_48, /**< \brief Length of Command frames passive phase is 50 */
227  IfxMsc_ControlFrameExtensionPassivePhaseLength_49, /**< \brief Length of Command frames passive phase is 51 */
228  IfxMsc_ControlFrameExtensionPassivePhaseLength_50, /**< \brief Length of Command frames passive phase is 52 */
229  IfxMsc_ControlFrameExtensionPassivePhaseLength_51, /**< \brief Length of Command frames passive phase is 53 */
230  IfxMsc_ControlFrameExtensionPassivePhaseLength_52, /**< \brief Length of Command frames passive phase is 54 */
231  IfxMsc_ControlFrameExtensionPassivePhaseLength_53, /**< \brief Length of Command frames passive phase is 55 */
232  IfxMsc_ControlFrameExtensionPassivePhaseLength_54, /**< \brief Length of Command frames passive phase is 56 */
233  IfxMsc_ControlFrameExtensionPassivePhaseLength_55, /**< \brief Length of Command frames passive phase is 57 */
234  IfxMsc_ControlFrameExtensionPassivePhaseLength_56, /**< \brief Length of Command frames passive phase is 58 */
235  IfxMsc_ControlFrameExtensionPassivePhaseLength_57, /**< \brief Length of Command frames passive phase is 59 */
236  IfxMsc_ControlFrameExtensionPassivePhaseLength_58, /**< \brief Length of Command frames passive phase is 60 */
237  IfxMsc_ControlFrameExtensionPassivePhaseLength_59, /**< \brief Length of Command frames passive phase is 61 */
238  IfxMsc_ControlFrameExtensionPassivePhaseLength_60, /**< \brief Length of Command frames passive phase is 62 */
239  IfxMsc_ControlFrameExtensionPassivePhaseLength_61, /**< \brief Length of Command frames passive phase is 63 */
240  IfxMsc_ControlFrameExtensionPassivePhaseLength_62, /**< \brief Length of Command frames passive phase is 64 */
241  IfxMsc_ControlFrameExtensionPassivePhaseLength_63, /**< \brief Length of Command frames passive phase is 65 */
243 
244 /** \brief Downstream Timing Extension Register - Passive Phase Length at Data Frames Extension\n
245  * Definition in Ifx_MSC.DSTE.B.PPDE
246  */
247 typedef enum
248 {
249  IfxMsc_DataFrameExtensionPassivePhaseLength_0 = 0, /**< \brief 0 Additional MSB bits extension of the PPD bit field */
250  IfxMsc_DataFrameExtensionPassivePhaseLength_1, /**< \brief 1 Additional MSB bits extension of the PPD bit field */
251  IfxMsc_DataFrameExtensionPassivePhaseLength_2, /**< \brief 2 Additional MSB bits extension of the PPD bit field */
252  IfxMsc_DataFrameExtensionPassivePhaseLength_3, /**< \brief 3 Additional MSB bits extension of the PPD bit field */
254 
255 /** \brief Interrupt Control Register - Data Frame Interrupt Enable\n
256  * Definition in Ifx_MSC.ICR.B.EDIE
257  */
258 typedef enum
259 {
260  IfxMsc_DataFrameInterrupt_disabled = 0, /**< \brief Interrupt generation Disable */
261  IfxMsc_DataFrameInterrupt_atLastDataBit = 1, /**< \brief An interrupt is generated when the last data bit has been shifted out */
262  IfxMsc_DataFrameInterrupt_atFirstDataBit = 2 /**< \brief An interrupt is generated when the First data bit has been shifted out */
264 
265 /** \brief Interrupt Control Register - Data Frame Interrupt Node Pointer\n
266  * Definition in Ifx_MSC.ICR.B.EDIP
267  */
268 typedef enum
269 {
270  IfxMsc_DataFrameInterruptNode_SR0 = 0, /**< \brief Service request output SR0 selected */
271  IfxMsc_DataFrameInterruptNode_SR1, /**< \brief Service request output SR1 selected */
272  IfxMsc_DataFrameInterruptNode_SR2, /**< \brief Service request output SR2 selected */
273  IfxMsc_DataFrameInterruptNode_SR3, /**< \brief Service request output SR3 selected */
275 
276 /** \brief Number of SRx[] (x->SRL/SRH) Bits Shifted at Data Frames\n
277  * Definition in Ifx_MSC.DSC.B.NDBH and Ifx_MSC.DSC.B.NDBL
278  */
279 typedef enum
280 {
281  IfxMsc_DataFrameLength_0 = 0, /**< \brief No SRx bit shifted */
282  IfxMsc_DataFrameLength_1 = 1, /**< \brief SRx[0] Shifted */
283  IfxMsc_DataFrameLength_2 = 2, /**< \brief SRx[1:0] Shifted */
284  IfxMsc_DataFrameLength_3, /**< \brief SRx[2:0] Shifted */
285  IfxMsc_DataFrameLength_4, /**< \brief SRx[3:0] Shifted */
286  IfxMsc_DataFrameLength_5, /**< \brief SRx[4:0] Shifted */
287  IfxMsc_DataFrameLength_6, /**< \brief SRx[5:0] Shifted */
288  IfxMsc_DataFrameLength_7, /**< \brief SRx[6:0] Shifted */
289  IfxMsc_DataFrameLength_8, /**< \brief SRx[7:0] Shifted */
290  IfxMsc_DataFrameLength_9, /**< \brief SRx[8:0] Shifted */
291  IfxMsc_DataFrameLength_10, /**< \brief SRx[9:0] Shifted */
292  IfxMsc_DataFrameLength_11, /**< \brief SRx[10:0] Shifted */
293  IfxMsc_DataFrameLength_12, /**< \brief SRx[11:0] Shifted */
294  IfxMsc_DataFrameLength_13, /**< \brief SRx[12:0] Shifted */
295  IfxMsc_DataFrameLength_14, /**< \brief SRx[13:0] Shifted */
296  IfxMsc_DataFrameLength_15, /**< \brief SRx[14:0] Shifted */
297  IfxMsc_DataFrameLength_16, /**< \brief SRx[15:0] Shifted */
299 
300 /** \brief Passive Phase Length at Data Frames\n
301  * Definition in Ifx_MSC.DSC.B.PPD
302  */
303 typedef enum
304 {
305  IfxMsc_DataFramePassivePhaseLength_2 = 2, /**< \brief Passive phase length is 2 tFCL */
306  IfxMsc_DataFramePassivePhaseLength_3, /**< \brief Passive phase length is 3 tFCL */
307  IfxMsc_DataFramePassivePhaseLength_4, /**< \brief Passive phase length is 4 tFCL */
308  IfxMsc_DataFramePassivePhaseLength_5, /**< \brief Passive phase length is 5 tFCL */
309  IfxMsc_DataFramePassivePhaseLength_6, /**< \brief Passive phase length is 6 tFCL */
310  IfxMsc_DataFramePassivePhaseLength_7, /**< \brief Passive phase length is 7 tFCL */
311  IfxMsc_DataFramePassivePhaseLength_8, /**< \brief Passive phase length is 8 tFCL */
312  IfxMsc_DataFramePassivePhaseLength_9, /**< \brief Passive phase length is 9 tFCL */
313  IfxMsc_DataFramePassivePhaseLength_10, /**< \brief Passive phase length is 10 tFCL */
314  IfxMsc_DataFramePassivePhaseLength_11, /**< \brief Passive phase length is 11 tFCL */
315  IfxMsc_DataFramePassivePhaseLength_12, /**< \brief Passive phase length is 12 tFCL */
316  IfxMsc_DataFramePassivePhaseLength_13, /**< \brief Passive phase length is 13 tFCL */
317  IfxMsc_DataFramePassivePhaseLength_14, /**< \brief Passive phase length is 14 tFCL */
318  IfxMsc_DataFramePassivePhaseLength_15, /**< \brief Passive phase length is 15 tFCL */
319  IfxMsc_DataFramePassivePhaseLength_16, /**< \brief Passive phase length is 16 tFCL */
320  IfxMsc_DataFramePassivePhaseLength_17, /**< \brief Passive phase length is 17 tFCL */
321  IfxMsc_DataFramePassivePhaseLength_18, /**< \brief Passive phase length is 18 tFCL */
322  IfxMsc_DataFramePassivePhaseLength_19, /**< \brief Passive phase length is 19 tFCL */
323  IfxMsc_DataFramePassivePhaseLength_20, /**< \brief Passive phase length is 20 tFCL */
324  IfxMsc_DataFramePassivePhaseLength_21, /**< \brief Passive phase length is 21 tFCL */
325  IfxMsc_DataFramePassivePhaseLength_22, /**< \brief Passive phase length is 22 tFCL */
326  IfxMsc_DataFramePassivePhaseLength_23, /**< \brief Passive phase length is 23 tFCL */
327  IfxMsc_DataFramePassivePhaseLength_24, /**< \brief Passive phase length is 24 tFCL */
328  IfxMsc_DataFramePassivePhaseLength_25, /**< \brief Passive phase length is 25 tFCL */
329  IfxMsc_DataFramePassivePhaseLength_26, /**< \brief Passive phase length is 26 tFCL */
330  IfxMsc_DataFramePassivePhaseLength_27, /**< \brief Passive phase length is 27 tFCL */
331  IfxMsc_DataFramePassivePhaseLength_28, /**< \brief Passive phase length is 28 tFCL */
332  IfxMsc_DataFramePassivePhaseLength_29, /**< \brief Passive phase length is 29 tFCL */
333  IfxMsc_DataFramePassivePhaseLength_30, /**< \brief Passive phase length is 30 tFCL */
334  IfxMsc_DataFramePassivePhaseLength_31, /**< \brief Passive phase length is 31 tFCL */
335  IfxMsc_DataFramePassivePhaseLength_32, /**< \brief Passive phase length is 32 tFCL */
337 
338 /** \brief Divider mode
339  */
340 typedef enum
341 {
342  IfxMsc_DividerMode_normal = 1, /**< \brief divider mode is normal */
343  IfxMsc_DividerMode_fractional = 2 /**< \brief divider mode is fractional */
345 
346 /** \brief Emergency Stop Register - Emergency stop feature Enable or Disable - SRL and SRH\n
347  * Definition in Ifx_MSC.ESR
348  */
349 typedef enum
350 {
351  IfxMsc_EmergencyStop_disabled = 0, /**< \brief Emergency stop feature for SRx bit is Disabled */
352  IfxMsc_EmergencyStop_enabled = 1 /**< \brief Emergency stop feature for SRx bit is Enabled */
354 
355 /** \brief Downstream Control Enhanced Register - Extension Enable\n
356  * Definition in Ifx_MSC.DSCE.B.NDBLE
357  */
358 typedef enum
359 {
360  IfxMsc_Extension_disabled = 0, /**< \brief Disables the extension bit fields */
361  IfxMsc_Extension_enabled = 1 /**< \brief Enables the extension bit fields */
363 
364 /** \brief Downstream Control Enhanced Register - Injection Position of the Pin 0 and 1 Signal\n
365  * Definition in Ifx_MSC.DSCE.B.INJPOSP0 and Ifx_MSC.DSCE.B.INJPOSP1
366  */
367 typedef enum
368 {
369  IfxMsc_ExternalBitInjectionPosition_0 = 0, /**< \brief Injected external bit is at Position 0 of the data frame */
370  IfxMsc_ExternalBitInjectionPosition_1, /**< \brief Injected external bit is at Position 1 of the data frame */
371  IfxMsc_ExternalBitInjectionPosition_2, /**< \brief Injected external bit is at Position 2 of the data frame */
372  IfxMsc_ExternalBitInjectionPosition_3, /**< \brief Injected external bit is at Position 3 of the data frame */
373  IfxMsc_ExternalBitInjectionPosition_4, /**< \brief Injected external bit is at Position 4 of the data frame */
374  IfxMsc_ExternalBitInjectionPosition_5, /**< \brief Injected external bit is at Position 5 of the data frame */
375  IfxMsc_ExternalBitInjectionPosition_6, /**< \brief Injected external bit is at Position 6 of the data frame */
376  IfxMsc_ExternalBitInjectionPosition_7, /**< \brief Injected external bit is at Position 7 of the data frame */
377  IfxMsc_ExternalBitInjectionPosition_8, /**< \brief Injected external bit is at Position 8 of the data frame */
378  IfxMsc_ExternalBitInjectionPosition_9, /**< \brief Injected external bit is at Position 9 of the data frame */
379  IfxMsc_ExternalBitInjectionPosition_10, /**< \brief Injected external bit is at Position 10 of the data frame */
380  IfxMsc_ExternalBitInjectionPosition_11, /**< \brief Injected external bit is at Position 11 of the data frame */
381  IfxMsc_ExternalBitInjectionPosition_12, /**< \brief Injected external bit is at Position 12 of the data frame */
382  IfxMsc_ExternalBitInjectionPosition_13, /**< \brief Injected external bit is at Position 13 of the data frame */
383  IfxMsc_ExternalBitInjectionPosition_14, /**< \brief Injected external bit is at Position 14 of the data frame */
384  IfxMsc_ExternalBitInjectionPosition_15, /**< \brief Injected external bit is at Position 15 of the data frame */
385  IfxMsc_ExternalBitInjectionPosition_16, /**< \brief Injected external bit is at Position 16 of the data frame */
386  IfxMsc_ExternalBitInjectionPosition_17, /**< \brief Injected external bit is at Position 17 of the data frame */
387  IfxMsc_ExternalBitInjectionPosition_18, /**< \brief Injected external bit is at Position 18 of the data frame */
388  IfxMsc_ExternalBitInjectionPosition_19, /**< \brief Injected external bit is at Position 19 of the data frame */
389  IfxMsc_ExternalBitInjectionPosition_20, /**< \brief Injected external bit is at Position 20 of the data frame */
390  IfxMsc_ExternalBitInjectionPosition_21, /**< \brief Injected external bit is at Position 21 of the data frame */
391  IfxMsc_ExternalBitInjectionPosition_22, /**< \brief Injected external bit is at Position 22 of the data frame */
392  IfxMsc_ExternalBitInjectionPosition_23, /**< \brief Injected external bit is at Position 23 of the data frame */
393  IfxMsc_ExternalBitInjectionPosition_24, /**< \brief Injected external bit is at Position 24 of the data frame */
394  IfxMsc_ExternalBitInjectionPosition_25, /**< \brief Injected external bit is at Position 25 of the data frame */
395  IfxMsc_ExternalBitInjectionPosition_26, /**< \brief Injected external bit is at Position 26 of the data frame */
396  IfxMsc_ExternalBitInjectionPosition_27, /**< \brief Injected external bit is at Position 27 of the data frame */
397  IfxMsc_ExternalBitInjectionPosition_28, /**< \brief Injected external bit is at Position 28 of the data frame */
398  IfxMsc_ExternalBitInjectionPosition_29, /**< \brief Injected external bit is at Position 29 of the data frame */
399  IfxMsc_ExternalBitInjectionPosition_30, /**< \brief Injected external bit is at Position 30 of the data frame */
400  IfxMsc_ExternalBitInjectionPosition_31, /**< \brief Injected external bit is at Position 31 of the data frame */
401  IfxMsc_ExternalBitInjectionPosition_32, /**< \brief Injected external bit is at Position 32 of the data frame */
402  IfxMsc_ExternalBitInjectionPosition_33, /**< \brief Injected external bit is at Position 33 of the data frame */
403  IfxMsc_ExternalBitInjectionPosition_34, /**< \brief Injected external bit is at Position 34 of the data frame */
404  IfxMsc_ExternalBitInjectionPosition_35, /**< \brief Injected external bit is at Position 35 of the data frame */
405  IfxMsc_ExternalBitInjectionPosition_36, /**< \brief Injected external bit is at Position 36 of the data frame */
406  IfxMsc_ExternalBitInjectionPosition_37, /**< \brief Injected external bit is at Position 37 of the data frame */
407  IfxMsc_ExternalBitInjectionPosition_38, /**< \brief Injected external bit is at Position 38 of the data frame */
408  IfxMsc_ExternalBitInjectionPosition_39, /**< \brief Injected external bit is at Position 39 of the data frame */
409  IfxMsc_ExternalBitInjectionPosition_40, /**< \brief Injected external bit is at Position 40 of the data frame */
410  IfxMsc_ExternalBitInjectionPosition_41, /**< \brief Injected external bit is at Position 41 of the data frame */
411  IfxMsc_ExternalBitInjectionPosition_42, /**< \brief Injected external bit is at Position 42 of the data frame */
412  IfxMsc_ExternalBitInjectionPosition_43, /**< \brief Injected external bit is at Position 43 of the data frame */
413  IfxMsc_ExternalBitInjectionPosition_44, /**< \brief Injected external bit is at Position 44 of the data frame */
414  IfxMsc_ExternalBitInjectionPosition_45, /**< \brief Injected external bit is at Position 45 of the data frame */
415  IfxMsc_ExternalBitInjectionPosition_46, /**< \brief Injected external bit is at Position 46 of the data frame */
416  IfxMsc_ExternalBitInjectionPosition_47, /**< \brief Injected external bit is at Position 47 of the data frame */
417  IfxMsc_ExternalBitInjectionPosition_48, /**< \brief Injected external bit is at Position 48 of the data frame */
418  IfxMsc_ExternalBitInjectionPosition_49, /**< \brief Injected external bit is at Position 49 of the data frame */
419  IfxMsc_ExternalBitInjectionPosition_50, /**< \brief Injected external bit is at Position 50 of the data frame */
420  IfxMsc_ExternalBitInjectionPosition_51, /**< \brief Injected external bit is at Position 51 of the data frame */
421  IfxMsc_ExternalBitInjectionPosition_52, /**< \brief Injected external bit is at Position 52 of the data frame */
422  IfxMsc_ExternalBitInjectionPosition_53, /**< \brief Injected external bit is at Position 53 of the data frame */
423  IfxMsc_ExternalBitInjectionPosition_54, /**< \brief Injected external bit is at Position 54 of the data frame */
424  IfxMsc_ExternalBitInjectionPosition_55, /**< \brief Injected external bit is at Position 55 of the data frame */
425  IfxMsc_ExternalBitInjectionPosition_56, /**< \brief Injected external bit is at Position 56 of the data frame */
426  IfxMsc_ExternalBitInjectionPosition_57, /**< \brief Injected external bit is at Position 57 of the data frame */
427  IfxMsc_ExternalBitInjectionPosition_58, /**< \brief Injected external bit is at Position 58 of the data frame */
428  IfxMsc_ExternalBitInjectionPosition_59, /**< \brief Injected external bit is at Position 59 of the data frame */
429  IfxMsc_ExternalBitInjectionPosition_60, /**< \brief Injected external bit is at Position 60 of the data frame */
430  IfxMsc_ExternalBitInjectionPosition_61, /**< \brief Injected external bit is at Position 61 of the data frame */
431  IfxMsc_ExternalBitInjectionPosition_62, /**< \brief Injected external bit is at Position 62 of the data frame */
432  IfxMsc_ExternalBitInjectionPosition_63, /**< \brief Injected external bit is at Position 63 of the data frame */
434 
435 /** \brief Downstream Control Enhanced Register - Injection Enable of the Pin 0 and 1 Signal\n
436  * Definition in Ifx_MSC.DSCE.B.INJENP0 and Ifx_MSC.DSCE.B.INJENP1
437  */
438 typedef enum
439 {
440  IfxMsc_ExternalSignalInjection_disabled = 0, /**< \brief Disables the external signal injection in a data frame */
441  IfxMsc_ExternalSignalInjection_enabled = 1 /**< \brief Enables the external signal injection in a data frame */
443 
444 /** \brief Output Control Register - Clock Control\n
445  * Definition in Ifx_MSC.OCR.B.CLKCTRL
446  */
447 typedef enum
448 {
449  IfxMsc_FclClockControlEnabled_activePhaseOnly = 0, /**< \brief FCL is active during active phases of data or command frames */
450  IfxMsc_FclClockControlEnabled_always = 1 /**< \brief FCL is always active */
452 
453 /** \brief Output Control Register - FCLP Line Polarity\n
454  * Definition in Ifx_MSC.OCR.B.CLP
455  */
456 typedef enum
457 {
458  IfxMsc_FclLinePolarity_nonInverted = 0, /**< \brief FCLP and FCL signal polarity is identical */
459  IfxMsc_FclLinePolarity_inverted = 1 /**< \brief FCLP signal has inverted FCL signal polarity */
461 
462 /** \brief Enable hardware clock control
463  */
464 typedef enum
465 {
466  IfxMsc_HardwareClock_disabled = 0, /**< \brief Hardware clock disable */
467  IfxMsc_HardwareClock_enabled = 1 /**< \brief Hardware clock enable */
469 
470 /** \brief OCDS Control and Status - OCDS Suspend Control
471  * Definition in Ifx_MSC.OCS.B.SUS
472  */
473 typedef enum
474 {
475  IfxMsc_ModuleSuspendRequestBit_noSuspend = 0, /**< \brief OCDS is not suspended */
476  IfxMsc_ModuleSuspendRequestBit_hardSuspend = 1, /**< \brief OCDS is Hard suspended. Clock is switched off immediately */
477  IfxMsc_ModuleSuspendRequestBit_softSuspend = 2 /**< \brief OCDS is Soft suspended */
479 
480 /** \brief Downstream Control Enhanced Register - Number of SRL/SRH Bits Shifted at Data Frames Extension (NDBL/NDBH)\n
481  * Definition in Ifx_MSC.DSCE.B.NDBLE and Ifx_MSC.DSCE.B.NDBHE
482  */
483 typedef enum
484 {
485  IfxMsc_MsbBitDataExtension_notPresent = 0, /**< \brief Additional MSB bit is not present in the extension of the NDBL/NDBH bit field */
486  IfxMsc_MsbBitDataExtension_present = 1 /**< \brief Additional MSB bit is present in the extension of the NDBL/NDBH bit field */
488 
489 /** \brief Asynchronous Block Configuration Register - N Divider ABRA\n
490  * Definition in Ifx_MSC.ABC.B.NDA
491  */
492 typedef enum
493 {
494  IfxMsc_NDividerAbra_1 = 0, /**< \brief Division ratio is 1 */
495  IfxMsc_NDividerAbra_2, /**< \brief Division ratio is 2 */
496  IfxMsc_NDividerAbra_3, /**< \brief Division ratio is 3 */
497  IfxMsc_NDividerAbra_4, /**< \brief Division ratio is 4 */
498  IfxMsc_NDividerAbra_5, /**< \brief Division ratio is 5 */
499  IfxMsc_NDividerAbra_6, /**< \brief Division ratio is 6 */
500  IfxMsc_NDividerAbra_7, /**< \brief Division ratio is 7 */
501  IfxMsc_NDividerAbra_8, /**< \brief Division ratio is 8 */
503 
504 /** \brief Downstream Timing Extension Register - N Divider Downstream\n
505  * Definition in Ifx_MSC.DSTE.B.NDD
506  */
507 typedef enum
508 {
509  IfxMsc_NDividerDownstream_1 = 0, /**< \brief division ratio is 1 */
510  IfxMsc_NDividerDownstream_2, /**< \brief division ratio is 2 */
511  IfxMsc_NDividerDownstream_3, /**< \brief division ratio is 3 */
512  IfxMsc_NDividerDownstream_4, /**< \brief division ratio is 4 */
513  IfxMsc_NDividerDownstream_5, /**< \brief division ratio is 5 */
514  IfxMsc_NDividerDownstream_6, /**< \brief division ratio is 6 */
515  IfxMsc_NDividerDownstream_7, /**< \brief division ratio is 7 */
516  IfxMsc_NDividerDownstream_8, /**< \brief division ratio is 8 */
517  IfxMsc_NDividerDownstream_9, /**< \brief division ratio is 9 */
518  IfxMsc_NDividerDownstream_10, /**< \brief division ratio is 10 */
519  IfxMsc_NDividerDownstream_11, /**< \brief division ratio is 11 */
520  IfxMsc_NDividerDownstream_12, /**< \brief division ratio is 12 */
521  IfxMsc_NDividerDownstream_13, /**< \brief division ratio is 13 */
522  IfxMsc_NDividerDownstream_14, /**< \brief division ratio is 14 */
523  IfxMsc_NDividerDownstream_15, /**< \brief division ratio is 15 */
524  IfxMsc_NDividerDownstream_16, /**< \brief division ratio is 16 */
526 
527 /** \brief Asynchronous Block Configuration Register - Overflow Interrupt Enable\n
528  * Definition in Ifx_MSC.ABC.B.OIE
529  */
530 typedef enum
531 {
532  IfxMsc_OverflowInterrupt_disabled = 0, /**< \brief Disables the path of the overflow interrupt towards the interrupt node */
533  IfxMsc_OverflowInterrupt_enabled = 1 /**< \brief Enables the path of the overflow interrupt towards the interrupt node */
535 
536 /** \brief Asynchronous Block Configuration Register - Overflow Interrupt Node Pointer\n
537  * Definition in Ifx_MSC.ABC.B.OIP
538  */
539 typedef enum
540 {
541  IfxMsc_OverflowInterruptNode_SR0 = 0, /**< \brief Service request output SR0 selected */
542  IfxMsc_OverflowInterruptNode_SR1, /**< \brief Service request output SR1 selected */
543  IfxMsc_OverflowInterruptNode_SR2, /**< \brief Service request output SR2 selected */
544  IfxMsc_OverflowInterruptNode_SR3, /**< \brief Service request output SR3 selected */
545  IfxMsc_OverflowInterruptNode_SR4, /**< \brief Service request output SR4 selected */
547 
548 /** \brief Parity Mode\n
549  * Definition in Ifx_MSC.USR.B.PCT
550  */
551 typedef enum
552 {
553  IfxMsc_Parity_even = 0, /**< \brief Even Parity */
554  IfxMsc_Parity_odd = 1 /**< \brief Odd Parity */
555 } IfxMsc_Parity;
556 
557 /** \brief Downstream Status Register - Number Of Passive Time Frames\n
558  * Definition in Ifx_MSC.DSS.B.NPTF
559  */
560 typedef enum
561 {
562  IfxMsc_PassiveTimeFrameCount_0 = 0, /**< \brief No Passive time frames inserted */
563  IfxMsc_PassiveTimeFrameCount_1 = 1, /**< \brief 1 Passive time frames inserted */
564  IfxMsc_PassiveTimeFrameCount_2, /**< \brief 2 Passive time frames inserted */
565  IfxMsc_PassiveTimeFrameCount_3, /**< \brief 3 Passive time frames inserted */
566  IfxMsc_PassiveTimeFrameCount_4, /**< \brief 4 Passive time frames inserted */
567  IfxMsc_PassiveTimeFrameCount_5, /**< \brief 5 Passive time frames inserted */
568  IfxMsc_PassiveTimeFrameCount_6, /**< \brief 6 Passive time frames inserted */
569  IfxMsc_PassiveTimeFrameCount_7, /**< \brief 7 Passive time frames inserted */
570  IfxMsc_PassiveTimeFrameCount_8, /**< \brief 8 Passive time frames inserted */
571  IfxMsc_PassiveTimeFrameCount_9, /**< \brief 9 Passive time frames inserted */
572  IfxMsc_PassiveTimeFrameCount_10, /**< \brief 10 Passive time frames inserted */
573  IfxMsc_PassiveTimeFrameCount_11, /**< \brief 11 Passive time frames inserted */
574  IfxMsc_PassiveTimeFrameCount_12, /**< \brief 12 Passive time frames inserted */
575  IfxMsc_PassiveTimeFrameCount_13, /**< \brief 13 Passive time frames inserted */
576  IfxMsc_PassiveTimeFrameCount_14, /**< \brief 14 Passive time frames inserted */
577  IfxMsc_PassiveTimeFrameCount_15, /**< \brief 15 Passive time frames inserted */
579 
580 /** \brief Interrupt Control Register - Receive Data Interrupt Enable\n
581  * Definition in Ifx_MSC.ICR.B.RDIE
582  */
583 typedef enum
584 {
585  IfxMsc_ReceiveDataInterrupt_disabled = 0, /**< \brief Interrupt generation disabled */
586  IfxMsc_ReceiveDataInterrupt_onDataReceive = 1, /**< \brief An interrupt is generated when data is received and written into the upstream data registers */
587  IfxMsc_ReceiveDataInterrupt_onRdieSet = 2, /**< \brief An interrupt is generated as with RDIE = 01B but only if the received data is not equal to 00H */
588  IfxMsc_ReceiveDataInterrupt_onDataReceiveInUd3 = 3 /**< \brief An interrupt is generated as with RDIE = 01B but only if the received data is not equal to 00H */
590 
591 /** \brief Interrupt Control Register - Receive Data Interrupt Pointer\n
592  * Definition in Ifx_MSC.ICR.B.RDIP
593  */
594 typedef enum
595 {
596  IfxMsc_ReceiveDataInterruptNode_SR0 = 0, /**< \brief Service request output SR0 selected */
597  IfxMsc_ReceiveDataInterruptNode_SR1, /**< \brief Service request output SR1 selected */
598  IfxMsc_ReceiveDataInterruptNode_SR2, /**< \brief Service request output SR2 selected */
599  IfxMsc_ReceiveDataInterruptNode_SR3, /**< \brief Service request output SR3 selected */
601 
602 /** \brief Output Control Register - SDI Line Polarity\n
603  * Definition in Ifx_MSC.OCR.B.ILP
604  */
605 typedef enum
606 {
607  IfxMsc_SdiLinePolarity_likeSi = 0, /**< \brief SDI and SI signal polarities are identical */
608  IfxMsc_SdiLinePolarity_invertedSi = 1 /**< \brief SDI and SI signal polarities are inverted */
610 
611 /** \brief Output Control Register - Serial Data Input Selection\n
612  * Definition in Ifx_MSC.OCR.B.SDISEL
613  */
614 typedef enum
615 {
616  IfxMsc_SerialDataInput_0 = 0, /**< \brief SDI0 is selected for the SDI of the upstream channel */
617  IfxMsc_SerialDataInput_1, /**< \brief SDI1 is selected for the SDI of the upstream channel */
618  IfxMsc_SerialDataInput_2, /**< \brief SDI2 is selected for the SDI of the upstream channel */
619  IfxMsc_SerialDataInput_3, /**< \brief SDI3 is selected for the SDI of the upstream channel */
620  IfxMsc_SerialDataInput_4, /**< \brief SDI4 is selected for the SDI of the upstream channel */
621  IfxMsc_SerialDataInput_5, /**< \brief SDI5 is selected for the SDI of the upstream channel */
622  IfxMsc_SerialDataInput_6, /**< \brief SDI6 is selected for the SDI of the upstream channel */
623  IfxMsc_SerialDataInput_7, /**< \brief SDI7 is selected for the SDI of the upstream channel */
625 
626 /** \brief Service Request Delay\n
627  * Definition in Ifx_MSC.USR.B.SRDC
628  */
629 typedef enum
630 {
631  IfxMsc_ServiceRequestDelay_noDelay = 0, /**< \brief No Delay */
632  IfxMsc_ServiceRequestDelay_1bit = 1 /**< \brief Delay of 1 bit time */
634 
635 /** \brief Asynchronous Block Configuration Register - Duration of the Low/High Phase of the Shift Clock\n
636  * Definition in Ifx_MSC.ABC.B.LOW and Ifx_MSC.ABC.B.HIGH
637  */
638 typedef enum
639 {
640  IfxMsc_ShiftClockPhaseDuration_1 = 0, /**< \brief Duration in periods of f_A is 1 */
641  IfxMsc_ShiftClockPhaseDuration_2, /**< \brief Duration in periods of f_A is 2 */
642  IfxMsc_ShiftClockPhaseDuration_3, /**< \brief Duration in periods of f_A is 3 */
643  IfxMsc_ShiftClockPhaseDuration_4, /**< \brief Duration in periods of f_A is 4 */
644  IfxMsc_ShiftClockPhaseDuration_5, /**< \brief Duration in periods of f_A is 5 */
645  IfxMsc_ShiftClockPhaseDuration_6, /**< \brief Duration in periods of f_A is 6 */
646  IfxMsc_ShiftClockPhaseDuration_7, /**< \brief Duration in periods of f_A is 7 */
647  IfxMsc_ShiftClockPhaseDuration_8, /**< \brief Duration in periods of f_A is 8 */
648  IfxMsc_ShiftClockPhaseDuration_9, /**< \brief Duration in periods of f_A is 9 */
649  IfxMsc_ShiftClockPhaseDuration_10, /**< \brief Duration in periods of f_A is 10 */
650  IfxMsc_ShiftClockPhaseDuration_11, /**< \brief Duration in periods of f_A is 11 */
651  IfxMsc_ShiftClockPhaseDuration_12, /**< \brief Duration in periods of f_A is 12 */
652  IfxMsc_ShiftClockPhaseDuration_13, /**< \brief Duration in periods of f_A is 13 */
653  IfxMsc_ShiftClockPhaseDuration_14, /**< \brief Duration in periods of f_A is 14 */
654  IfxMsc_ShiftClockPhaseDuration_15, /**< \brief Duration in periods of f_A is 15 */
655  IfxMsc_ShiftClockPhaseDuration_16, /**< \brief Duration in periods of f_A is 16 */
657 
658 /** \brief Clock Control Register - Sleep Mode Enable Control
659  * Definition in Ifx_MSC.CLC.B.EDIS
660  */
661 typedef enum
662 {
663  IfxMsc_SleepMode_disabled = 0, /**< \brief module sleep mode is disabled */
664  IfxMsc_SleepMode_enabled = 1 /**< \brief module sleep mode is enabled */
666 
667 /** \brief Output Control Register - SOP Line Polarity\n
668  * Definition in Ifx_MSC.OCR.B.SLP
669  */
670 typedef enum
671 {
672  IfxMsc_SoLinePolarity_nonInverted = 0, /**< \brief SOP and SO polarity is identical */
673  IfxMsc_SoLinePolarity_inverted = 1 /**< \brief SOP and SO polarity is inverted */
675 
676 /** \brief Downstream Select Data Source Low Register - Select Source for - SRL and SRHNumber Of Passive Time Frames\n
677  * Definition in Ifx_MSC.DSDSL and Ifx_MSC.DSDSH
678  */
679 typedef enum
680 {
681  IfxMsc_Source_downstreamDataRegister = 0, /**< \brief SRx[16] is taken from data Register DD.DDL[xx] */
682  IfxMsc_Source_alternateInputLine = 2, /**< \brief SRx[16] is taken from ALTINL input line */
683  IfxMsc_Source_alternateInputLineInverted = 3 /**< \brief SRx[16] is taken from ALTINL input line in inverted state */
684 } IfxMsc_Source;
685 
686 /** \brief Msc Targets - use as chip enable selection for ENH, ENL and ENC
687  */
688 typedef enum
689 {
690  IfxMsc_Target_en0 = 0, /**< \brief Target EN0 */
691  IfxMsc_Target_en1, /**< \brief Target EN1 */
692  IfxMsc_Target_en2, /**< \brief Target EN2 */
693  IfxMsc_Target_en3, /**< \brief Target EN3 */
694 } IfxMsc_Target;
695 
696 /** \brief Interrupt Control Register - Time Frame Interrupt Enable\n
697  * Definition in Ifx_MSC.ICR.B.TFIE
698  */
699 typedef enum
700 {
701  IfxMsc_TimeFrameInterrupt_disabled = 0, /**< \brief Interrupt generation disabled */
702  IfxMsc_TimeFrameInterrupt_enabled = 1 /**< \brief Interrupt generation enabled */
704 
705 /** \brief Interrupt Control Register - Time Frame Interrupt Pointer\n
706  * Definition in Ifx_MSC.ICR.B.TFIP
707  */
708 typedef enum
709 {
710  IfxMsc_TimeFrameInterruptNode_SR0 = 0, /**< \brief Service request output SR0 selected */
711  IfxMsc_TimeFrameInterruptNode_SR1, /**< \brief Service request output SR1 selected */
712  IfxMsc_TimeFrameInterruptNode_SR2, /**< \brief Service request output SR2 selected */
713  IfxMsc_TimeFrameInterruptNode_SR3, /**< \brief Service request output SR3 selected */
715 
716 /** \brief Downstream Channel Transmission Mode\n
717  * Definition in Ifx_MSC.DSC.B.TM
718  */
719 typedef enum
720 {
721  IfxMsc_TransmissionMode_triggered = 0, /**< \brief Triggered Mode */
722  IfxMsc_TransmissionMode_dataRepetition = 1 /**< \brief Data Repetition Mode */
724 
725 /** \brief Asynchronous Block Configuration Register - Underflow Interrupt Enable\n
726  * Definition in Ifx_MSC.ABC.B.UIE
727  */
728 typedef enum
729 {
730  IfxMsc_UnderflowInterrupt_disabled = 0, /**< \brief Disables the path of the Underflow interrupt towards the interrupt node */
731  IfxMsc_UnderflowInterrupt_enabled = 1 /**< \brief Enables the path of the Underflow interrupt towards the interrupt node */
733 
734 /** \brief Asynchronous Block Configuration Register - Underflow Interrupt Node Pointer\n
735  * Definition in Ifx_MSC.ABC.B.UIP
736  */
737 typedef enum
738 {
739  IfxMsc_UnderflowInterruptNode_SR0 = 0, /**< \brief Service request output SR0 selected */
740  IfxMsc_UnderflowInterruptNode_SR1, /**< \brief Service request output SR1 selected */
741  IfxMsc_UnderflowInterruptNode_SR2, /**< \brief Service request output SR2 selected */
742  IfxMsc_UnderflowInterruptNode_SR3, /**< \brief Service request output SR3 selected */
743  IfxMsc_UnderflowInterruptNode_SR4, /**< \brief Service request output SR4 selected */
745 
746 /** \brief Channel Frame Type\n
747  * Definition in Ifx_MSC.USR.B.UFT
748  */
749 typedef enum
750 {
751  IfxMsc_UpstreamChannelFrameType_12bit = 0, /**< \brief 12-bit Upstream frame selected */
752  IfxMsc_UpstreamChannelFrameType_16bit = 1 /**< \brief 16-bit Upstream frame selected */
754 
755 /** \brief Upstream Receiving Rate\n
756  * Definition in Ifx_MSC.USR.B.URR
757  */
758 typedef enum
759 {
760  IfxMsc_UpstreamChannelReceivingRate_disabled = 0, /**< \brief Disabled */
761  IfxMsc_UpstreamChannelReceivingRate_4 = 1, /**< \brief Baud rate = f_MSC / 4 */
762  IfxMsc_UpstreamChannelReceivingRate_8 = 2, /**< \brief Baud rate = f_MSC / 8 */
763  IfxMsc_UpstreamChannelReceivingRate_16 = 3, /**< \brief Baud rate = f_MSC / 16 */
764  IfxMsc_UpstreamChannelReceivingRate_32 = 4, /**< \brief Baud rate = f_MSC / 32 */
765  IfxMsc_UpstreamChannelReceivingRate_64 = 5, /**< \brief Baud rate = f_MSC / 64 */
766  IfxMsc_UpstreamChannelReceivingRate_128 = 6, /**< \brief Baud rate = f_MSC / 128 */
767  IfxMsc_UpstreamChannelReceivingRate_256 = 7 /**< \brief Baud rate = f_MSC / 256 */
769 
770 /** \brief Upstream Control Enhanced Register 1 - Upstream Timeout Interrupt Enable\n
771  * Definition in Ifx_MSC.USCE.B.USTOEN
772  */
773 typedef enum
774 {
775  IfxMsc_UpstreamTimeoutInterrupt_disabled = 0, /**< \brief Upstream Timeout Interrupt Disabled */
776  IfxMsc_UpstreamTimeoutInterrupt_enabled = 1 /**< \brief Upstream Timeout Interrupt Enabled */
778 
779 /** \brief Upstream Control Enhanced Register 1 - Upstream Timeout Interrupt Node Pointer\n
780  * Definition in Ifx_MSC.USCE.B.USTOIP
781  */
782 typedef enum
783 {
784  IfxMsc_UpstreamTimeoutInterruptNode_SR0 = 0, /**< \brief Service request output SR0 selected */
785  IfxMsc_UpstreamTimeoutInterruptNode_SR1, /**< \brief Service request output SR1 selected */
786  IfxMsc_UpstreamTimeoutInterruptNode_SR2, /**< \brief Service request output SR2 selected */
787  IfxMsc_UpstreamTimeoutInterruptNode_SR3, /**< \brief Service request output SR3 selected */
789 
790 /** \brief Upstream Control Enhanced Register 1 - Upstream Timeout Prescaler\n
791  * Definition in Ifx_MSC.USCE.B.USTOPRE
792  */
793 typedef enum
794 {
795  IfxMsc_UpstreamTimeoutPrescaler_1 = 0, /**< \brief Prescale value 1 for the upstream time-out limit */
796  IfxMsc_UpstreamTimeoutPrescaler_2 = 1, /**< \brief Prescale value 2 for the upstream time-out limit */
797  IfxMsc_UpstreamTimeoutPrescaler_4 = 2, /**< \brief Prescale value 4 for the upstream time-out limit */
798  IfxMsc_UpstreamTimeoutPrescaler_8 = 3, /**< \brief Prescale value 8 for the upstream time-out limit */
799  IfxMsc_UpstreamTimeoutPrescaler_16 = 4, /**< \brief Prescale value 16 for the upstream time-out limit */
800  IfxMsc_UpstreamTimeoutPrescaler_32 = 5, /**< \brief Prescale value 32 for the upstream time-out limit */
801  IfxMsc_UpstreamTimeoutPrescaler_64 = 6, /**< \brief Prescale value 64 for the upstream time-out limit */
802  IfxMsc_UpstreamTimeoutPrescaler_128 = 7, /**< \brief Prescale value 128 for the upstream time-out limit */
803  IfxMsc_UpstreamTimeoutPrescaler_256 = 8, /**< \brief Prescale value 256 for the upstream time-out limit */
804  IfxMsc_UpstreamTimeoutPrescaler_512 = 9, /**< \brief Prescale value 512 for the upstream time-out limit */
805  IfxMsc_UpstreamTimeoutPrescaler_1024 = 10, /**< \brief Prescale value 1024 for the upstream time-out limit */
806  IfxMsc_UpstreamTimeoutPrescaler_2048 = 11, /**< \brief Prescale value 2048 for the upstream time-out limit */
807  IfxMsc_UpstreamTimeoutPrescaler_4096 = 12, /**< \brief Prescale value 4096 for the upstream time-out limit */
808  IfxMsc_UpstreamTimeoutPrescaler_8192 = 13, /**< \brief Prescale value 8192 for the upstream time-out limit */
809  IfxMsc_UpstreamTimeoutPrescaler_16384 = 14, /**< \brief Prescale value 16384 for the upstream time-out limit */
810  IfxMsc_UpstreamTimeoutPrescaler_32768 = 15 /**< \brief Prescale value 32768 for the upstream time-out limit */
812 
813 /** \brief Upstream Control Enhanced Register 1 - Upstream Timeout Value\n
814  * Definition in Ifx_MSC.USCE.B.USTOVAL
815  */
816 typedef enum
817 {
818  IfxMsc_UpstreamTimeoutValue_1 = 0, /**< \brief Upstream timeout value for the N-Divider */
819  IfxMsc_UpstreamTimeoutValue_2, /**< \brief Upstream timeout value for the N-Divider */
820  IfxMsc_UpstreamTimeoutValue_3, /**< \brief Upstream timeout value for the N-Divider */
821  IfxMsc_UpstreamTimeoutValue_4, /**< \brief Upstream timeout value for the N-Divider */
822  IfxMsc_UpstreamTimeoutValue_5, /**< \brief Upstream timeout value for the N-Divider */
823  IfxMsc_UpstreamTimeoutValue_6, /**< \brief Upstream timeout value for the N-Divider */
824  IfxMsc_UpstreamTimeoutValue_7, /**< \brief Upstream timeout value for the N-Divider */
825  IfxMsc_UpstreamTimeoutValue_8, /**< \brief Upstream timeout value for the N-Divider */
826  IfxMsc_UpstreamTimeoutValue_9, /**< \brief Upstream timeout value for the N-Divider */
827  IfxMsc_UpstreamTimeoutValue_10, /**< \brief Upstream timeout value for the N-Divider */
828  IfxMsc_UpstreamTimeoutValue_11, /**< \brief Upstream timeout value for the N-Divider */
829  IfxMsc_UpstreamTimeoutValue_12, /**< \brief Upstream timeout value for the N-Divider */
830  IfxMsc_UpstreamTimeoutValue_13, /**< \brief Upstream timeout value for the N-Divider */
831  IfxMsc_UpstreamTimeoutValue_14, /**< \brief Upstream timeout value for the N-Divider */
832  IfxMsc_UpstreamTimeoutValue_15, /**< \brief Upstream timeout value for the N-Divider */
833  IfxMsc_UpstreamTimeoutValue_16, /**< \brief Upstream timeout value for the N-Divider */
835 
836 /** \} */
837 
838 /** \addtogroup IfxLld_Msc_Std_Config_Flags
839  * \{ */
840 
841 /******************************************************************************/
842 /*-------------------------Inline Function Prototypes-------------------------*/
843 /******************************************************************************/
844 
845 /** \brief Clear ABRA overflow flag
846  * \param msc pointer to the base of MSC registers
847  * \return None
848  */
849 IFX_INLINE void IfxMsc_clearAbraOverflowFlag(Ifx_MSC *msc);
850 
851 /** \brief Clear ABRA underflow flag
852  * \param msc pointer to the base of MSC registers
853  * \return None
854  */
855 IFX_INLINE void IfxMsc_clearAbraUnderflowFlag(Ifx_MSC *msc);
856 
857 /** \brief Clear Upstream timeout
858  * \param msc pointer to the base of MSC registers
859  * \return None
860  */
861 IFX_INLINE void IfxMsc_clearUpstreamTimeout(Ifx_MSC *msc);
862 
863 /** \brief Clear the valid flag
864  * \param msc pointer to the base of MSC registers
865  * \param upstreamIdx data register ID
866  * \return None
867  */
868 IFX_INLINE void IfxMsc_clearUpstreamValidFlag(Ifx_MSC *msc, uint8 upstreamIdx);
869 
870 /** \brief Get the status of the valid flag
871  * \param msc pointer to the base of MSC registers
872  * \param upstreamIdx data register ID
873  * \return Status TRUE or FALSE
874  */
875 IFX_INLINE boolean IfxMsc_getUpstreamValidFlag(Ifx_MSC *msc, uint8 upstreamIdx);
876 
877 /** \} */
878 
879 /** \addtogroup IfxLld_Msc_Std_Set_Command_Target
880  * \{ */
881 
882 /******************************************************************************/
883 /*-------------------------Inline Function Prototypes-------------------------*/
884 /******************************************************************************/
885 
886 /** \brief Select the target for command phase
887  * \param msc pointer to the base of MSC registers
888  * \param enX Target to be selected
889  * \return None
890  */
891 IFX_INLINE void IfxMsc_setCommandTarget(Ifx_MSC *msc, IfxMsc_Target enX);
892 
893 /** \} */
894 
895 /** \addtogroup IfxLld_Msc_Std_Set_Data
896  * \{ */
897 
898 /******************************************************************************/
899 /*-------------------------Inline Function Prototypes-------------------------*/
900 /******************************************************************************/
901 
902 /** \brief Select the target for data high phase
903  * \param msc pointer to the base of MSC registers
904  * \param enX Target to be selected
905  * \return None
906  */
907 IFX_INLINE void IfxMsc_setDataHighTarget(Ifx_MSC *msc, IfxMsc_Target enX);
908 
909 /** \brief Select the target for data low phase
910  * \param msc pointer to the base of MSC registers
911  * \param enX Target to be selected
912  * \return None
913  */
914 IFX_INLINE void IfxMsc_setDataLowTarget(Ifx_MSC *msc, IfxMsc_Target enX);
915 
916 /** \} */
917 
918 /** \addtogroup IfxLld_Msc_Std_Get_Data
919  * \{ */
920 
921 /******************************************************************************/
922 /*-------------------------Inline Function Prototypes-------------------------*/
923 /******************************************************************************/
924 
925 /** \brief Get the upstream data from upstream data register
926  * \param msc pointer to the base of MSC registers
927  * \param upstreamIdx Upstream data register ID
928  * \return Recevived data
929  */
930 IFX_INLINE uint16 IfxMsc_getData(Ifx_MSC *msc, uint8 upstreamIdx);
931 
932 /** \brief Get the selected target during high phase
933  * \param msc pointer to the base of MSC registers
934  * \return Selected target
935  */
937 
938 /** \brief Get the selected target during low phase
939  * \param msc pointer to the base of MSC registers
940  * \return Selected target
941  */
943 
944 /** \} */
945 
946 /** \addtogroup IfxLld_Msc_Std_Enable_Module
947  * \{ */
948 
949 /******************************************************************************/
950 /*-------------------------Global Function Prototypes-------------------------*/
951 /******************************************************************************/
952 
953 /** \brief Enable MSC kernel
954  * \param msc pointer to the base of MSC registers
955  * \return None
956  */
957 IFX_EXTERN void IfxMsc_enableModule(Ifx_MSC *msc);
958 
959 /** \} */
960 
961 /** \addtogroup IfxLld_Msc_Std_Reset_Module
962  * \{ */
963 
964 /******************************************************************************/
965 /*-------------------------Global Function Prototypes-------------------------*/
966 /******************************************************************************/
967 
968 /** \brief Clear reset bit of MSC kernel
969  * \param msc pointer to the base of MSC registers
970  * \return None
971  */
972 IFX_EXTERN void IfxMsc_clearReset(Ifx_MSC *msc);
973 
974 /** \brief Reset MSC kernel
975  * \param msc pointer to the base of MSC registers
976  * \return None
977  */
978 IFX_EXTERN void IfxMsc_resetModule(Ifx_MSC *msc);
979 
980 /** \} */
981 
982 /** \addtogroup IfxLld_Msc_Std_Baud_Calculator
983  * \{ */
984 
985 /******************************************************************************/
986 /*-------------------------Global Function Prototypes-------------------------*/
987 /******************************************************************************/
988 
989 /** \brief Get the NDD value for the supplied baud rate when when ABRA block is enabled
990  * \param baud Required baud rate
991  * \return NDD value
992  */
994 
995 /** \brief Get the step value for the supplied baud rate when divider mode is fractional
996  * \param msc pointer to the base of MSC registers
997  * \param baud Required baud rate
998  * \return Step value
999  */
1001 
1002 /** \brief Get the step value for the supplied baud rate when divider mode is normal
1003  * \param msc pointer to the base of MSC registers
1004  * \param baud Required baud rate
1005  * \return Step value
1006  */
1008 
1009 /** \} */
1010 
1011 /** \addtogroup IfxLld_Msc_Std_IO
1012  * \{ */
1013 
1014 /******************************************************************************/
1015 /*-------------------------Inline Function Prototypes-------------------------*/
1016 /******************************************************************************/
1017 
1018 /** \brief Initializes a EN output
1019  * \param en the EN Pin which should be configured
1020  * \param pinMode the pin output mode which should be configured
1021  * \param padDriver the pad driver mode which should be configured
1022  * \return None
1023  */
1025 
1026 /** \brief Initializes a FCLN output
1027  * \param fcln the FCLN Pin which should be configured
1028  * \param pinMode the pin output mode which should be configured
1029  * \param padDriver the pad driver mode which should be configured
1030  * \return None
1031  */
1033 
1034 /** \brief Initializes a FCLP output
1035  * \param fclp the FCLP Pin which should be configured
1036  * \param pinMode the pin output mode which should be configured
1037  * \param padDriver the pad driver mode which should be configured
1038  * \return None
1039  */
1041 
1042 /** \brief Initializes a INJ input
1043  * \param inj the INJ Pin which should be configured
1044  * \param pinMode the pin input mode which should be configured
1045  * \return None
1046  */
1048 
1049 /** \brief Initializes a SDI input
1050  * \param sdi the SDI Pin which should be configured
1051  * \param pinMode the pin input mode which should be configured
1052  * \return None
1053  */
1055 
1056 /** \brief Initializes a SON output
1057  * \param son the SON Pin which should be configured
1058  * \param pinMode the pin output mode which should be configured
1059  * \param padDriver the pad driver mode which should be configured
1060  * \return None
1061  */
1063 
1064 /** \brief Initializes a SOP output
1065  * \param sop the SOP Pin which should be configured
1066  * \param pinMode the pin output mode which should be configured
1067  * \param padDriver the pad driver mode which should be configured
1068  * \return None
1069  */
1071 
1072 /** \} */
1073 
1074 /******************************************************************************/
1075 /*-------------------------Global Function Prototypes-------------------------*/
1076 /******************************************************************************/
1077 
1078 /** \brief clear data frame interrupt flag
1079  * \param msc pointer to the base of MSC registers
1080  * \return None
1081  */
1083 
1084 /** \brief get the status of the active data frame
1085  * \param msc pointer to the base of MSC registers
1086  * \return Status TRUE or FALSE
1087  */
1088 IFX_EXTERN boolean IfxMsc_getActiveDataFrameStatus(Ifx_MSC *msc);
1089 
1090 /** \brief get the status of the data frame interrupt flag
1091  * \param msc pointer to the base of MSC registers
1092  * \return Status TRUE or FALSE
1093  */
1094 IFX_EXTERN boolean IfxMsc_getDataFrameInterruptFlag(Ifx_MSC *msc);
1095 
1096 /******************************************************************************/
1097 /*---------------------Inline Function Implementations------------------------*/
1098 /******************************************************************************/
1099 
1101 {
1102  /* Overflow Flag Clear */
1103  msc->ABC.B.OFM = 2;
1104 }
1105 
1106 
1108 {
1109  /* Underflow Flag Clear */
1110  msc->ABC.B.UFM = 2;
1111 }
1112 
1113 
1115 {
1116  /* Upstream Timeout Clear */
1117  msc->USCE.B.USTC = 1;
1118 }
1119 
1120 
1121 IFX_INLINE void IfxMsc_clearUpstreamValidFlag(Ifx_MSC *msc, uint8 upstreamIdx)
1122 {
1123  msc->UD[upstreamIdx].B.C = 1;
1124 }
1125 
1126 
1127 IFX_INLINE boolean IfxMsc_getUpstreamValidFlag(Ifx_MSC *msc, uint8 upstreamIdx)
1128 {
1129  boolean flag = 0;
1130 
1131  flag = msc->UD[upstreamIdx].B.V;
1132 
1133  return flag;
1134 }
1135 
1136 
1138 {
1139  /* Set command target - en0, en1, en2 or en3 */
1140  msc->OCR.B.CSC = enX;
1141 }
1142 
1143 
1145 {
1146  /* Set data high target - en0, en1, en2 or en3 */
1147  msc->OCR.B.CSH = enX;
1148 }
1149 
1150 
1152 {
1153  /* Set data low target - en0, en1, en2 or en3 */
1154  msc->OCR.B.CSL = enX;
1155 }
1156 
1157 
1158 IFX_INLINE uint16 IfxMsc_getData(Ifx_MSC *msc, uint8 upstreamIdx)
1159 {
1160  uint16 data = 0;
1161 
1162  data = msc->UD[upstreamIdx].B.DATA;
1163 
1164  return data;
1165 }
1166 
1167 
1169 {
1170  /* get data high target - en0, en1, en2 or en3 */
1171  return (IfxMsc_Target)msc->OCR.B.CSH;
1172 }
1173 
1174 
1176 {
1177  /* get data low target - en0, en1, en2 or en3 */
1178  return (IfxMsc_Target)msc->OCR.B.CSL;
1179 }
1180 
1181 
1183 {
1184  IfxPort_setPinModeOutput(en->pin.port, en->pin.pinIndex, pinMode, en->select);
1185  IfxPort_setPinPadDriver(en->pin.port, en->pin.pinIndex, padDriver);
1186 }
1187 
1188 
1190 {
1191  IfxPort_setPinModeOutput(fcln->pin.port, fcln->pin.pinIndex, pinMode, fcln->select);
1192  IfxPort_setPinPadDriver(fcln->pin.port, fcln->pin.pinIndex, padDriver);
1193 }
1194 
1195 
1197 {
1198  IfxPort_setPinModeOutput(fclp->pin.port, fclp->pin.pinIndex, pinMode, fclp->select);
1199  IfxPort_setPinPadDriver(fclp->pin.port, fclp->pin.pinIndex, padDriver);
1200 }
1201 
1202 
1204 {
1205  IfxPort_setPinModeInput(inj->pin.port, inj->pin.pinIndex, pinMode);
1206 }
1207 
1208 
1210 {
1211  IfxPort_setPinModeInput(sdi->pin.port, sdi->pin.pinIndex, pinMode);
1212  sdi->module->OCR.B.SDISEL = sdi->select;
1213 }
1214 
1215 
1217 {
1218  IfxPort_setPinModeOutput(son->pin.port, son->pin.pinIndex, pinMode, son->select);
1219  IfxPort_setPinPadDriver(son->pin.port, son->pin.pinIndex, padDriver);
1220 }
1221 
1222 
1224 {
1225  IfxPort_setPinModeOutput(sop->pin.port, sop->pin.pinIndex, pinMode, sop->select);
1226  IfxPort_setPinPadDriver(sop->pin.port, sop->pin.pinIndex, padDriver);
1227 }
1228 
1229 
1230 #endif /* IFXMSC_H */