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30 #include "IfxScu_bf.h"
31 #include "IfxFlash_bf.h"
36 #ifndef IFX_CFG_SCU_XTAL_FREQUENCY
37 # define IFX_CFG_SCU_XTAL_FREQUENCY 20000000
38 # warning "IFX_CFG_SCU_XTAL_FREQUENCY not specified in your IfxCfg.h file."
39 # warning "Please doublecheck the external XTAL frequency with the default setting of 20 MHz!"
42 #ifndef IFX_CFG_SCU_PLL_FREQUENCY
43 # define IFX_CFG_SCU_PLL_FREQUENCY 200000000
46 #define IFXSCU_VCO_BASE_FREQUENCY (100000000.0)
47 #define IFXSCU_EVR_OSC_FREQUENCY (100000000.0)
51 #define IFXSCU_PLL_FREERUNNING_FREQUENCY (100000000.0)
62 #ifndef IFXSCU_CFG_PLL_STEPS_16MHZ_80MHZ
64 #define IFXSCU_CFG_PLL_STEPS_16MHZ_80MHZ \
72 #ifndef IFXSCU_CFG_PLL_STEPS_16MHZ_133MHZ
74 #define IFXSCU_CFG_PLL_STEPS_16MHZ_133MHZ \
87 #ifndef IFXSCU_CFG_PLL_STEPS_16MHZ_160MHZ
89 #define IFXSCU_CFG_PLL_STEPS_16MHZ_160MHZ \
102 #ifndef IFXSCU_CFG_PLL_STEPS_16MHZ_200MHZ
104 #define IFXSCU_CFG_PLL_STEPS_16MHZ_200MHZ \
122 #ifndef IFXSCU_CFG_PLL_STEPS_16MHZ_240MHZ
124 #define IFXSCU_CFG_PLL_STEPS_16MHZ_240MHZ \
143 #ifndef IFXSCU_CFG_PLL_STEPS_20MHZ_80MHZ
145 #define IFXSCU_CFG_PLL_STEPS_20MHZ_80MHZ \
153 #ifndef IFXSCU_CFG_PLL_STEPS_20MHZ_133MHZ
155 #define IFXSCU_CFG_PLL_STEPS_20MHZ_133MHZ \
168 #ifndef IFXSCU_CFG_PLL_STEPS_20MHZ_160MHZ
170 #define IFXSCU_CFG_PLL_STEPS_20MHZ_160MHZ \
183 #ifndef IFXSCU_CFG_PLL_STEPS_20MHZ_200MHZ
185 #define IFXSCU_CFG_PLL_STEPS_20MHZ_200MHZ \
203 #ifndef IFXSCU_CFG_PLL_STEPS_20MHZ_240MHZ
205 #define IFXSCU_CFG_PLL_STEPS_20MHZ_240MHZ \
223 #ifndef IFXSCU_CFG_PLL_STEPS_20MHZ_300MHZ
225 #define IFXSCU_CFG_PLL_STEPS_20MHZ_300MHZ \
244 #ifndef IFXSCU_CFG_PLL_STEPS_40MHZ_80MHZ
246 #define IFXSCU_CFG_PLL_STEPS_40MHZ_80MHZ \
254 #ifndef IFXSCU_CFG_PLL_STEPS_40MHZ_133MHZ
256 #define IFXSCU_CFG_PLL_STEPS_40MHZ_133MHZ \
269 #ifndef IFXSCU_CFG_PLL_STEPS_40MHZ_160MHZ
271 #define IFXSCU_CFG_PLL_STEPS_40MHZ_160MHZ \
284 #ifndef IFXSCU_CFG_PLL_STEPS_40MHZ_200MHZ
286 #define IFXSCU_CFG_PLL_STEPS_40MHZ_200MHZ \
304 #ifndef IFXSCU_CFG_PLL_STEPS_40MHZ_240MHZ
306 #define IFXSCU_CFG_PLL_STEPS_40MHZ_240MHZ \
324 #ifndef IFXSCU_CFG_PLL_STEPS_40MHZ_300MHZ
326 #define IFXSCU_CFG_PLL_STEPS_40MHZ_300MHZ \
345 #ifndef IFXSCU_CFG_PLL_STEPS_8MHZ_80MHZ
347 #define IFXSCU_CFG_PLL_STEPS_8MHZ_80MHZ \
355 #ifndef IFXSCU_CFG_PLL_STEPS_8MHZ_160MHZ
357 #define IFXSCU_CFG_PLL_STEPS_8MHZ_160MHZ \
370 #ifndef IFXSCU_CFG_PLL_STEPS_8MHZ_200MHZ
372 #define IFXSCU_CFG_PLL_STEPS_8MHZ_200MHZ \
398 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_80MHZ
400 #define IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_80MHZ \
402 {(1 - 1), (40 - 1), (7 - 1), 0.000200F}
405 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_133MHZ
407 #define IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_133MHZ \
409 {(1 - 1), (50 - 1), (8 - 1), 0.000200F}
412 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_160MHZ
414 #define IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_160MHZ \
416 {(1 - 1), (40 - 1), (6 - 1), 0.000200F}
419 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_200MHZ
421 #define IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_200MHZ \
423 {(1 - 1), (50 - 1), (8 - 1), 0.000200F}
426 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_240MHZ
428 #define IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_240MHZ \
430 {(1 - 1), (45 - 1), (7 - 1), 0.000200F}
435 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_80MHZ
437 #define IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_80MHZ \
439 {(2 - 1), (64 - 1), (7 - 1), 0.000200F}
442 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_133MHZ
444 #define IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_133MHZ \
446 {(2 - 1), (80 - 1), (8 - 1), 0.000200F}
449 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_160MHZ
451 #define IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_160MHZ \
453 {(2 - 1), (64 - 1), (6 - 1), 0.000200F}
456 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_200MHZ
458 #define IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_200MHZ \
460 {(2 - 1), (60 - 1), (6 - 1), 0.000200F}
463 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_240MHZ
465 #define IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_240MHZ \
467 {(2 - 1), (72 - 1), (7 - 1), 0.000200F}
470 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_300MHZ
472 #define IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_300MHZ \
474 {(2 - 1), (60 - 1), (6 - 1), 0.000200F}
479 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_80MHZ
481 #define IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_80MHZ \
483 {(4 - 1), (64 - 1), (7 - 1), 0.000200F}
486 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_133MHZ
488 #define IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_133MHZ \
490 {(4 - 1), (80 - 1), (8 - 1), 0.000200F}
493 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_160MHZ
495 #define IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_160MHZ \
497 {(4 - 1), (64 - 1), (6 - 1), 0.000200F}
500 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_200MHZ
502 #define IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_200MHZ \
504 {(4 - 1), (60 - 1), (6 - 1), 0.000200F}
507 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_240MHZ
509 #define IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_240MHZ \
511 {(4 - 1), (72 - 1), (7 - 1), 0.000200F}
514 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_300MHZ
516 #define IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_300MHZ \
518 {(4 - 1), (60 - 1), (6 - 1), 0.000200F}
524 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_8MHZ_80MHZ
526 #define IFXSCU_CFG_PLL_INITIAL_STEP_8MHZ_80MHZ \
528 {(1 - 1), (50 - 1), (5 - 1), 0.000200F}
531 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_8MHZ_160MHZ
533 #define IFXSCU_CFG_PLL_INITIAL_STEP_8MHZ_160MHZ \
535 {(1 - 1), (60 - 1), (5 - 1), 0.000200F}
538 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_8MHZ_200MHZ
540 #define IFXSCU_CFG_PLL_INITIAL_STEP_8MHZ_200MHZ \
542 {(1 - 1), (75 - 1), (6 - 1), 0.000200F}
554 #ifndef IFXSCU_CFG_MAXDIV_80MHZ
556 #define IFXSCU_CFG_MAXDIV_80MHZ (1)
559 #ifndef IFXSCU_CFG_MAXDIV_133MHZ
561 #define IFXSCU_CFG_MAXDIV_133MHZ (1)
564 #ifndef IFXSCU_CFG_MAXDIV_160MHZ
566 #define IFXSCU_CFG_MAXDIV_160MHZ (1)
569 #ifndef IFXSCU_CFG_MAXDIV_200MHZ
571 #define IFXSCU_CFG_MAXDIV_200MHZ (1)
574 #ifndef IFXSCU_CFG_MAXDIV_240MHZ
576 #define IFXSCU_CFG_MAXDIV_240MHZ (1)
579 #ifndef IFXSCU_CFG_MAXDIV_300MHZ
581 #define IFXSCU_CFG_MAXDIV_300MHZ (1)
584 #ifndef IFXSCU_CFG_SRIDIV_80MHZ
586 #define IFXSCU_CFG_SRIDIV_80MHZ (IFXSCU_CFG_MAXDIV_80MHZ)
589 #ifndef IFXSCU_CFG_SRIDIV_133MHZ
591 #define IFXSCU_CFG_SRIDIV_133MHZ (IFXSCU_CFG_MAXDIV_133MHZ)
594 #ifndef IFXSCU_CFG_SRIDIV_160MHZ
596 #define IFXSCU_CFG_SRIDIV_160MHZ (IFXSCU_CFG_MAXDIV_160MHZ)
599 #ifndef IFXSCU_CFG_SRIDIV_200MHZ
601 #define IFXSCU_CFG_SRIDIV_200MHZ (IFXSCU_CFG_MAXDIV_200MHZ)
604 #ifndef IFXSCU_CFG_SRIDIV_240MHZ
606 #define IFXSCU_CFG_SRIDIV_240MHZ (IFXSCU_CFG_MAXDIV_240MHZ)
609 #ifndef IFXSCU_CFG_SRIDIV_300MHZ
611 #define IFXSCU_CFG_SRIDIV_300MHZ (IFXSCU_CFG_MAXDIV_300MHZ)
614 #ifndef IFXSCU_CFG_BAUD1DIV_80MHZ
616 #define IFXSCU_CFG_BAUD1DIV_80MHZ (IFXSCU_CFG_MAXDIV_80MHZ)
619 #ifndef IFXSCU_CFG_BAUD1DIV_133MHZ
621 #define IFXSCU_CFG_BAUD1DIV_133MHZ (IFXSCU_CFG_MAXDIV_133MHZ * 2)
624 #ifndef IFXSCU_CFG_BAUD1DIV_160MHZ
626 #define IFXSCU_CFG_BAUD1DIV_160MHZ (IFXSCU_CFG_MAXDIV_160MHZ * 2)
629 #ifndef IFXSCU_CFG_BAUD1DIV_200MHZ
631 #define IFXSCU_CFG_BAUD1DIV_200MHZ (IFXSCU_CFG_MAXDIV_200MHZ * 2)
634 #ifndef IFXSCU_CFG_BAUD1DIV_240MHZ
636 #define IFXSCU_CFG_BAUD1DIV_240MHZ (IFXSCU_CFG_MAXDIV_240MHZ * 3)
639 #ifndef IFXSCU_CFG_BAUD1DIV_300MHZ
641 #define IFXSCU_CFG_BAUD1DIV_300MHZ (IFXSCU_CFG_MAXDIV_300MHZ * 3)
644 #ifndef IFXSCU_CFG_BAUD2DIV_80MHZ
646 #define IFXSCU_CFG_BAUD2DIV_80MHZ (IFXSCU_CFG_MAXDIV_80MHZ)
649 #ifndef IFXSCU_CFG_BAUD2DIV_133MHZ
651 #define IFXSCU_CFG_BAUD2DIV_133MHZ (IFXSCU_CFG_MAXDIV_133MHZ)
654 #ifndef IFXSCU_CFG_BAUD2DIV_160MHZ
656 #define IFXSCU_CFG_BAUD2DIV_160MHZ (IFXSCU_CFG_MAXDIV_160MHZ)
659 #ifndef IFXSCU_CFG_BAUD2DIV_200MHZ
661 #define IFXSCU_CFG_BAUD2DIV_200MHZ (IFXSCU_CFG_MAXDIV_200MHZ)
664 #ifndef IFXSCU_CFG_BAUD2DIV_240MHZ
666 #define IFXSCU_CFG_BAUD2DIV_240MHZ (IFXSCU_CFG_MAXDIV_240MHZ)
669 #ifndef IFXSCU_CFG_BAUD2DIV_300MHZ
671 #define IFXSCU_CFG_BAUD2DIV_300MHZ (IFXSCU_CFG_MAXDIV_300MHZ)
674 #ifndef IFXSCU_CFG_SPBDIV_80MHZ
676 #define IFXSCU_CFG_SPBDIV_80MHZ (IFXSCU_CFG_MAXDIV_80MHZ)
679 #ifndef IFXSCU_CFG_SPBDIV_133MHZ
681 #define IFXSCU_CFG_SPBDIV_133MHZ (IFXSCU_CFG_MAXDIV_133MHZ * 2)
684 #ifndef IFXSCU_CFG_SPBDIV_160MHZ
686 #define IFXSCU_CFG_SPBDIV_160MHZ (IFXSCU_CFG_MAXDIV_160MHZ * 2)
689 #ifndef IFXSCU_CFG_SPBDIV_200MHZ
691 #define IFXSCU_CFG_SPBDIV_200MHZ (IFXSCU_CFG_MAXDIV_200MHZ * 2)
694 #ifndef IFXSCU_CFG_SPBDIV_240MHZ
696 #define IFXSCU_CFG_SPBDIV_240MHZ (IFXSCU_CFG_MAXDIV_240MHZ * 3)
699 #ifndef IFXSCU_CFG_SPBDIV_300MHZ
701 #define IFXSCU_CFG_SPBDIV_300MHZ (IFXSCU_CFG_MAXDIV_300MHZ * 3)
704 #ifndef IFXSCU_CFG_FSI2DIV_80MHZ
706 #define IFXSCU_CFG_FSI2DIV_80MHZ (IFXSCU_CFG_MAXDIV_80MHZ)
709 #ifndef IFXSCU_CFG_FSI2DIV_133MHZ
711 #define IFXSCU_CFG_FSI2DIV_133MHZ (IFXSCU_CFG_MAXDIV_133MHZ)
714 #ifndef IFXSCU_CFG_FSI2DIV_160MHZ
716 #define IFXSCU_CFG_FSI2DIV_160MHZ (IFXSCU_CFG_MAXDIV_160MHZ)
719 #ifndef IFXSCU_CFG_FSI2DIV_200MHZ
721 #define IFXSCU_CFG_FSI2DIV_200MHZ (IFXSCU_CFG_MAXDIV_200MHZ)
724 #ifndef IFXSCU_CFG_FSI2DIV_240MHZ
726 #define IFXSCU_CFG_FSI2DIV_240MHZ (IFXSCU_CFG_MAXDIV_240MHZ)
729 #ifndef IFXSCU_CFG_FSI2DIV_300MHZ
731 #define IFXSCU_CFG_FSI2DIV_300MHZ (IFXSCU_CFG_MAXDIV_300MHZ)
734 #ifndef IFXSCU_CFG_FSIDIV_80MHZ
736 #define IFXSCU_CFG_FSIDIV_80MHZ (IFXSCU_CFG_MAXDIV_80MHZ)
739 #ifndef IFXSCU_CFG_FSIDIV_133MHZ
741 #define IFXSCU_CFG_FSIDIV_133MHZ (IFXSCU_CFG_MAXDIV_133MHZ * 2)
744 #ifndef IFXSCU_CFG_FSIDIV_160MHZ
746 #define IFXSCU_CFG_FSIDIV_160MHZ (IFXSCU_CFG_MAXDIV_160MHZ * 2)
749 #ifndef IFXSCU_CFG_FSIDIV_200MHZ
751 #define IFXSCU_CFG_FSIDIV_200MHZ (IFXSCU_CFG_MAXDIV_200MHZ * 2)
754 #ifndef IFXSCU_CFG_FSIDIV_240MHZ
756 #define IFXSCU_CFG_FSIDIV_240MHZ (IFXSCU_CFG_MAXDIV_240MHZ * 2)
759 #ifndef IFXSCU_CFG_FSIDIV_300MHZ
761 #define IFXSCU_CFG_FSIDIV_300MHZ (IFXSCU_CFG_MAXDIV_300MHZ * 2)
764 #ifndef IFXSCU_CFG_CANDIV_80MHZ
766 #define IFXSCU_CFG_CANDIV_80MHZ (IFXSCU_CFG_MAXDIV_80MHZ)
769 #ifndef IFXSCU_CFG_CANDIV_133MHZ
771 #define IFXSCU_CFG_CANDIV_133MHZ (IFXSCU_CFG_MAXDIV_133MHZ * 2)
774 #ifndef IFXSCU_CFG_CANDIV_160MHZ
776 #define IFXSCU_CFG_CANDIV_160MHZ (IFXSCU_CFG_MAXDIV_160MHZ * 2)
779 #ifndef IFXSCU_CFG_CANDIV_200MHZ
781 #define IFXSCU_CFG_CANDIV_200MHZ (IFXSCU_CFG_MAXDIV_200MHZ * 2)
784 #ifndef IFXSCU_CFG_CANDIV_240MHZ
786 #define IFXSCU_CFG_CANDIV_240MHZ (IFXSCU_CFG_MAXDIV_240MHZ * 3)
789 #ifndef IFXSCU_CFG_CANDIV_300MHZ
791 #define IFXSCU_CFG_CANDIV_300MHZ (IFXSCU_CFG_MAXDIV_300MHZ * 3)
794 #ifndef IFXSCU_CFG_ERAYDIV_80MHZ
796 #define IFXSCU_CFG_ERAYDIV_80MHZ (IFXSCU_CFG_MAXDIV_80MHZ)
799 #ifndef IFXSCU_CFG_ERAYDIV_133MHZ
801 #define IFXSCU_CFG_ERAYDIV_133MHZ (IFXSCU_CFG_MAXDIV_133MHZ * 2)
804 #ifndef IFXSCU_CFG_ERAYDIV_160MHZ
806 #define IFXSCU_CFG_ERAYDIV_160MHZ (IFXSCU_CFG_MAXDIV_160MHZ * 2)
809 #ifndef IFXSCU_CFG_ERAYDIV_200MHZ
811 #define IFXSCU_CFG_ERAYDIV_200MHZ (IFXSCU_CFG_MAXDIV_200MHZ * 3)
814 #ifndef IFXSCU_CFG_ERAYDIV_240MHZ
816 #define IFXSCU_CFG_ERAYDIV_240MHZ (IFXSCU_CFG_MAXDIV_240MHZ * 3)
819 #ifndef IFXSCU_CFG_ERAYDIV_300MHZ
821 #define IFXSCU_CFG_ERAYDIV_300MHZ (IFXSCU_CFG_MAXDIV_300MHZ * 4)
824 #ifndef IFXSCU_CFG_STMDIV_80MHZ
826 #define IFXSCU_CFG_STMDIV_80MHZ (IFXSCU_CFG_MAXDIV_80MHZ)
829 #ifndef IFXSCU_CFG_STMDIV_133MHZ
831 #define IFXSCU_CFG_STMDIV_133MHZ (IFXSCU_CFG_MAXDIV_133MHZ * 2)
834 #ifndef IFXSCU_CFG_STMDIV_160MHZ
836 #define IFXSCU_CFG_STMDIV_160MHZ (IFXSCU_CFG_MAXDIV_160MHZ * 2)
839 #ifndef IFXSCU_CFG_STMDIV_200MHZ
841 #define IFXSCU_CFG_STMDIV_200MHZ (IFXSCU_CFG_MAXDIV_200MHZ * 2)
844 #ifndef IFXSCU_CFG_STMDIV_240MHZ
846 #define IFXSCU_CFG_STMDIV_240MHZ (IFXSCU_CFG_MAXDIV_240MHZ * 3)
849 #ifndef IFXSCU_CFG_STMDIV_300MHZ
851 #define IFXSCU_CFG_STMDIV_300MHZ (IFXSCU_CFG_MAXDIV_300MHZ * 3)
854 #ifndef IFXSCU_CFG_GTMDIV_80MHZ
856 #define IFXSCU_CFG_GTMDIV_80MHZ (IFXSCU_CFG_MAXDIV_80MHZ)
859 #ifndef IFXSCU_CFG_GTMDIV_133MHZ
861 #define IFXSCU_CFG_GTMDIV_133MHZ (IFXSCU_CFG_MAXDIV_133MHZ * 2)
864 #ifndef IFXSCU_CFG_GTMDIV_160MHZ
866 #define IFXSCU_CFG_GTMDIV_160MHZ (IFXSCU_CFG_MAXDIV_160MHZ * 2)
869 #ifndef IFXSCU_CFG_GTMDIV_200MHZ
871 #define IFXSCU_CFG_GTMDIV_200MHZ (IFXSCU_CFG_MAXDIV_200MHZ * 2)
874 #ifndef IFXSCU_CFG_GTMDIV_240MHZ
876 #define IFXSCU_CFG_GTMDIV_240MHZ (IFXSCU_CFG_MAXDIV_240MHZ * 3)
879 #ifndef IFXSCU_CFG_GTMDIV_300MHZ
881 #define IFXSCU_CFG_GTMDIV_300MHZ (IFXSCU_CFG_MAXDIV_300MHZ * 3)
884 #ifndef IFXSCU_CFG_ETHDIV_80MHZ
886 #define IFXSCU_CFG_ETHDIV_80MHZ (IFXSCU_CFG_MAXDIV_80MHZ * 2)
889 #ifndef IFXSCU_CFG_ETHDIV_133MHZ
891 #define IFXSCU_CFG_ETHDIV_133MHZ (IFXSCU_CFG_MAXDIV_133MHZ * 3)
894 #ifndef IFXSCU_CFG_ETHDIV_160MHZ
896 #define IFXSCU_CFG_ETHDIV_160MHZ (IFXSCU_CFG_MAXDIV_160MHZ * 4)
899 #ifndef IFXSCU_CFG_ETHDIV_200MHZ
901 #define IFXSCU_CFG_ETHDIV_200MHZ (IFXSCU_CFG_MAXDIV_200MHZ * 4)
904 #ifndef IFXSCU_CFG_ETHDIV_240MHZ
906 #define IFXSCU_CFG_ETHDIV_240MHZ (IFXSCU_CFG_MAXDIV_240MHZ * 5)
909 #ifndef IFXSCU_CFG_ETHDIV_300MHZ
911 #define IFXSCU_CFG_ETHDIV_300MHZ (IFXSCU_CFG_MAXDIV_300MHZ * 6)
914 #ifndef IFXSCU_CFG_ASCLINFDIV_80MHZ
916 #define IFXSCU_CFG_ASCLINFDIV_80MHZ (IFXSCU_CFG_MAXDIV_80MHZ)
919 #ifndef IFXSCU_CFG_ASCLINFDIV_133MHZ
921 #define IFXSCU_CFG_ASCLINFDIV_133MHZ (IFXSCU_CFG_MAXDIV_133MHZ)
924 #ifndef IFXSCU_CFG_ASCLINFDIV_160MHZ
926 #define IFXSCU_CFG_ASCLINFDIV_160MHZ (IFXSCU_CFG_MAXDIV_160MHZ)
929 #ifndef IFXSCU_CFG_ASCLINFDIV_200MHZ
931 #define IFXSCU_CFG_ASCLINFDIV_200MHZ (IFXSCU_CFG_MAXDIV_200MHZ)
934 #ifndef IFXSCU_CFG_ASCLINFDIV_240MHZ
936 #define IFXSCU_CFG_ASCLINFDIV_240MHZ (IFXSCU_CFG_MAXDIV_240MHZ)
939 #ifndef IFXSCU_CFG_ASCLINFDIV_300MHZ
941 #define IFXSCU_CFG_ASCLINFDIV_300MHZ (IFXSCU_CFG_MAXDIV_300MHZ)
944 #ifndef IFXSCU_CFG_ASCLINSDIV_80MHZ
946 #define IFXSCU_CFG_ASCLINSDIV_80MHZ (IFXSCU_CFG_MAXDIV_80MHZ)
949 #ifndef IFXSCU_CFG_ASCLINSDIV_133MHZ
951 #define IFXSCU_CFG_ASCLINSDIV_133MHZ (IFXSCU_CFG_MAXDIV_133MHZ * 2)
954 #ifndef IFXSCU_CFG_ASCLINSDIV_160MHZ
956 #define IFXSCU_CFG_ASCLINSDIV_160MHZ (IFXSCU_CFG_MAXDIV_160MHZ * 2)
959 #ifndef IFXSCU_CFG_ASCLINSDIV_200MHZ
961 #define IFXSCU_CFG_ASCLINSDIV_200MHZ (IFXSCU_CFG_MAXDIV_200MHZ * 2)
964 #ifndef IFXSCU_CFG_ASCLINSDIV_240MHZ
966 #define IFXSCU_CFG_ASCLINSDIV_240MHZ (IFXSCU_CFG_MAXDIV_240MHZ * 3)
969 #ifndef IFXSCU_CFG_ASCLINSDIV_300MHZ
971 #define IFXSCU_CFG_ASCLINSDIV_300MHZ (IFXSCU_CFG_MAXDIV_300MHZ * 3)
974 #ifndef IFXSCU_CFG_BBBDIV_80MHZ
976 #define IFXSCU_CFG_BBBDIV_80MHZ (IFXSCU_CFG_SRIDIV_80MHZ * 2)
979 #ifndef IFXSCU_CFG_BBBDIV_133MHZ
981 #define IFXSCU_CFG_BBBDIV_133MHZ (IFXSCU_CFG_SRIDIV_133MHZ * 2)
984 #ifndef IFXSCU_CFG_BBBDIV_160MHZ
986 #define IFXSCU_CFG_BBBDIV_160MHZ (IFXSCU_CFG_SRIDIV_160MHZ * 2)
989 #ifndef IFXSCU_CFG_BBBDIV_200MHZ
991 #define IFXSCU_CFG_BBBDIV_200MHZ (IFXSCU_CFG_SRIDIV_200MHZ * 2)
994 #ifndef IFXSCU_CFG_BBBDIV_240MHZ
996 #define IFXSCU_CFG_BBBDIV_240MHZ (IFXSCU_CFG_SRIDIV_240MHZ * 2)
999 #ifndef IFXSCU_CFG_BBBDIV_300MHZ
1001 #define IFXSCU_CFG_BBBDIV_300MHZ (IFXSCU_CFG_SRIDIV_300MHZ * 2)
1004 #ifndef IFXSCU_CFG_CPU0DIV_80MHZ
1006 #define IFXSCU_CFG_CPU0DIV_80MHZ (0)
1009 #ifndef IFXSCU_CFG_CPU0DIV_133MHZ
1011 #define IFXSCU_CFG_CPU0DIV_133MHZ (0)
1014 #ifndef IFXSCU_CFG_CPU0DIV_160MHZ
1016 #define IFXSCU_CFG_CPU0DIV_160MHZ (0)
1019 #ifndef IFXSCU_CFG_CPU0DIV_200MHZ
1021 #define IFXSCU_CFG_CPU0DIV_200MHZ (0)
1024 #ifndef IFXSCU_CFG_CPU0DIV_240MHZ
1026 #define IFXSCU_CFG_CPU0DIV_240MHZ (0)
1029 #ifndef IFXSCU_CFG_CPU0DIV_300MHZ
1031 #define IFXSCU_CFG_CPU0DIV_300MHZ (0)
1034 #ifndef IFXSCU_CFG_CPU1DIV_80MHZ
1036 #define IFXSCU_CFG_CPU1DIV_80MHZ (0)
1039 #ifndef IFXSCU_CFG_CPU1DIV_133MHZ
1041 #define IFXSCU_CFG_CPU1DIV_133MHZ (0)
1044 #ifndef IFXSCU_CFG_CPU1DIV_160MHZ
1046 #define IFXSCU_CFG_CPU1DIV_160MHZ (0)
1049 #ifndef IFXSCU_CFG_CPU1DIV_200MHZ
1051 #define IFXSCU_CFG_CPU1DIV_200MHZ (0)
1054 #ifndef IFXSCU_CFG_CPU1DIV_240MHZ
1056 #define IFXSCU_CFG_CPU1DIV_240MHZ (0)
1059 #ifndef IFXSCU_CFG_CPU1DIV_300MHZ
1061 #define IFXSCU_CFG_CPU1DIV_300MHZ (0)
1064 #ifndef IFXSCU_CFG_CPU2DIV_80MHZ
1066 #define IFXSCU_CFG_CPU2DIV_80MHZ (0)
1069 #ifndef IFXSCU_CFG_CPU2DIV_133MHZ
1071 #define IFXSCU_CFG_CPU2DIV_133MHZ (0)
1074 #ifndef IFXSCU_CFG_CPU2DIV_160MHZ
1076 #define IFXSCU_CFG_CPU2DIV_160MHZ (0)
1079 #ifndef IFXSCU_CFG_CPU2DIV_200MHZ
1081 #define IFXSCU_CFG_CPU2DIV_200MHZ (0)
1084 #ifndef IFXSCU_CFG_CPU2DIV_240MHZ
1086 #define IFXSCU_CFG_CPU2DIV_240MHZ (0)
1089 #ifndef IFXSCU_CFG_CPU2DIV_300MHZ
1091 #define IFXSCU_CFG_CPU2DIV_300MHZ (0)
1100 #ifndef IFXSCU_CFG_FLASH_FCON_WSPFLASH_80MHZ
1102 #define IFXSCU_CFG_FLASH_FCON_WSPFLASH_80MHZ (3-1)
1105 #ifndef IFXSCU_CFG_FLASH_FCON_WSPFLASH_133MHZ
1107 #define IFXSCU_CFG_FLASH_FCON_WSPFLASH_133MHZ (4-1)
1110 #ifndef IFXSCU_CFG_FLASH_FCON_WSPFLASH_160MHZ
1112 #define IFXSCU_CFG_FLASH_FCON_WSPFLASH_160MHZ (5-1)
1115 #ifndef IFXSCU_CFG_FLASH_FCON_WSPFLASH_200MHZ
1117 #define IFXSCU_CFG_FLASH_FCON_WSPFLASH_200MHZ (6-1)
1120 #ifndef IFXSCU_CFG_FLASH_FCON_WSPFLASH_240MHZ
1122 #define IFXSCU_CFG_FLASH_FCON_WSPFLASH_240MHZ (8-1)
1125 #ifndef IFXSCU_CFG_FLASH_FCON_WSPFLASH_300MHZ
1127 #define IFXSCU_CFG_FLASH_FCON_WSPFLASH_300MHZ (9-1)
1131 #ifndef IFXSCU_CFG_FLASH_FCON_WSECPF_80MHZ
1133 #define IFXSCU_CFG_FLASH_FCON_WSECPF_80MHZ (1-1)
1136 #ifndef IFXSCU_CFG_FLASH_FCON_WSECPF_133MHZ
1138 #define IFXSCU_CFG_FLASH_FCON_WSECPF_133MHZ (2-1)
1141 #ifndef IFXSCU_CFG_FLASH_FCON_WSECPF_160MHZ
1143 #define IFXSCU_CFG_FLASH_FCON_WSECPF_160MHZ (2-1)
1146 #ifndef IFXSCU_CFG_FLASH_FCON_WSECPF_200MHZ
1148 #define IFXSCU_CFG_FLASH_FCON_WSECPF_200MHZ (2-1)
1151 #ifndef IFXSCU_CFG_FLASH_FCON_WSECPF_240MHZ
1153 #define IFXSCU_CFG_FLASH_FCON_WSECPF_240MHZ (3-1)
1156 #ifndef IFXSCU_CFG_FLASH_FCON_WSECPF_300MHZ
1158 #define IFXSCU_CFG_FLASH_FCON_WSECPF_300MHZ (3-1)
1162 #ifndef IFXSCU_CFG_FLASH_FCON_WSDFLASH_80MHZ
1164 #define IFXSCU_CFG_FLASH_FCON_WSDFLASH_80MHZ (16-1)
1167 #ifndef IFXSCU_CFG_FLASH_FCON_WSDFLASH_133MHZ
1169 #define IFXSCU_CFG_FLASH_FCON_WSDFLASH_133MHZ (14-1)
1172 #ifndef IFXSCU_CFG_FLASH_FCON_WSDFLASH_160MHZ
1174 #define IFXSCU_CFG_FLASH_FCON_WSDFLASH_160MHZ (16-1)
1177 #ifndef IFXSCU_CFG_FLASH_FCON_WSDFLASH_200MHZ
1179 #define IFXSCU_CFG_FLASH_FCON_WSDFLASH_200MHZ (20-1)
1182 #ifndef IFXSCU_CFG_FLASH_FCON_WSDFLASH_240MHZ
1184 #define IFXSCU_CFG_FLASH_FCON_WSDFLASH_240MHZ (16-1)
1187 #ifndef IFXSCU_CFG_FLASH_FCON_WSDFLASH_300MHZ
1189 #define IFXSCU_CFG_FLASH_FCON_WSDFLASH_300MHZ (20-1)
1193 #ifndef IFXSCU_CFG_FLASH_FCON_WSECDF_80MHZ
1195 #define IFXSCU_CFG_FLASH_FCON_WSECDF_80MHZ (2-1)
1198 #ifndef IFXSCU_CFG_FLASH_FCON_WSECDF_133MHZ
1200 #define IFXSCU_CFG_FLASH_FCON_WSECDF_133MHZ (2-1)
1203 #ifndef IFXSCU_CFG_FLASH_FCON_WSECDF_160MHZ
1205 #define IFXSCU_CFG_FLASH_FCON_WSECDF_160MHZ (2-1)
1208 #ifndef IFXSCU_CFG_FLASH_FCON_WSECDF_200MHZ
1210 #define IFXSCU_CFG_FLASH_FCON_WSECDF_200MHZ (2-1)
1213 #ifndef IFXSCU_CFG_FLASH_FCON_WSECDF_240MHZ
1215 #define IFXSCU_CFG_FLASH_FCON_WSECDF_240MHZ (2-1)
1218 #ifndef IFXSCU_CFG_FLASH_FCON_WSECDF_300MHZ
1220 #define IFXSCU_CFG_FLASH_FCON_WSECDF_300MHZ (2-1)
1224 #define IFXSCU_CFG_FLASH_WAITSTATE_MSK \
1226 (IFX_FLASH_FCON_WSPFLASH_MSK << IFX_FLASH_FCON_WSPFLASH_OFF) | \
1227 (IFX_FLASH_FCON_WSECPF_MSK << IFX_FLASH_FCON_WSECPF_OFF) | \
1228 (IFX_FLASH_FCON_WSDFLASH_MSK << IFX_FLASH_FCON_WSDFLASH_OFF) | \
1229 (IFX_FLASH_FCON_WSECDF_MSK << IFX_FLASH_FCON_WSECDF_OFF))
1231 #define IFXSCU_CFG_FLASH_WAITSTATE_VAL_BASIC_(pllFreq) \
1233 (IFXSCU_CFG_FLASH_FCON_WSPFLASH_##pllFreq << IFX_FLASH_FCON_WSPFLASH_OFF)| \
1234 (IFXSCU_CFG_FLASH_FCON_WSECPF_##pllFreq << IFX_FLASH_FCON_WSECPF_OFF) | \
1235 (IFXSCU_CFG_FLASH_FCON_WSDFLASH_##pllFreq << IFX_FLASH_FCON_WSDFLASH_OFF)| \
1236 (IFXSCU_CFG_FLASH_FCON_WSECDF_##pllFreq << IFX_FLASH_FCON_WSECDF_OFF))
1238 #define IFXSCU_CFG_FLASH_WAITSTATE_VAL_BASIC(pllFreq) IFXSCU_CFG_FLASH_WAITSTATE_VAL_BASIC_(pllFreq)
1240 #define IFXSCU_CFG_FLASH_WAITSTATE_VAL IFXSCU_CFG_FLASH_WAITSTATE_VAL_BASIC(IFXSCU_CFG_PLL_FREQ)
1244 #define IFXSCU_CFG_CCUCON0_MASK \
1246 (IFX_SCU_CCUCON0_BAUD1DIV_MSK << IFX_SCU_CCUCON0_BAUD1DIV_OFF) | \
1247 (IFX_SCU_CCUCON0_BAUD2DIV_MSK << IFX_SCU_CCUCON0_BAUD2DIV_OFF) | \
1248 (IFX_SCU_CCUCON0_SRIDIV_MSK << IFX_SCU_CCUCON0_SRIDIV_OFF) | \
1249 (IFX_SCU_CCUCON0_SPBDIV_MSK << IFX_SCU_CCUCON0_SPBDIV_OFF) | \
1250 (IFX_SCU_CCUCON0_FSI2DIV_MSK << IFX_SCU_CCUCON0_FSI2DIV_OFF) | \
1251 (IFX_SCU_CCUCON0_FSIDIV_MSK << IFX_SCU_CCUCON0_FSIDIV_OFF))
1253 #define IFXSCU_CFG_CCUCON0_BASIC_(pllFreq) \
1255 (IFXSCU_CFG_BAUD1DIV_##pllFreq << IFX_SCU_CCUCON0_BAUD1DIV_OFF) | \
1256 (IFXSCU_CFG_BAUD2DIV_##pllFreq << IFX_SCU_CCUCON0_BAUD2DIV_OFF) | \
1257 (IFXSCU_CFG_SRIDIV_##pllFreq << IFX_SCU_CCUCON0_SRIDIV_OFF) | \
1258 (IFXSCU_CFG_SPBDIV_##pllFreq << IFX_SCU_CCUCON0_SPBDIV_OFF) | \
1259 (IFXSCU_CFG_FSI2DIV_##pllFreq << IFX_SCU_CCUCON0_FSI2DIV_OFF) | \
1260 (IFXSCU_CFG_FSIDIV_##pllFreq << IFX_SCU_CCUCON0_FSIDIV_OFF))
1262 #define IFXSCU_CFG_CCUCON0_BASIC(pllFreq) IFXSCU_CFG_CCUCON0_BASIC_(pllFreq)
1264 #define IFXSCU_CFG_CCUCON0 IFXSCU_CFG_CCUCON0_BASIC(IFXSCU_CFG_PLL_FREQ)
1267 #define IFXSCU_CFG_CCUCON1_MASK \
1269 (IFX_SCU_CCUCON1_CANDIV_MSK << IFX_SCU_CCUCON1_CANDIV_OFF) | \
1270 (IFX_SCU_CCUCON1_ERAYDIV_MSK << IFX_SCU_CCUCON1_ERAYDIV_OFF) | \
1271 (IFX_SCU_CCUCON1_STMDIV_MSK << IFX_SCU_CCUCON1_STMDIV_OFF) | \
1272 (IFX_SCU_CCUCON1_GTMDIV_MSK << IFX_SCU_CCUCON1_GTMDIV_OFF) | \
1273 (IFX_SCU_CCUCON1_ETHDIV_MSK << IFX_SCU_CCUCON1_ETHDIV_OFF) | \
1274 (IFX_SCU_CCUCON1_ASCLINFDIV_MSK << IFX_SCU_CCUCON1_ASCLINFDIV_OFF) | \
1275 (IFX_SCU_CCUCON1_ASCLINSDIV_MSK << IFX_SCU_CCUCON1_ASCLINSDIV_OFF))
1277 #define IFXSCU_CFG_CCUCON1_BASIC_(pllFreq) \
1279 (IFXSCU_CFG_CANDIV_##pllFreq << IFX_SCU_CCUCON1_CANDIV_OFF) | \
1280 (IFXSCU_CFG_ERAYDIV_##pllFreq << IFX_SCU_CCUCON1_ERAYDIV_OFF) | \
1281 (IFXSCU_CFG_STMDIV_##pllFreq << IFX_SCU_CCUCON1_STMDIV_OFF) | \
1282 (IFXSCU_CFG_GTMDIV_##pllFreq << IFX_SCU_CCUCON1_GTMDIV_OFF) | \
1283 (IFXSCU_CFG_ETHDIV_##pllFreq << IFX_SCU_CCUCON1_ETHDIV_OFF) | \
1284 (IFXSCU_CFG_ASCLINFDIV_##pllFreq << IFX_SCU_CCUCON1_ASCLINFDIV_OFF) | \
1285 (IFXSCU_CFG_ASCLINSDIV_##pllFreq << IFX_SCU_CCUCON1_ASCLINSDIV_OFF))
1287 #define IFXSCU_CFG_CCUCON1_BASIC(pllFreq) IFXSCU_CFG_CCUCON1_BASIC_(pllFreq)
1289 #define IFXSCU_CFG_CCUCON1 IFXSCU_CFG_CCUCON1_BASIC(IFXSCU_CFG_PLL_FREQ)
1292 #define IFXSCU_CFG_CCUCON2_MASK \
1294 (IFX_SCU_CCUCON2_BBBDIV_MSK << IFX_SCU_CCUCON2_BBBDIV_OFF))
1296 #define IFXSCU_CFG_CCUCON2_BASIC_(pllFreq) \
1298 (IFXSCU_CFG_BBBDIV_##pllFreq << IFX_SCU_CCUCON2_BBBDIV_OFF))
1300 #define IFXSCU_CFG_CCUCON2_BASIC(pllFreq) IFXSCU_CFG_CCUCON2_BASIC_(pllFreq)
1302 #define IFXSCU_CFG_CCUCON2 IFXSCU_CFG_CCUCON2_BASIC(IFXSCU_CFG_PLL_FREQ)
1305 #define IFXSCU_CFG_CCUCON5_MASK \
1307 (IFX_SCU_CCUCON5_MAXDIV_MSK << IFX_SCU_CCUCON5_MAXDIV_OFF))
1309 #define IFXSCU_CFG_CCUCON5_BASIC_(pllFreq) \
1311 (IFXSCU_CFG_MAXDIV_##pllFreq << IFX_SCU_CCUCON5_MAXDIV_OFF))
1313 #define IFXSCU_CFG_CCUCON5_BASIC(pllFreq) IFXSCU_CFG_CCUCON5_BASIC_(pllFreq)
1315 #define IFXSCU_CFG_CCUCON5 IFXSCU_CFG_CCUCON5_BASIC(IFXSCU_CFG_PLL_FREQ)
1318 #define IFXSCU_CFG_CCUCON6_MASK \
1320 (IFX_SCU_CCUCON6_CPU0DIV_MSK << IFX_SCU_CCUCON6_CPU0DIV_OFF))
1322 #define IFXSCU_CFG_CCUCON6_BASIC_(pllFreq) \
1324 (IFXSCU_CFG_CPU0DIV_##pllFreq << IFX_SCU_CCUCON6_CPU0DIV_OFF))
1326 #define IFXSCU_CFG_CCUCON6_BASIC(pllFreq) IFXSCU_CFG_CCUCON6_BASIC_(pllFreq)
1328 #define IFXSCU_CFG_CCUCON6 IFXSCU_CFG_CCUCON6_BASIC(IFXSCU_CFG_PLL_FREQ)
1331 #define IFXSCU_CFG_CCUCON7_MASK \
1333 (IFX_SCU_CCUCON7_CPU1DIV_MSK << IFX_SCU_CCUCON7_CPU1DIV_OFF))
1335 #define IFXSCU_CFG_CCUCON7_BASIC_(pllFreq) \
1337 (IFXSCU_CFG_CPU1DIV_##pllFreq << IFX_SCU_CCUCON7_CPU1DIV_OFF))
1339 #define IFXSCU_CFG_CCUCON7_BASIC(pllFreq) IFXSCU_CFG_CCUCON7_BASIC_(pllFreq)
1341 #define IFXSCU_CFG_CCUCON7 IFXSCU_CFG_CCUCON7_BASIC(IFXSCU_CFG_PLL_FREQ)
1344 #define IFXSCU_CFG_CCUCON8_MASK \
1346 (IFX_SCU_CCUCON8_CPU2DIV_MSK << IFX_SCU_CCUCON8_CPU2DIV_OFF))
1348 #define IFXSCU_CFG_CCUCON8_BASIC_(pllFreq) \
1350 (IFXSCU_CFG_CPU2DIV_##pllFreq << IFX_SCU_CCUCON8_CPU2DIV_OFF))
1352 #define IFXSCU_CFG_CCUCON8_BASIC(pllFreq) IFXSCU_CFG_CCUCON8_BASIC_(pllFreq)
1354 #define IFXSCU_CFG_CCUCON8 IFXSCU_CFG_CCUCON8_BASIC(IFXSCU_CFG_PLL_FREQ)
1356 #define IFXSCU_CFG_CLK_DISTRIBUTION \
1359 {IFXSCU_CFG_CCUCON0, IFXSCU_CFG_CCUCON0_MASK}, \
1360 {IFXSCU_CFG_CCUCON1, IFXSCU_CFG_CCUCON1_MASK}, \
1361 {IFXSCU_CFG_CCUCON2, IFXSCU_CFG_CCUCON2_MASK}, \
1362 {IFXSCU_CFG_CCUCON5, IFXSCU_CFG_CCUCON5_MASK}, \
1363 {IFXSCU_CFG_CCUCON6, IFXSCU_CFG_CCUCON6_MASK}, \
1364 {IFXSCU_CFG_CCUCON7, IFXSCU_CFG_CCUCON7_MASK}, \
1365 {IFXSCU_CFG_CCUCON8, IFXSCU_CFG_CCUCON8_MASK} \
1370 #define IFXSCU_CFG_PLL_STEPS_BASIC_(xtalFreq, pllFreq) IFXSCU_CFG_PLL_STEPS_##xtalFreq##_##pllFreq
1371 #define IFXSCU_CFG_PLL_STEPS_BASIC(xtalFreq, pllFreq) IFXSCU_CFG_PLL_STEPS_BASIC_(xtalFreq, pllFreq)
1372 #define IFXSCU_CFG_PLL_STEPS IFXSCU_CFG_PLL_STEPS_BASIC(IFXSCU_CFG_XTAL_FREQ, IFXSCU_CFG_PLL_FREQ)
1375 #define IFXSCU_CFG_PLL_INITIAL_STEP_BASIC_(xtalFreq, pllFreq) IFXSCU_CFG_PLL_INITIAL_STEP_##xtalFreq##_##pllFreq
1376 #define IFXSCU_CFG_PLL_INITIAL_STEP_BASIC(xtalFreq, pllFreq) IFXSCU_CFG_PLL_INITIAL_STEP_BASIC_(xtalFreq, pllFreq)
1377 #define IFXSCU_CFG_PLL_INITIAL_STEP IFXSCU_CFG_PLL_INITIAL_STEP_BASIC(IFXSCU_CFG_XTAL_FREQ, IFXSCU_CFG_PLL_FREQ)
1379 #define IFXSCU_CFG_FLASH_WAITSTATE \
1381 {IFXSCU_CFG_FLASH_WAITSTATE_VAL, IFXSCU_CFG_FLASH_WAITSTATE_MSK}
1384 #if (IFX_CFG_SCU_XTAL_FREQUENCY == (20000000))
1385 #define IFXSCU_CFG_XTAL_FREQ 20MHZ
1386 #elif (IFX_CFG_SCU_XTAL_FREQUENCY == (40000000))
1387 #define IFXSCU_CFG_XTAL_FREQ 40MHZ
1388 #elif (IFX_CFG_SCU_XTAL_FREQUENCY == (16000000))
1389 #define IFXSCU_CFG_XTAL_FREQ 16MHZ
1390 #elif (IFX_CFG_SCU_XTAL_FREQUENCY == (8000000))
1391 #define IFXSCU_CFG_XTAL_FREQ 8MHZ
1393 #error "Wrong XTAL frequency configuration! check IFX_CFG_SCU_XTAL_FREQUENCY configuration in Ifx_Cfg.h."
1394 #error "Aurix Triboard supported crystal frequencies are 8MHz, 16MHz, 20MHz and 40MHz"
1397 #if (IFX_CFG_SCU_PLL_FREQUENCY == (80000000))
1398 #define IFXSCU_CFG_PLL_FREQ 80MHZ
1399 #elif (IFX_CFG_SCU_PLL_FREQUENCY == (133000000)) && (IFX_CFG_SCU_XTAL_FREQUENCY != (8000000))
1400 #define IFXSCU_CFG_PLL_FREQ 133MHZ
1401 #elif (IFX_CFG_SCU_PLL_FREQUENCY == (160000000))
1402 #define IFXSCU_CFG_PLL_FREQ 160MHZ
1403 #elif (IFX_CFG_SCU_PLL_FREQUENCY == (200000000))
1404 #define IFXSCU_CFG_PLL_FREQ 200MHZ
1406 #error "Wrong PLL frequency configuration!, check IFX_CFG_SCU_PLL_FREQUENCY configuration in Ifx_Cfg.h."
1407 #error "Supported PLL frequencies are 80MHz, 133MHz (8MHz XTAL doesn't support), 160Mhz, and 200MHz."