iLLD_TC27xC  1.0
IfxEth_Phy_Pef7071.c
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1 /**
2  * \file IfxEth_Phy_Pef7071.c
3  * \brief ETH PHY_PEF7071 details
4  *
5  * \version iLLD_0_1_0_10
6  * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
7  *
8  *
9  * IMPORTANT NOTICE
10  *
11  *
12  * Infineon Technologies AG (Infineon) is supplying this file for use
13  * exclusively with Infineon's microcontroller products. This file can be freely
14  * distributed within development tools that are supporting such microcontroller
15  * products.
16  *
17  * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
18  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
19  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
20  * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
21  * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
22  *
23  */
24 
25 /******************************************************************************/
26 /*----------------------------------Includes----------------------------------*/
27 /******************************************************************************/
28 
29 #include "IfxEth_Phy_Pef7071.h"
30 
31 /******************************************************************************/
32 /*----------------------------------Macros------------------------------------*/
33 /******************************************************************************/
34 
35 #define IFXETH_PHY_PEF7071_MDIO_CTRL 0x00
36 
37 #define IFXETH_PHY_PEF7071_MDIO_STAT 0x01
38 
39 #define IFXETH_PHY_PEF7071_MDIO_PHYID1 0x02
40 
41 #define IFXETH_PHY_PEF7071_MDIO_PHYID2 0x03
42 
43 #define IFXETH_PHY_PEF7071_MDIO_AN_ADV 0x04
44 
45 #define IFXETH_PHY_PEF7071_MDIO_AN_LPA 0x05
46 
47 #define IFXETH_PHY_PEF7071_MDIO_AN_EXP 0x06
48 
49 #define IFXETH_PHY_PEF7071_MDIO_AN_NPTX 0x07
50 
51 #define IFXETH_PHY_PEF7071_MDIO_AN_NPRX 0x08
52 
53 #define IFXETH_PHY_PEF7071_MDIO_GCTRL 0x09
54 
55 #define IFXETH_PHY_PEF7071_MDIO_GSTAT 0x0A
56 
57 #define IFXETH_PHY_PEF7071_MDIO_RES11 0x0B
58 
59 #define IFXETH_PHY_PEF7071_MDIO_RES12 0x0C
60 
61 #define IFXETH_PHY_PEF7071_MDIO_MMDCTRL 0x0D
62 
63 #define IFXETH_PHY_PEF7071_MDIO_MMDDATA 0x0E
64 
65 #define IFXETH_PHY_PEF7071_MDIO_XSTAT 0x0F
66 
67 #define IFXETH_PHY_PEF7071_MDIO_PHYPERF 0x10
68 
69 #define IFXETH_PHY_PEF7071_MDIO_PHYSTAT1 0x11
70 
71 #define IFXETH_PHY_PEF7071_MDIO_PHYSTAT2 0x12
72 
73 #define IFXETH_PHY_PEF7071_MDIO_PHYCTL1 0x13
74 
75 #define IFXETH_PHY_PEF7071_MDIO_PHYCTL2 0x14
76 
77 #define IFXETH_PHY_PEF7071_MDIO_ERRCNT 0x15
78 
79 #define IFXETH_PHY_PEF7071_MDIO_EECTRL 0x16
80 
81 #define IFXETH_PHY_PEF7071_MDIO_MIICTRL 0x17
82 
83 #define IFXETH_PHY_PEF7071_MDIO_MIISTAT 0x18
84 
85 #define IFXETH_PHY_PEF7071_MDIO_IMASK 0x19
86 
87 #define IFXETH_PHY_PEF7071_MDIO_ISTAT 0x1A
88 
89 #define IFXETH_PHY_PEF7071_MDIO_LED 0x1B
90 
91 #define IFXETH_PHY_PEF7071_MDIO_TPGCTRL 0x1C
92 
93 #define IFXETH_PHY_PEF7071_MDIO_TPGDATA 0x1D
94 
95 #define IFXETH_PHY_PEF7071_MDIO_FWV 0x1E
96 
97 #define IFXETH_PHY_PEF7071_MDIO_RES1F 0x1F
98 
99 #define IFXETH_PHY_PEF7071_WAIT_GMII_READY() while (ETH_GMII_ADDRESS.B.GB) {}
100 
101 /** \addtogroup IfxLld_Eth_Phy_Pef7071_Functions
102  * \{ */
103 
104 /******************************************************************************/
105 /*-----------------------Private Function Prototypes--------------------------*/
106 /******************************************************************************/
107 
108 /**
109  * \return None
110  */
111 static void IfxEth_Phy_Pef7071_read_mdio_reg(uint32 layeraddr, uint32 regaddr, uint32 *pdata);
112 
113 /**
114  * \return None
115  */
116 static void IfxEth_Phy_Pef7071_write_mdio_reg(uint32 layeraddr, uint32 regaddr, uint32 data);
117 
118 /** \} */
119 
120 /******************************************************************************/
121 /*-----------------------Exported Variables/Constants-------------------------*/
122 /******************************************************************************/
123 
125 
126 /******************************************************************************/
127 /*-------------------------Function Implementations---------------------------*/
128 /******************************************************************************/
129 
131 {
133 
134  /* // read once all PHY registers
135  * int i;
136  * for(i = 0; i < 31; i++)
137  * {
138  * uint32 value;
139  * read_mdio_reg(0, i, &value);
140  * } */
141 
142  // reset PHY
143  IfxEth_Phy_Pef7071_write_mdio_reg(0, IFXETH_PHY_PEF7071_MDIO_CTRL, 0x8000); // reset
144  uint32 value;
145 
146  do
147  {
148  IfxEth_Phy_Pef7071_read_mdio_reg(0, IFXETH_PHY_PEF7071_MDIO_CTRL, &value);
149  } while (value & 0x8000); // wait for reset to finish
150 
151  // setup PHY
152  IfxEth_Phy_Pef7071_write_mdio_reg(0, IFXETH_PHY_PEF7071_MDIO_MIICTRL, 0xF702); // skew adaptation is needed, RMII mode (10/100MBit)
153  IfxEth_Phy_Pef7071_write_mdio_reg(0, IFXETH_PHY_PEF7071_MDIO_GCTRL, 0x0000); // advertise no 1000BASE-T (full/half duplex)
154  IfxEth_Phy_Pef7071_write_mdio_reg(0, IFXETH_PHY_PEF7071_MDIO_AN_ADV, 0x0101); // advertise 100BASE-TX full duplex only
155  IfxEth_Phy_Pef7071_write_mdio_reg(0, IFXETH_PHY_PEF7071_MDIO_CTRL, 0x1200); // enable auto-negotiation, restart auto-negotiation
156 
157  // we set our loop mode (RJ45) in side the PHY (PHYCTL1 register) if we will have a loop
158  // if (CONFIG_ETH._loop)
159  // write_mdio_reg (0, 0x13, (0x4 << 13) | 0x1);
160 
161  // done
163 
164  return 1;
165 }
166 
167 
169 {
170  boolean linkEstablished = FALSE;
171 
173  {
174  uint32 value;
175  IfxEth_Phy_Pef7071_read_mdio_reg(0, IFXETH_PHY_PEF7071_MDIO_STAT, &value);
176  linkEstablished = ((value & (1 << 2)) != 0) ? TRUE : FALSE;
177  }
178 
179  return linkEstablished;
180 }
181 
182 
183 static void IfxEth_Phy_Pef7071_read_mdio_reg(uint32 layeraddr, uint32 regaddr, uint32 *pdata)
184 {
185  // 5bit Physical Layer Adddress, 5bit GMII Regnr, 4bit csrclock divider, Read, Busy
186  ETH_GMII_ADDRESS.U = (layeraddr << 11) | (regaddr << 6) | (0 << 2) | (0 << 1) | (1 << 0);
187 
189 
190  // get data
191  *pdata = ETH_GMII_DATA.U;
192 }
193 
194 
195 static void IfxEth_Phy_Pef7071_write_mdio_reg(uint32 layeraddr, uint32 regaddr, uint32 data)
196 {
197  // put data
198  ETH_GMII_DATA.U = data;
199 
200  // 5bit Physical Layer Adddress, 5bit GMII Regnr, 4bit csrclock divider, Write, Busy
201  ETH_GMII_ADDRESS.U = (layeraddr << 11) | (regaddr << 6) | (0 << 2) | (1 << 1) | (1 << 0);
202 
204 }