iLLD_TC27xC  1.0
IfxDma.h
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1 /**
2  * \file IfxDma.h
3  * \brief DMA basic functionality
4  * \ingroup IfxLld_Dma
5  *
6  * \version iLLD_0_1_0_10
7  * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
8  *
9  *
10  * IMPORTANT NOTICE
11  *
12  *
13  * Infineon Technologies AG (Infineon) is supplying this file for use
14  * exclusively with Infineon's microcontroller products. This file can be freely
15  * distributed within development tools that are supporting such microcontroller
16  * products.
17  *
18  * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
19  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
20  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
21  * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
22  * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
23  *
24  * \defgroup IfxLld_Dma DMA
25  * \ingroup IfxLld
26  * \defgroup IfxLld_Dma_Std Standard Driver
27  * \ingroup IfxLld_Dma
28  * \defgroup IfxLld_Dma_Std_Enum Enumerations
29  * \ingroup IfxLld_Dma_Std
30  * \defgroup IfxLld_Dma_Std_Reset Reset Functions
31  * \ingroup IfxLld_Dma_Std
32  * \defgroup IfxLld_Dma_Std_Channel_Transaction Channel Transaction Functions
33  * \ingroup IfxLld_Dma_Std
34  * \defgroup IfxLld_Dma_Std_Move_Engine Move Engine functions
35  * \ingroup IfxLld_Dma_Std
36  * \defgroup IfxLld_Dma_Std_Channel_Configure Channel configuration Functions
37  * \ingroup IfxLld_Dma_Std
38  * \defgroup IfxLld_Dma_Std_Channel_Halt Channel Halt Functions
39  * \ingroup IfxLld_Dma_Std
40  * \defgroup IfxLld_Dma_Std_Double_Buffer Double Buffer functions
41  * \ingroup IfxLld_Dma_Std
42  * \defgroup IfxLld_Dma_Std_Interrupts Interrupt functions
43  * \ingroup IfxLld_Dma_Std
44  */
45 
46 #ifndef IFXDMA_H
47 #define IFXDMA_H 1
48 
49 /******************************************************************************/
50 /*----------------------------------Includes----------------------------------*/
51 /******************************************************************************/
52 
53 #include "_Impl/IfxDma_cfg.h"
54 #include "IfxDma_bf.h"
55 
56 /******************************************************************************/
57 /*--------------------------------Enumerations--------------------------------*/
58 /******************************************************************************/
59 
60 /** \addtogroup IfxLld_Dma_Std_Enum
61  * \{ */
62 /** \brief Bus Master Mode definition
63  * Definition in Ifx_DMA.MODE[4].B.MODE
64  */
65 typedef enum
66 {
67  IfxDma_BusMasterMode_user = 0, /**< \brief Selected hardware resource performs Bus access in user mode */
68  IfxDma_BusMasterMode_supervisor = 1 /**< \brief Selected hardware resource performs Bus access in supervisor mode */
70 
71 /** \brief Channel Bus Priority definition
72  */
73 typedef enum
74 {
75  IfxDma_ChannelBusPriority_low = 0, /**< \brief low priority */
76  IfxDma_ChannelBusPriority_medium = 1, /**< \brief medium priority */
77  IfxDma_ChannelBusPriority_high = 2 /**< \brief high priority */
79 
80 /** \brief DMA channel resources definition
81  */
82 typedef enum
83 {
84  IfxDma_ChannelId_none = -1, /**< \brief None of the Ifx_DMA Channels */
85  IfxDma_ChannelId_0 = 0, /**< \brief Ifx_DMA Channel 0 */
86  IfxDma_ChannelId_1, /**< \brief Ifx_DMA Channel 1 */
87  IfxDma_ChannelId_2, /**< \brief Ifx_DMA Channel 2 */
88  IfxDma_ChannelId_3, /**< \brief Ifx_DMA Channel 3 */
89  IfxDma_ChannelId_4, /**< \brief Ifx_DMA Channel 4 */
90  IfxDma_ChannelId_5, /**< \brief Ifx_DMA Channel 5 */
91  IfxDma_ChannelId_6, /**< \brief Ifx_DMA Channel 6 */
92  IfxDma_ChannelId_7, /**< \brief Ifx_DMA Channel 7 */
93  IfxDma_ChannelId_8, /**< \brief Ifx_DMA Channel 8 */
94  IfxDma_ChannelId_9, /**< \brief Ifx_DMA Channel 9 */
95  IfxDma_ChannelId_10, /**< \brief Ifx_DMA Channel 10 */
96  IfxDma_ChannelId_11, /**< \brief Ifx_DMA Channel 11 */
97  IfxDma_ChannelId_12, /**< \brief Ifx_DMA Channel 12 */
98  IfxDma_ChannelId_13, /**< \brief Ifx_DMA Channel 13 */
99  IfxDma_ChannelId_14, /**< \brief Ifx_DMA Channel 14 */
100  IfxDma_ChannelId_15, /**< \brief Ifx_DMA Channel 15 */
101  IfxDma_ChannelId_16, /**< \brief Ifx_DMA Channel 16 */
102  IfxDma_ChannelId_17, /**< \brief Ifx_DMA Channel 17 */
103  IfxDma_ChannelId_18, /**< \brief Ifx_DMA Channel 18 */
104  IfxDma_ChannelId_19, /**< \brief Ifx_DMA Channel 19 */
105  IfxDma_ChannelId_20, /**< \brief Ifx_DMA Channel 20 */
106  IfxDma_ChannelId_21, /**< \brief Ifx_DMA Channel 21 */
107  IfxDma_ChannelId_22, /**< \brief Ifx_DMA Channel 22 */
108  IfxDma_ChannelId_23, /**< \brief Ifx_DMA Channel 23 */
109  IfxDma_ChannelId_24, /**< \brief Ifx_DMA Channel 24 */
110  IfxDma_ChannelId_25, /**< \brief Ifx_DMA Channel 25 */
111  IfxDma_ChannelId_26, /**< \brief Ifx_DMA Channel 26 */
112  IfxDma_ChannelId_27, /**< \brief Ifx_DMA Channel 27 */
113  IfxDma_ChannelId_28, /**< \brief Ifx_DMA Channel 28 */
114  IfxDma_ChannelId_29, /**< \brief Ifx_DMA Channel 29 */
115  IfxDma_ChannelId_30, /**< \brief Ifx_DMA Channel 30 */
116  IfxDma_ChannelId_31, /**< \brief Ifx_DMA Channel 31 */
117  IfxDma_ChannelId_32, /**< \brief Ifx_DMA Channel 32 */
118  IfxDma_ChannelId_33, /**< \brief Ifx_DMA Channel 33 */
119  IfxDma_ChannelId_34, /**< \brief Ifx_DMA Channel 34 */
120  IfxDma_ChannelId_35, /**< \brief Ifx_DMA Channel 35 */
121  IfxDma_ChannelId_36, /**< \brief Ifx_DMA Channel 36 */
122  IfxDma_ChannelId_37, /**< \brief Ifx_DMA Channel 37 */
123  IfxDma_ChannelId_38, /**< \brief Ifx_DMA Channel 38 */
124  IfxDma_ChannelId_39, /**< \brief Ifx_DMA Channel 39 */
125  IfxDma_ChannelId_40, /**< \brief Ifx_DMA Channel 40 */
126  IfxDma_ChannelId_41, /**< \brief Ifx_DMA Channel 41 */
127  IfxDma_ChannelId_42, /**< \brief Ifx_DMA Channel 42 */
128  IfxDma_ChannelId_43, /**< \brief Ifx_DMA Channel 43 */
129  IfxDma_ChannelId_44, /**< \brief Ifx_DMA Channel 44 */
130  IfxDma_ChannelId_45, /**< \brief Ifx_DMA Channel 45 */
131  IfxDma_ChannelId_46, /**< \brief Ifx_DMA Channel 46 */
132  IfxDma_ChannelId_47, /**< \brief Ifx_DMA Channel 47 */
133  IfxDma_ChannelId_48, /**< \brief Ifx_DMA Channel 48 */
134  IfxDma_ChannelId_49, /**< \brief Ifx_DMA Channel 49 */
135  IfxDma_ChannelId_50, /**< \brief Ifx_DMA Channel 50 */
136  IfxDma_ChannelId_51, /**< \brief Ifx_DMA Channel 51 */
137  IfxDma_ChannelId_52, /**< \brief Ifx_DMA Channel 52 */
138  IfxDma_ChannelId_53, /**< \brief Ifx_DMA Channel 53 */
139  IfxDma_ChannelId_54, /**< \brief Ifx_DMA Channel 54 */
140  IfxDma_ChannelId_55, /**< \brief Ifx_DMA Channel 55 */
141  IfxDma_ChannelId_56, /**< \brief Ifx_DMA Channel 56 */
142  IfxDma_ChannelId_57, /**< \brief Ifx_DMA Channel 57 */
143  IfxDma_ChannelId_58, /**< \brief Ifx_DMA Channel 58 */
144  IfxDma_ChannelId_59, /**< \brief Ifx_DMA Channel 59 */
145  IfxDma_ChannelId_60, /**< \brief Ifx_DMA Channel 60 */
146  IfxDma_ChannelId_61, /**< \brief Ifx_DMA Channel 61 */
147  IfxDma_ChannelId_62, /**< \brief Ifx_DMA Channel 62 */
148  IfxDma_ChannelId_63, /**< \brief Ifx_DMA Channel 63 */
150 
151 /** \brief DMA circular buffer (wrap around) definition
152  * Definition in Ifx_DMA.CH[64].ADICR.B.CBLS
153  */
154 typedef enum
155 {
156  IfxDma_ChannelIncrementCircular_none = -1, /**< \brief no circular buffer operation */
157  IfxDma_ChannelIncrementCircular_1 = 0, /**< \brief circular buffer size is 1 byte */
158  IfxDma_ChannelIncrementCircular_2 = 1, /**< \brief circular buffer size is 2 byte */
159  IfxDma_ChannelIncrementCircular_4 = 2, /**< \brief circular buffer size is 4 byte */
160  IfxDma_ChannelIncrementCircular_8 = 3, /**< \brief circular buffer size is 8 byte */
161  IfxDma_ChannelIncrementCircular_16 = 4, /**< \brief circular buffer size is 16 byte */
162  IfxDma_ChannelIncrementCircular_32 = 5, /**< \brief circular buffer size is 32 byte */
163  IfxDma_ChannelIncrementCircular_64 = 6, /**< \brief circular buffer size is 64 byte */
164  IfxDma_ChannelIncrementCircular_128 = 7, /**< \brief circular buffer size is 128 byte */
165  IfxDma_ChannelIncrementCircular_256 = 8, /**< \brief circular buffer size is 256 byte */
166  IfxDma_ChannelIncrementCircular_512 = 9, /**< \brief circular buffer size is 512 byte */
167  IfxDma_ChannelIncrementCircular_1024 = 10, /**< \brief circular buffer size is 1024 byte */
168  IfxDma_ChannelIncrementCircular_2048 = 11, /**< \brief circular buffer size is 2048 byte */
169  IfxDma_ChannelIncrementCircular_4096 = 12, /**< \brief circular buffer size is 4096 byte */
170  IfxDma_ChannelIncrementCircular_8192 = 13, /**< \brief circular buffer size is 8192 byte */
171  IfxDma_ChannelIncrementCircular_16384 = 14, /**< \brief circular buffer size is 16384 byte */
172  IfxDma_ChannelIncrementCircular_32768 = 15 /**< \brief circular buffer size is 32768 byte */
174 
175 /** \brief DMA incrementation direction definition
176  * Definition in Ifx_DMA.CH[64].ADICR.B.INCS
177  */
178 typedef enum
179 {
180  IfxDma_ChannelIncrementDirection_negative = 0, /**< \brief pointer is decremented */
181  IfxDma_ChannelIncrementDirection_positive = 1 /**< \brief pointer is incremented */
183 
184 /** \brief DMA incrementation definition
185  * Definition in Ifx_DMA.CH[64].ADICR.B.SMF
186  */
187 typedef enum
188 {
189  IfxDma_ChannelIncrementStep_1 = 0, /**< \brief increment by 1 width */
190  IfxDma_ChannelIncrementStep_2 = 1, /**< \brief increment by 2 width */
191  IfxDma_ChannelIncrementStep_4 = 2, /**< \brief increment by 4 width */
192  IfxDma_ChannelIncrementStep_8 = 3, /**< \brief increment by 8 width */
193  IfxDma_ChannelIncrementStep_16 = 4, /**< \brief increment by 16 width */
194  IfxDma_ChannelIncrementStep_32 = 5, /**< \brief increment by 32 width */
195  IfxDma_ChannelIncrementStep_64 = 6, /**< \brief increment by 64 width */
196  IfxDma_ChannelIncrementStep_128 = 7 /**< \brief increment by 128 width */
198 
199 /** \brief Channel Transfer Interrupt generation mechanism.
200  * Definition in Ifx_DMA.CH[64].ADICR.B.INTCT (bit 0)
201  */
202 typedef enum
203 {
204  IfxDma_ChannelInterruptControl_thresholdLimitMatch = 0, /**< \brief interrupt when transfer count (TCOUNT) equals the threshold limit (IRDV) */
205  IfxDma_ChannelInterruptControl_transferCountDecremented = 1 /**< \brief interrupt when transfer count (TCOUNT) is decremented */
207 
208 /** \brief DMA transfer definition
209  * Definition in Ifx_DMA.BLK0.ME.CHCR.B.BLKM and Ifx_DMA.BLK1.ME.CHCR.B.BLKM
210  */
211 typedef enum
212 {
213  IfxDma_ChannelMove_1 = 0, /**< \brief 1 DMA move per DMA transfer */
214  IfxDma_ChannelMove_2 = 1, /**< \brief 2 DMA move per DMA transfer */
215  IfxDma_ChannelMove_4 = 2, /**< \brief 4 DMA move per DMA transfer */
216  IfxDma_ChannelMove_8 = 3, /**< \brief 8 DMA move per DMA transfer */
217  IfxDma_ChannelMove_16 = 4, /**< \brief 16 DMA move per DMA transfer */
218  IfxDma_ChannelMove_3 = 5, /**< \brief 3 DMA move per DMA transfer */
219  IfxDma_ChannelMove_5 = 6, /**< \brief 5 DMA move per DMA transfer */
220  IfxDma_ChannelMove_9 = 7 /**< \brief 9 DMA move per DMA transfer */
222 
223 /** \brief DMA move size definition
224  * Definition in Ifx_DMA.BLK0.ME.CHCR.B.CHDW and Ifx_DMA.BLK1.ME.CHCR.B.CHDW
225  */
226 typedef enum
227 {
228  IfxDma_ChannelMoveSize_8bit = 0, /**< \brief 1 DMA move is 8 bit wide */
229  IfxDma_ChannelMoveSize_16bit = 1, /**< \brief 1 DMA move is 16 bit wide */
230  IfxDma_ChannelMoveSize_32bit = 2, /**< \brief 1 DMA move is 32 bit wide */
231  IfxDma_ChannelMoveSize_64bit = 3, /**< \brief 1 DMA move is 64 bit wide */
232  IfxDma_ChannelMoveSize_128bit = 4, /**< \brief 1 DMA move is 128 bit wide */
233  IfxDma_ChannelMoveSize_256bit = 5 /**< \brief 1 DMA move is 256 bit wide */
235 
236 /** \brief DMA operation mode
237  * Definition in Ifx_DMA.BLK0.ME.CHCR.B.CHMODE and Ifx_DMA.BLK1.ME.CHCR.B.CHMODE
238  */
239 typedef enum
240 {
241  IfxDma_ChannelOperationMode_single = 0, /**< \brief channel disabled after transaction */
242  IfxDma_ChannelOperationMode_continuous = 1 /**< \brief channel stays enabled after transaction */
244 
245 /** \brief Pattern detection selection
246  * Definition in Ifx_DMA.BLK0.ME.CHCR.B.PATSEL and Ifx_DMA.BLK1.ME.CHCR.B.PATSEL
247  */
248 typedef enum
249 {
250  IfxDma_ChannelPattern_0_disable = 0, /**< \brief Pattern detect 0 disabled */
251  IfxDma_ChannelPattern_0_mode1 = 1, /**< \brief Compare match configuration 1 : pattern compare of MExR.RD[0] to PAT0[0] masked by PAT0[2] */
252  IfxDma_ChannelPattern_0_mode2 = 2, /**< \brief Compare match configuration 2 : pattern compare of MExR.RD[0] to PAT0[1] masked by PAT0[3] */
253  IfxDma_ChannelPattern_0_mode3 = 3, /**< \brief Compare match configuration 3 : pattern compare of MExR.RD[0] to PAT0[0] masked by PAT0[2] of actual DMA read move and pattern compare of MExR.RD[0] to PAT0[1] masked by PAT0[3] of previous DMA read move */
254  IfxDma_ChannelPattern_1_disable = 4, /**< \brief Pattern detect 1 disabled */
255  IfxDma_ChannelPattern_1_mode1 = 5, /**< \brief Compare match configuration 1 : pattern compare of MExR.RD[0] to PAT1[0] masked by PAT1[2] */
256  IfxDma_ChannelPattern_1_mode2 = 6, /**< \brief Compare match configuration 2 : pattern compare of MExR.RD[0] to PAT1[1] masked by PAT1[3] */
257  IfxDma_ChannelPattern_1_mode3 = 7 /**< \brief Compare match configuration 3 : pattern compare of MExR.RD[0] to PAT1[0] masked by PAT1[2] of actual DMA read move and pattern compare of MExR.RD[0] to PAT1[1] masked by PAT1[3] of previous DMA read move */
259 
260 /** \brief Channel Priority definition
261  */
262 typedef enum
263 {
264  IfxDma_ChannelPriority_low = 0, /**< \brief low priority */
265  IfxDma_ChannelPriority_medium = 1, /**< \brief medium priority */
266  IfxDma_ChannelPriority_high = 2 /**< \brief high priority */
268 
269 /** \brief DMA request mode
270  * Definition in Ifx_DMA.BLK0.ME.CHCR.B.RROAT and Ifx_DMA.BLK1.ME.CHCR.B.RROAT
271  */
272 typedef enum
273 {
274  IfxDma_ChannelRequestMode_oneTransferPerRequest = 0, /**< \brief a request initiates a single transfer */
275  IfxDma_ChannelRequestMode_completeTransactionPerRequest = 1 /**< \brief a request initiates a complete transaction */
277 
278 /** \brief DMA request selection
279  * Definition in Ifx_DMA.BLK0.ME.CHCR.B.PRSEL and Ifx_DMA.BLK1.ME.CHCR.B.PRSEL
280  */
281 typedef enum
282 {
283  IfxDma_ChannelRequestSource_peripheral = 0, /**< \brief Transfer Request via Hardware Trigger */
284  IfxDma_ChannelRequestSource_daisyChain = 1 /**< \brief Transfer Request via next (higher priority) channel */
286 
287 /** \brief shadow definition definition
288  * Definition in Ifx_DMA.CH[64].ADICR.B.SHCT
289  */
290 typedef enum
291 {
292  IfxDma_ChannelShadow_none = 0, /**< \brief shadow address register not used. Source and destination address register are written directly */
293  IfxDma_ChannelShadow_src = 1, /**< \brief Shadow address register used for source address buffering. When writing to SADRmx, the address is buffered in SHADRmx and transferred to SADRmx with the start of the next DMA transaction */
294  IfxDma_ChannelShadow_dst = 2, /**< \brief Shadow address register used for destination address buffering. When writing to DADRmx, the address is buffered in SHADRmx and transferred to DADRmx with the start of the next DMA transaction */
295  IfxDma_ChannelShadow_srcDirectWrite = 5, /**< \brief Shadow address used for source buffering. When writing to SADRz, the address is buffered in SHADRz and transferred to SADRz with the start of the next DMA transaction */
296  IfxDma_ChannelShadow_dstDirectWrite = 6, /**< \brief Shadow address used for destination buffering. When writing to DADRz, the address is buffered in SHADRz and transferred to DADRz with the start of the next DMA transaction */
297  IfxDma_ChannelShadow_doubleSourceBufferingSwSwitch = 8, /**< \brief Software switch only. Shadow address used for double buffering */
298  IfxDma_ChannelShadow_doubleSourceBufferingHwSwSwitch = 9, /**< \brief Automatic Hardware and Software switch. Shadow address used for double buffering */
299  IfxDma_ChannelShadow_doubleDestinationBufferingSwSwitch = 10, /**< \brief Software switch only. Shadow address used for double buffering */
300  IfxDma_ChannelShadow_doubleDestinationBufferingHwSwSwitch = 11, /**< \brief Automatic Hardware and Software switch. Shadow address used for double buffering */
301  IfxDma_ChannelShadow_linkedList = 12, /**< \brief The DMA controller reads a DMA channel transaction control set and overwrites 8 X words in the corresponding DMARAM channel z */
302  IfxDma_ChannelShadow_accumulatedLinkedList = 13, /**< \brief The DMA controller reads a DMA channel transaction control set and overwrites 6 X words in the corresponding DMARAM channel z */
303  IfxDma_ChannelShadow_safeLinkedList = 14, /**< \brief The DMA controller reads a DMA channel transaction control set. The Linked List only proceeds with the next DMA transaction if the existing SDCRC checksum matches the expected SDCRC checksum in the loaded from the new DMA transaction control set */
304  IfxDma_ChannelShadow_conditionalLinkedList = 15 /**< \brief Shadow address register (MExSHADR) and source and destination address CRC register (MExSDCRC) are used as address pointers to a Linked List. The selection of the address pointer is determined by DMA channel pattern detection conditions */
306 
307 typedef enum
308 {
309  IfxDma_HardwareResourcePartition_0 = 0, /**< \brief "Set of DMA channels are associated with hardware resource partition " + str(x) */
310  IfxDma_HardwareResourcePartition_1, /**< \brief "Set of DMA channels are associated with hardware resource partition " + str(x) */
311  IfxDma_HardwareResourcePartition_2, /**< \brief "Set of DMA channels are associated with hardware resource partition " + str(x) */
312  IfxDma_HardwareResourcePartition_3, /**< \brief "Set of DMA channels are associated with hardware resource partition " + str(x) */
314 
315 /** \brief DMA move engine definition
316  */
317 typedef enum
318 {
319  IfxDma_MoveEngine_0 = 0, /**< \brief first move engine */
320  IfxDma_MoveEngine_1 = 1 /**< \brief second move engine */
322 
323 /** \} */
324 
325 /** \addtogroup IfxLld_Dma_Std_Reset
326  * \{ */
327 
328 /******************************************************************************/
329 /*-------------------------Inline Function Prototypes-------------------------*/
330 /******************************************************************************/
331 
332 /** \brief Return the status of a DMA channel (reset / not reset)
333  * \param dma pointer to DMA module
334  * \param channelId DMA channel number
335  * \return TRUE if the channel is reset
336  * FALSE if the channel is not reset
337  *
338  * \code
339  * // check whether the channel is reset or not and also the hardware trigger disabled
340  *
341  * if (IfxDma_isChannelReset(chn[0].dma, chn[0].channelId) &&
342  * (!IfxDma_isChannelTransactionEnabled(chn[0].dma, chn[0].channelId))) {
343  * // Dma is out of RESET and there is no hardware request enabled
344  * IfxDma_Dma_startChannelTransaction(&chn[0]);
345  * }
346  * \endcode
347  *
348  */
349 IFX_INLINE boolean IfxDma_isChannelReset(Ifx_DMA *dma, IfxDma_ChannelId channelId);
350 
351 /** \brief Reset the channel
352  * \param dma pointer to DMA module
353  * \param channelId DMA channel number
354  * \return None
355  *
356  * \code
357  * // Apply reset to the channel
358  * IfxDma_resetChannel(chn[0].dma, chn[0].channelId);
359  * \endcode
360  *
361  */
362 IFX_INLINE void IfxDma_resetChannel(Ifx_DMA *dma, IfxDma_ChannelId channelId);
363 
364 /** \} */
365 
366 /** \addtogroup IfxLld_Dma_Std_Channel_Transaction
367  * \{ */
368 
369 /******************************************************************************/
370 /*-------------------------Inline Function Prototypes-------------------------*/
371 /******************************************************************************/
372 
373 /** \brief Clear the channel transaction request lost flag status
374  * \param dma pointer to DMA module
375  * \param channelId DMA channel number
376  * \return None
377  *
378  * \code
379  * // Clear the channel transaction request lost flag status
380  * IfxDma_clearChannelTransactionRequestLost(chn[0].dma, chn[0].channelId);
381  * \endcode
382  *
383  */
385 
386 /** \brief Disable a DMA channel hardware transaction request
387  * \param dma pointer to DMA module
388  * \param channelId DMA channel number
389  * \return None
390  *
391  * A coding example can be found in \ref IfxDma_enableChannelTransaction
392  *
393  */
394 IFX_INLINE void IfxDma_disableChannelTransaction(Ifx_DMA *dma, IfxDma_ChannelId channelId);
395 
396 /** \brief Disable the generation of a channel transaction lost error interrupt
397  * \param dma pointer to DMA module
398  * \param channelId DMA channel number
399  * \return None
400  *
401  * \code
402  * // Disable the transaction request lost interrupt for given channel
403  * IfxDma_disableChannelTransactionLostError(chn[0].dma, chn[0].channelId);
404  * \endcode
405  *
406  */
408 
409 /** \brief Enable a DMA channel hardware transaction request
410  * \param dma pointer to DMA module
411  * \param channelId DMA channel number
412  * \return None
413  *
414  * \code
415  * unsigned *src = (unsigned *)((unsigned)&SRC_DMACH0.U + 4*NUM_CHANNELS);
416  * for(int chn=0; chn<NUM_CHANNELS; ++chn, ++src) {
417  * IfxSrc_setRequest(src);
418  * }
419  *
420  * // Do not restrict the hardware triggering to only one transaction
421  *
422  * IfxDma_setChannelContinuousMode(chn[0].dma, chn[0].channelId);
423  * IfxDma_setChannelContinuousMode(chn[1].dma, chn[1].channelId);
424  * IfxDma_setChannelContinuousMode(chn[2].dma, chn[2].channelId);
425  *
426  * // Check for end of transaction
427  *
428  * while(!(IfxDma_getAndClearChannelInterrupt(chn[0].dma, chn[0].channelId)));
429  *
430  * // Enable the hardware trigger for channel 3
431  * IfxDma_enableChannelTransaction(chn[3].dma, chn[3].channelId);
432  *
433  * // Disable the hardware trigger for channel 2
434  * IfxDma_disableChannelTransaction(chn[2].dma, chn[2].channelId);
435  * // Hardware triggers for second time
436  *
437  * unsigned *SRc = (unsigned *)((unsigned)&SRC_DMACH0.U + 4*NUM_CHANNELS);
438  * for(int chn=0; chn<NUM_CHANNELS; ++chn, ++src) {
439  * IfxSrc_setRequest(src);
440  * }
441  *
442  * // Restrict the hardware triggering to only one transaction
443  * IfxDma_setChannelSingleMode(chn[0].dma, chn[0].channelId);
444  * IfxDma_setChannelSingleMode(chn[1].dma, chn[1].channelId);
445  * \endcode
446  *
447  */
448 IFX_INLINE void IfxDma_enableChannelTransaction(Ifx_DMA *dma, IfxDma_ChannelId channelId);
449 
450 /** \brief Enable the generation of a channel transaction lost error interrupt
451  * \param dma pointer to DMA module
452  * \param channelId DMA channel number
453  * \return None
454  *
455  * \code
456  * // Enable the transaction request lost interrupt for given channel
457  * IfxDma_enableChannelTransactionLostError(chn[0].dma, chn[0].channelId);
458  * \endcode
459  *
460  */
462 
463 /** \brief Check the channel transaction request lost flag status
464  * \param dma pointer to DMA module
465  * \param channelId DMA channel number
466  * \return TRUE if the TRL is set
467  * FALSE if the TRL is not set
468  *
469  * \code
470  * boolean trlFlag;
471  *
472  * // Check whether the channel transaction request lost flag is set or not
473  * trlFlag = IfxDma_getChannelTransactionRequestLost(chn[0].dma, chn[0].channelId));
474  * \endcode
475  *
476  */
478 
479 /** \brief Return the hardware transaction request status of a DMA channel
480  * \param dma pointer to DMA module
481  * \param channelId DMA channel number
482  * \return TRUE if the hardware transaction request is enabled
483  * FALSE if the hardware transaction request is disabled
484  *
485  * A coding example can be found in \ref IfxDma_isChannelReset
486  *
487  */
488 IFX_INLINE boolean IfxDma_isChannelTransactionEnabled(Ifx_DMA *dma, IfxDma_ChannelId channelId);
489 
490 /** \brief Return the status of a DMA channel (transaction pending)
491  * \param dma pointer to DMA module
492  * \param channelId DMA channel number
493  * \return TRUE if a transaction request for the given channel is pending
494  *
495  * \code
496  * // check for the channel request pending with the channel
497  * if (IfxDma_isChannelTransactionPending(chn[0].dma, chn[0].channelId) == TRUE) {
498  * // There is channel request pending for channel 0
499  * result |= 0;
500  * }
501  * \endcode
502  *
503  */
504 IFX_INLINE boolean IfxDma_isChannelTransactionPending(Ifx_DMA *dma, IfxDma_ChannelId channelId);
505 
506 /** \brief Request a DMA channel transaction
507  * \param dma pointer to DMA module
508  * \param channelId DMA channel number
509  * \return None
510  *
511  * A coding example can be found in \ref IfxDma_Dma_startChannelTransaction
512  *
513  */
514 IFX_INLINE void IfxDma_startChannelTransaction(Ifx_DMA *dma, IfxDma_ChannelId channelId);
515 
516 /** \brief Converts DMA circular range to circular code
517  * \param range DMA circular range
518  * \return DMA circular code
519  */
521 
522 /** \} */
523 
524 /** \addtogroup IfxLld_Dma_Std_Move_Engine
525  * \{ */
526 
527 /******************************************************************************/
528 /*-------------------------Inline Function Prototypes-------------------------*/
529 /******************************************************************************/
530 
531 /** \brief Clear the DMA error status flags
532  * \param dma pointer to DMA module
533  * \param moveEngine pointer to the DMA move engine
534  * \param mask value holds the bits to clear or mask
535  * \return None
536  *
537  * \code
538  * // Clear the status of the error flags (as defined in _Impl/IfxDma_cfg.h)
539  * IfxDma_clearErrorFlags(chn[0].dma,IfxDma_MoveEngine_1,
540  * IFXDMA_ERROR_S | // move engine source error
541  * IFXDMA_ERROR_D | // move engine destination error
542  * IFXDMA_ERROR_SPB | // bus error on SPB
543  * IFXDMA_ERROR_SRI | // bus error on SRI
544  * IFXDMA_ERROR_RAM | // RAM error
545  * IFXDMA_ERROR_SLL | // safe linked list CRC checksum error
546  * IFXDMA_ERROR_DLL); // failed linked list load error
547  * \endcode
548  *
549  */
550 IFX_INLINE void IfxDma_clearErrorFlags(Ifx_DMA *dma, IfxDma_MoveEngine moveEngine, uint32 mask);
551 
552 /** \brief Disable the generation of a Move engine destination error interrupt
553  * \param dma pointer to DMA module
554  * \param moveEngine pointer to the DMA move engine
555  * \return None
556  *
557  * A coding example can be found in \ref IfxDma_disableMoveEngineSourceError
558  *
559  */
561 
562 /** \brief Disable the generation of a Move engine source error interrupt
563  * \param dma pointer to DMA module
564  * \param moveEngine pointer to the DMA move engine
565  * \return None
566  *
567  * \code
568  * // Disable the move engine source and destination move errors
569  * IfxDma_disableMoveEngineSourceError(chn[0].dma,IfxDma_MoveEngine_1);
570  * IfxDma_disableMoveEngineDestinationError(chn[0].dma,IfxDma_MoveEngine_1);
571  * \endcode
572  *
573  */
575 
576 /** \brief Enable the generation of a Move engine destination error interrupt
577  * \param dma pointer to DMA module
578  * \param moveEngine pointer to the DMA move engine
579  * \return None
580  *
581  * A coding example can be found in \ref IfxDma_enableMoveEngineSourceError
582  *
583  */
585 
586 /** \brief Enable the generation of a Move engine source error interrupt
587  * \param dma pointer to DMA module
588  * \param moveEngine pointer to the DMA move engine
589  * \return None
590  *
591  * \code
592  * // Enable the move engine source and destination move errors
593  * IfxDma_enableMoveEngineSourceError(chn[0].dma,IfxDma_MoveEngine_1);
594  * IfxDma_enableMoveEngineDestinationError(chn[0].dma,IfxDma_MoveEngine_1);
595  * \endcode
596  *
597  */
599 
600 /** \brief Return the DMA error status flags
601  * \param dma pointer to DMA module
602  * \param moveEngine pointer to the DMA move engine
603  * \return the content of the DMA.ERRSR register
604  *
605  * \code
606  * uint32 errorFlags = 0;
607  *
608  * // Get the status of the error flags of move engine
609  * errorFlags = IfxDma_getErrorFlags(chn[0].dma,IfxDma_MoveEngine_1);
610  *
611  * if( errorFlags & IFXDMA_ERROR_S ) { // move engine source error
612  * }
613  *
614  * if( errorFlags & IFXDMA_ERROR_D ) { // move engine destination error
615  * // ...
616  * }
617  *
618  * if( errorFlags & IFXDMA_ERROR_SPB ) { // bus error on SPB
619  * // ...
620  * }
621  *
622  * if( errorFlags & IFXDMA_ERROR_SRI ) { // bus error on SRI
623  * // ...
624  * }
625  *
626  * if( errorFlags & IFXDMA_ERROR_RAM ) { // RAM error
627  * // ...
628  * }
629  *
630  * if( errorFlags & IFXDMA_ERROR_SLL ) { // safe linked list CRC checksum error
631  * // ...
632  * }
633  *
634  * if( errorFlags & IFXDMA_ERROR_DLL ) { // failed linked list load error
635  * // ...
636  * }
637  * \endcode
638  *
639  */
640 IFX_INLINE uint32 IfxDma_getErrorFlags(Ifx_DMA *dma, IfxDma_MoveEngine moveEngine);
641 
642 /** \} */
643 
644 /** \addtogroup IfxLld_Dma_Std_Channel_Configure
645  * \{ */
646 
647 /******************************************************************************/
648 /*-------------------------Inline Function Prototypes-------------------------*/
649 /******************************************************************************/
650 
651 /** \brief Get a channel source address
652  * \param dma pointer to DMA module
653  * \param channelId DMA channel number
654  * \return Actual channel destination address
655  *
656  * \code
657  * uint32 destAddr = IfxDma_getChannelDestinationAddress(chn[2].dma, chn[2].channelId);
658  *
659  * \endcode
660  *
661  */
663 
664 /** \brief Get a channel source address
665  * \param dma pointer to DMA module
666  * \param channelId DMA channel number
667  * \return Actual channel source address
668  *
669  * \code
670  * uint32 sourceAddr = IfxDma_getChannelSourceAddress(chn[2].dma, chn[2].channelId);
671  * \endcode
672  *
673  */
675 
676 /** \brief Return remaining DMA transfer count
677  * \param dma pointer to DMA module
678  * \param channelId DMA channel number
679  * \return Remaining DMA transfer count
680  *
681  * \code
682  * // Wait till transfer count (TCOUNT) becomes 0
683  *
684  * bool notFinished;
685  * do {
686  * notFinished = false;
687  * if( IfxDma_getChannelTransferCount(chn[0].dma, chn[0].channelId) ) {
688  * notFinished = true;
689  * break;
690  * }
691  * } while( notFinished );
692  * \endcode
693  *
694  */
696 
697 /** \brief get the time stamp
698  * \param dma pointer to DMA module
699  * \return the current time stamp
700  *
701  * \code
702  * uint32 timestamp = IfxDma_getTimestamp(chn[0].dma);
703  * \endcode
704  *
705  */
707 
708 /** \brief Configure the move count for each DMA channel transfer
709  * \param dma pointer to DMA module
710  * \param channelId DMA channel number
711  * \param blockMode value holds the number of moves with in a DMA transfer
712  * \return None
713  *
714  * A coding example can be found in \ref IfxDma_setChannelTransferCount
715  *
716  */
717 IFX_INLINE void IfxDma_setChannelBlockMode(Ifx_DMA *dma, IfxDma_ChannelId channelId, IfxDma_ChannelMove blockMode);
718 
719 /** \brief Configure a DMA channel to "continous transaction mode"
720  * After a transaction, the hardware request transaction remain enabled
721  * \param dma pointer to DMA module
722  * \param channelId DMA channel number
723  * \return None
724  *
725  * A coding example can be found in \ref IfxDma_enableChannelTransaction
726  *
727  */
728 IFX_INLINE void IfxDma_setChannelContinuousMode(Ifx_DMA *dma, IfxDma_ChannelId channelId);
729 
730 /** \brief Configure the destination address
731  * \param dma pointer to DMA module
732  * \param channelId DMA channel number
733  * \param address is the Initial address of the destination pointer
734  * \return None
735  *
736  * A coding example can be found in \ref IfxDma_setChannelSourceAddress
737  *
738  */
739 IFX_INLINE void IfxDma_setChannelDestinationAddress(Ifx_DMA *dma, IfxDma_ChannelId channelId, void *address);
740 
741 /** \brief Configure a DMA channel destination pointer
742  * \param dma pointer to DMA module
743  * \param channelId DMA channel number
744  * \param incStep Specifies the pointer incrementation step
745  * \param direction Specifies the incrementation direction
746  * \param size Specifies the size of the circular buffer
747  * \return None
748  *
749  * A coding example can be found in \ref IfxDma_setChannelSourceIncrementStep
750  *
751  */
753 
754 /** \brief Configure a DMA channel move
755  * \param dma pointer to DMA module
756  * \param channelId DMA channel number
757  * \param moveSize value holds the opcode or size of data of individual moves with in a DMA transfer
758  * \return None
759  *
760  * A coding example can be found in \ref IfxDma_setChannelTransferCount
761  *
762  */
763 IFX_INLINE void IfxDma_setChannelMoveSize(Ifx_DMA *dma, IfxDma_ChannelId channelId, IfxDma_ChannelMoveSize moveSize);
764 
765 /** \brief Configure a DMA channel shadow pointer
766  * \param dma pointer to DMA module
767  * \param channelId DMA channel number
768  * \param shadow Specifies the shadow pointer
769  * \return None
770  *
771  * \code
772  * // Push the shadow mode into double buffer
773  * IfxDma_setChannelShadow(chn[0].dma, chn[0].channelId,
774  * IfxDma_ChannelShadow_doubleSourceBufferingSwSwitch);
775  * \endcode
776  *
777  */
778 IFX_INLINE void IfxDma_setChannelShadow(Ifx_DMA *dma, IfxDma_ChannelId channelId, IfxDma_ChannelShadow shadow);
779 
780 /** \brief Configure a DMA channel to "single transaction mode"
781  * After a transaction, the hardware request transaction is disabled, and must be set by software again
782  * \param dma pointer to DMA module
783  * \param channelId DMA channel number
784  * \return None
785  *
786  * A coding example can be found in \ref IfxDma_enableChannelTransaction
787  *
788  */
789 IFX_INLINE void IfxDma_setChannelSingleMode(Ifx_DMA *dma, IfxDma_ChannelId channelId);
790 
791 /** \brief Configure a DMA channel to "single transaction mode"
792  * One transfer request starts a complete DMA transaction
793  * \param dma pointer to DMA module
794  * \param channelId DMA channel number
795  * \return None
796  *
797  * A coding example can be found in \ref IfxDma_setChannelTransferCount
798  *
799  */
801 
802 /** \brief Configure a DMA channel to "single transfer mode"
803  * A transfer request is required for each transfer
804  * \param dma pointer to DMA module
805  * \param channelId DMA channel number
806  * \return None
807  *
808  * A coding example can be found in \ref IfxDma_setChannelTransferCount
809  *
810  */
811 IFX_INLINE void IfxDma_setChannelSingleTransfer(Ifx_DMA *dma, IfxDma_ChannelId channelId);
812 
813 /** \brief Configure the source address
814  * \param dma pointer to DMA module
815  * \param channelId DMA channel number
816  * \param address is the Initial address of the source pointer
817  * \return None
818  *
819  * \code
820  * // Check for the end of current transaction and before trigger the channel request for
821  * // for another channel, re configure the source and destination addresses
822  *
823  * while(!(IfxDma_getAndClearChannelInterrupt(chn[1].dma, chn[1].channelId)));
824  *
825  * // Re-Program the source address for the channel 2
826  * IfxDma_setChannelSourceAddress(chn[2].dma, chn[2].channelId,Sadr);
827  *
828  * // Re-Program the destination address for channel 2
829  * IfxDma_setChannelDestinationAddress(chn[2].dma, chn[2].channelId,Dadr);
830  *
831  * // Start DMA transaction for channel 2
832  * IfxDma_Dma_startChannelTransaction(&chn[2]);
833  * \endcode
834  *
835  */
836 IFX_INLINE void IfxDma_setChannelSourceAddress(Ifx_DMA *dma, IfxDma_ChannelId channelId, const void *address);
837 
838 /** \brief Configure a DMA channel source pointer
839  * \param dma pointer to DMA module
840  * \param channelId DMA channel number
841  * \param incStep Specifies the pointer incrementation step
842  * \param direction Specifies the incrementation direction
843  * \param size Specifies the size of the circular buffer
844  * \return None
845  *
846  * \code
847  * // Re-program the source and destination circular buffer control fields
848  * IfxDma_setChannelSourceIncrementStep(chn[0].dma, chn[0].channelId, IfxDma_ChannelIncrementStep_2, IfxDma_ChannelIncrementDirection_negative, IfxDma_ChannelIncrementCircular_16);
849  *
850  * IfxDma_setChannelDestinationIncrementStep(chn[0].dma, chn[0].channelId, IfxDma_ChannelIncrementStep_2, IfxDma_ChannelIncrementDirection_negative, IfxDma_ChannelIncrementCircular_16);
851  * \endcode
852  *
853  */
855 
856 /** \brief Configure the move count of a DMA channel transaction
857  * \param dma pointer to DMA module
858  * \param channelId DMA channel number
859  * \param transferCount value holds the DMA transfers within a transaction (1..16383; 0 handled like 1 transaction)
860  * \return None
861  *
862  * \code
863  * // Start DMA transaction
864  * IfxDma_Dma_startChannelTransaction(&chn[0]);
865  *
866  * // Wait till end of transaction
867  * while(!(IfxDma_getAndClearChannelInterrupt(chn[0].dma, chn[0].channelId)));
868  *
869  * // Change the TREL configuration for channel 1
870  * IfxDma_setChannelTransferCount(chn[1].dma, chn[1].channelId,0x6);
871  *
872  * // Change the BLKM configuration for channel 1
873  * IfxDma_setChannelBlockMode(chn[1].dma, chn[1].channelId,IfxDma_ChannelMove_3);
874  *
875  * // Change the Move size configuration for channel 1
876  * IfxDma_setChannelMoveSize(chn[1].dma, chn[1].channelId,IfxDma_ChannelMoveSize_64bit);
877  *
878  * // Pull down the channel pending request after the first transfer is initiated
879  * IfxDma_setChannelSingleTransfer(chn[1].dma, chn[1].channelId);
880  *
881  * // Pull down the channel pending request after the transaction gets over
882  * IfxDma_setChannelSingleTransaction(chn[2].dma, chn[2].channelId);
883  *
884  * // Start DMA transaction
885  * IfxDma_Dma_startChannelTransaction(&chn[1]);
886  *
887  * // Start DMA transaction
888  * IfxDma_Dma_startChannelTransaction(&chn[2]);
889  * \endcode
890  *
891  */
892 IFX_INLINE void IfxDma_setChannelTransferCount(Ifx_DMA *dma, IfxDma_ChannelId channelId, uint32 transferCount);
893 
894 /** \brief Configure the shadow pointer register to read only
895  * \param dma pointer to DMA module
896  * \param channelId DMA channel number
897  * \return None
898  *
899  * \code
900  * // Disable the shadow mode to come out of double buffer mode
901  * IfxDma_writeChannelShadowDisable(chn[0].dma, chn[0].channelId);
902  * \endcode
903  *
904  */
905 IFX_INLINE void IfxDma_writeChannelShadowDisable(Ifx_DMA *dma, IfxDma_ChannelId channelId);
906 
907 /** \brief Configure the shadow pointer register to write-able
908  * \param dma pointer to DMA module
909  * \param channelId DMA channel number
910  * \return None
911  *
912  * \code
913  * // Enable the shadow mode to come out of double buffer mode
914  * IfxDma_writeChannelShadowEnable(chn[0].dma, chn[0].channelId);
915  * \endcode
916  *
917  */
918 IFX_INLINE void IfxDma_writeChannelShadowEnable(Ifx_DMA *dma, IfxDma_ChannelId channelId);
919 
920 /** \} */
921 
922 /** \addtogroup IfxLld_Dma_Std_Channel_Halt
923  * \{ */
924 
925 /******************************************************************************/
926 /*-------------------------Inline Function Prototypes-------------------------*/
927 /******************************************************************************/
928 
929 /** \brief Clear channel halt request and aknowledgement
930  * \param dma pointer to DMA module
931  * \param channelId DMA channel number
932  * \return None
933  *
934  * \code
935  * // Quit the halt mode of operation
936  * IfxDma_clearChannelHalt(chn[0].dma, chn[0].channelId);
937  * \endcode
938  *
939  */
940 IFX_INLINE void IfxDma_clearChannelHalt(Ifx_DMA *dma, IfxDma_ChannelId channelId);
941 
942 /** \brief Get channel halt aknowledgement
943  * \param dma pointer to DMA module
944  * \param channelId DMA channel number
945  * \return halt aknowledgement
946  *
947  * \code
948  * // Check for the channel halt aknowledgement
949  * while(!(IfxDma_getChannelHalt(chn[0].dma, chn[0].channelId)));
950  * \endcode
951  *
952  */
953 IFX_INLINE boolean IfxDma_getChannelHalt(Ifx_DMA *dma, IfxDma_ChannelId channelId);
954 
955 /** \brief setting channel halt request
956  * \param dma pointer to DMA module
957  * \param channelId DMA channel number
958  * \return None
959  *
960  * \code
961  * // Halt the channel processing
962  * IfxDma_setChannelHalt(chn[0].dma,chn[0].channelId);
963  * \endcode
964  *
965  */
966 IFX_INLINE void IfxDma_setChannelHalt(Ifx_DMA *dma, IfxDma_ChannelId channelId);
967 
968 /** \} */
969 
970 /** \addtogroup IfxLld_Dma_Std_Double_Buffer
971  * \{ */
972 
973 /******************************************************************************/
974 /*-------------------------Inline Function Prototypes-------------------------*/
975 /******************************************************************************/
976 
977 /** \brief get information on buffer being read by software and clear the notification flag
978  * \param dma pointer to DMA module
979  * \param channelId DMA channel number
980  * \return TRUE if one of the buffers is being read by software
981  * FALSE if one of the buffers is already read by software
982  *
983  * \code
984  * // Check the buffer being read (Double buffer operation mode)
985  * while(!(IfxDma_getDoubleBufferRead(chn[0].dma, chn[0].channelId)));
986  * \endcode
987  *
988  */
989 IFX_INLINE boolean IfxDma_getDoubleBufferRead(Ifx_DMA *dma, IfxDma_ChannelId channelId);
990 
991 /** \brief get Double buffer selection
992  * \param dma pointer to DMA module
993  * \param channelId channelId DMA channel number
994  * \return TRUE if buffer 1 is being filled
995  * FALSE if buffer 0 is being filled
996  *
997  * \code
998  * boolean buffer_being_filled;
999  *
1000  * // Check the buffer being filled (Double buffer operation mode)
1001  * buffer_being_filled = IfxDma_getDoubleBufferSelection(chn[0].dma, chn[0].channelId));
1002  * \endcode
1003  *
1004  */
1005 IFX_INLINE boolean IfxDma_getDoubleBufferSelection(Ifx_DMA *dma, IfxDma_ChannelId channelId);
1006 
1007 /** \brief keeps the double buffer active
1008  * \param dma pointer to DMA module
1009  * \param channelId DMA channel number
1010  * \return None
1011  *
1012  * \code
1013  * IfxDma_keepDoubleBufferActive(chn[0].dma, chn[0].channelId);
1014  * \endcode
1015  *
1016  */
1017 IFX_INLINE void IfxDma_keepDoubleBufferActive(Ifx_DMA *dma, IfxDma_ChannelId channelId);
1018 
1019 /** \brief Double buffer switch application
1020  * \param dma pointer to DMA module
1021  * \param channelId DMA channel number
1022  * \return None
1023  *
1024  * \code
1025  * // Apply software buffer switch
1026  * IfxDma_switchDoubleBuffer(chn[0].dma, chn[0].channelId);
1027  * \endcode
1028  *
1029  */
1030 IFX_INLINE void IfxDma_switchDoubleBuffer(Ifx_DMA *dma, IfxDma_ChannelId channelId);
1031 
1032 /** \} */
1033 
1034 /** \addtogroup IfxLld_Dma_Std_Interrupts
1035  * \{ */
1036 
1037 /******************************************************************************/
1038 /*-------------------------Inline Function Prototypes-------------------------*/
1039 /******************************************************************************/
1040 
1041 /** \brief Clear a channel transfer interrupt flag
1042  * \param dma pointer to DMA module
1043  * \param channelId channel for which the interrupt flag should be cleared
1044  * \return None
1045  *
1046  * see Dma.INTSR
1047  *
1048  */
1049 IFX_INLINE void IfxDma_clearChannelInterrupt(Ifx_DMA *dma, IfxDma_ChannelId channelId);
1050 
1051 /** \brief Disable channel interrupt trigger
1052  * \param dma pointer to DMA module
1053  * \param channelId DMA channel number
1054  * \return None
1055  *
1056  * \code
1057  * IfxDma_disableChannelInterrupt(chn[0].dma, chn[0].channelId);
1058  * \endcode
1059  *
1060  */
1061 IFX_INLINE void IfxDma_disableChannelInterrupt(Ifx_DMA *dma, IfxDma_ChannelId channelId);
1062 
1063 /** \brief Enable channel interrupt trigger
1064  * \param dma pointer to DMA module
1065  * \param channelId DMA channel number
1066  * \return None
1067  *
1068  * \code
1069  * IfxDma_enableChannelInterrupt(chn[0].dma, chn[0].channelId);
1070  * \endcode
1071  *
1072  */
1073 IFX_INLINE void IfxDma_enableChannelInterrupt(Ifx_DMA *dma, IfxDma_ChannelId channelId);
1074 
1075 /** \brief Return and clear a channel transfer interrupt flag
1076  * The flag is automatically cleared with the call to this function
1077  * \param dma pointer to DMA module
1078  * \param channelId DMA channel number
1079  * \return TRUE if the interrupt flag is set
1080  * FALSE if the interrupt flag is not set
1081  *
1082  * \code
1083  * // wait for the end of transaction for intended channel by checking the channel interrupt flag
1084  * // and clear it once it is set and checked
1085  *
1086  * // Wait till end of the transaction
1087  * while(!(IfxDma_getAndClearChannelInterrupt(chn[2].dma, chn[2].channelId)));
1088  * \endcode
1089  *
1090  */
1091 IFX_INLINE boolean IfxDma_getAndClearChannelInterrupt(Ifx_DMA *dma, IfxDma_ChannelId channelId);
1092 
1093 /** \brief Returns and clears the pattern detection interrupt flag
1094  * \param dma pointer to DMA module
1095  * \param channelId DMA channel number
1096  * \return TRUE if pattern detection for a given channel is found
1097  * FALSE if pattern detection for a given channel is not found
1098  *
1099  * \code
1100  * // wait till pattern match is found for given channel
1101  * // and clear it once it is set and checked
1102  *
1103  * // Wait for the pattern detection
1104  * while(!(IfxDma_getAndClearChannelPatternDetectionInterrupt(chn[0].dma, chn[0].channelId)));
1105  * \endcode
1106  *
1107  */
1109 
1110 /** \brief Returns and clears the status of channel wrap destination buffer interrupt trigger flag
1111  * \param dma pointer to DMA module
1112  * \param channelId DMA channel number
1113  * \return TRUE if wrap destination buffer interrupt trigger flag is set
1114  * FALSE if wrap destination buffer interrupt trigger flag is not set or get cleared already
1115  *
1116  * \code
1117  * // wait for the destination buffer wrap interrupt flag
1118  * // and clear it once it is set and checked
1119  * boolean destinationWrapFlag;
1120  *
1121  * destinationWrapFlag = IfxDma_getAndClearChannelWrapDestinationBufferInterrupt(chn[0].dma, chn[0].channelId);
1122  * \endcode
1123  *
1124  */
1126 
1127 /** \brief Returns and clears the status of channel wrap source buffer interrupt trigger flag
1128  * \param dma pointer to DMA module
1129  * \param channelId DMA channel number
1130  * \return TRUE if wrap source buffer interrupt trigger flag is set
1131  * FALSE if wrap source buffer interrupt trigger flag is not set or get cleared already
1132  *
1133  * \code
1134  * // wait for the source buffer wrap interrupt flag
1135  * // and clear it once it is set and checked
1136  * boolean sourceWrapFlag;
1137  *
1138  * sourceWrapFlag = IfxDma_getAndClearChannelWrapSourceBufferInterrupt(chn[0].dma, chn[0].channelId);
1139  * \endcode
1140  *
1141  */
1143 
1144 /** \brief Return a channel transfer interrupt flag
1145  * \param dma pointer to DMA module
1146  * \param channelId channel for which the interrupt flag should be returned
1147  * \return TRUE if the interrupt flag is set
1148  * FALSE if the interrupt flag is not set
1149  *
1150  * see Dma.INTSR
1151  *
1152  */
1153 IFX_INLINE boolean IfxDma_getChannelInterrupt(Ifx_DMA *dma, IfxDma_ChannelId channelId);
1154 
1155 /** \brief Returns whether the old value of pattern detection corresponding pattern comparison operation found a pattern match in previous DMA * read move or not
1156  * \param dma pointer to DMA module
1157  * \param channelId DMA channel number
1158  * \return TRUE if corresponding pattern comparison operation found a pattern match in previous DMA read move or not
1159  * FALSE if corresponding pattern comparison operation did not find a pattern match in previous DMA read move
1160  *
1161  * \code
1162  * boolean patternDetectOldVal;
1163  *
1164  * // Check the old value of the pattern detection
1165  * patternDetectOldVal = IfxDma_getChannelPatternDetectionOldValue(chn[0].dma, chn[0].channelId);
1166  * \endcode
1167  *
1168  */
1170 
1171 /** \brief Returns the SRC pointer for given DMA channel
1172  * \param dma pointer to DMA module
1173  * \param channelId DMA channel number
1174  * \return SRC pointer for given DMA channel
1175  *
1176  * \code
1177  *
1178  * \endcode
1179  *
1180  */
1181 IFX_INLINE volatile Ifx_SRC_SRCR *IfxDma_getSrcPointer(Ifx_DMA *dma, IfxDma_ChannelId channelId);
1182 
1183 /** \brief Setting of channel interrupt service request by software
1184  * \param dma pointer to DMA module
1185  * \param channelId DMA channel number
1186  * \return None
1187  *
1188  * \code
1189  * // Set the channel interrupt service request through software
1190  * IfxDma_setChannelInterruptServiceRequest(chn[0].dma, chn[0].channelId);
1191  * \endcode
1192  *
1193  */
1195 
1196 /** \} */
1197 
1198 /******************************************************************************/
1199 /*---------------------Inline Function Implementations------------------------*/
1200 /******************************************************************************/
1201 
1202 IFX_INLINE boolean IfxDma_isChannelReset(Ifx_DMA *dma, IfxDma_ChannelId channelId)
1203 {
1204  return dma->TSR[channelId].B.RST != 0;
1205 }
1206 
1207 
1208 IFX_INLINE void IfxDma_resetChannel(Ifx_DMA *dma, IfxDma_ChannelId channelId)
1209 {
1210  dma->TSR[channelId].B.RST = 1;
1211 }
1212 
1213 
1215 {
1216  dma->TSR[channelId].B.CTL = 1;
1217 }
1218 
1219 
1221 {
1222  dma->TSR[channelId].B.DCH = 1;
1223 }
1224 
1225 
1227 {
1228  dma->CH[channelId].ADICR.B.ETRL = 0;
1229 }
1230 
1231 
1233 {
1234  dma->TSR[channelId].B.ECH = 1;
1235 }
1236 
1237 
1239 {
1240  dma->CH[channelId].ADICR.B.ETRL = 1;
1241 }
1242 
1243 
1245 {
1246  return dma->TSR[channelId].B.TRL != 0;
1247 }
1248 
1249 
1251 {
1252  return dma->TSR[channelId].B.HTRE != 0;
1253 }
1254 
1255 
1257 {
1258  return dma->TSR[channelId].B.CH != 0;
1259 }
1260 
1261 
1263 {
1264  dma->CH[channelId].CHCSR.B.SCH = 1;
1265 }
1266 
1267 
1269 {
1270  return (IfxDma_ChannelIncrementCircular)(31 - __clz((uint32)range));
1271 }
1272 
1273 
1274 IFX_INLINE void IfxDma_clearErrorFlags(Ifx_DMA *dma, IfxDma_MoveEngine moveEngine, uint32 mask)
1275 {
1276  if (moveEngine == IfxDma_MoveEngine_1)
1277  {
1278  dma->BLK1.CLRE.U = mask;
1279  }
1280  else
1281  {
1282  dma->BLK0.CLRE.U = mask;
1283  }
1284 }
1285 
1286 
1288 {
1289  if (moveEngine == IfxDma_MoveEngine_1)
1290  {
1291  dma->BLK1.EER.B.EDER = 0;
1292  }
1293  else
1294  {
1295  dma->BLK0.EER.B.EDER = 0;
1296  }
1297 }
1298 
1299 
1301 {
1302  if (moveEngine == IfxDma_MoveEngine_1)
1303  {
1304  dma->BLK1.EER.B.ESER = 0;
1305  }
1306  else
1307  {
1308  dma->BLK0.EER.B.ESER = 0;
1309  }
1310 }
1311 
1312 
1314 {
1315  if (moveEngine == IfxDma_MoveEngine_1)
1316  {
1317  dma->BLK1.EER.B.EDER = 1;
1318  }
1319  else
1320  {
1321  dma->BLK0.EER.B.EDER = 1;
1322  }
1323 }
1324 
1325 
1327 {
1328  if (moveEngine == IfxDma_MoveEngine_1)
1329  {
1330  dma->BLK1.EER.B.ESER = 1;
1331  }
1332  else
1333  {
1334  dma->BLK0.EER.B.ESER = 1;
1335  }
1336 }
1337 
1338 
1340 {
1341  if (moveEngine == IfxDma_MoveEngine_1)
1342  {
1343  return dma->BLK1.ERRSR.U;
1344  }
1345  else
1346  {
1347  return dma->BLK0.ERRSR.U;
1348  }
1349 }
1350 
1351 
1353 {
1354  return dma->CH[channelId].DADR.U;
1355 }
1356 
1357 
1359 {
1360  return dma->CH[channelId].SADR.U;
1361 }
1362 
1363 
1365 {
1366  return dma->CH[channelId].CHCSR.B.TCOUNT;
1367 }
1368 
1369 
1371 {
1372  return dma->TIME.U;
1373 }
1374 
1375 
1377 {
1378  dma->CH[channelId].CHCFGR.B.BLKM = blockMode;
1379 }
1380 
1381 
1383 {
1384  dma->CH[channelId].CHCFGR.B.CHMODE = 1;
1385 }
1386 
1387 
1388 IFX_INLINE void IfxDma_setChannelDestinationAddress(Ifx_DMA *dma, IfxDma_ChannelId channelId, void *address)
1389 {
1390  dma->CH[channelId].DADR.U = (uint32)address;
1391 }
1392 
1393 
1395 {
1396  Ifx_DMA_CH_ADICR adicr;
1397  adicr.U = dma->CH[channelId].ADICR.U;
1398  adicr.B.DMF = incStep;
1399  adicr.B.INCD = direction;
1400  adicr.B.CBLD = size;
1401  dma->CH[channelId].ADICR.U = adicr.U;
1402 }
1403 
1404 
1406 {
1407  dma->CH[channelId].CHCFGR.B.CHDW = moveSize;
1408 }
1409 
1410 
1412 {
1413  dma->CH[channelId].ADICR.B.SHCT = shadow;
1414 }
1415 
1416 
1418 {
1419  dma->CH[channelId].CHCFGR.B.CHMODE = 0;
1420 }
1421 
1422 
1424 {
1425  dma->CH[channelId].CHCFGR.B.RROAT = 1;
1426 }
1427 
1428 
1430 {
1431  dma->CH[channelId].CHCFGR.B.RROAT = 0;
1432 }
1433 
1434 
1435 IFX_INLINE void IfxDma_setChannelSourceAddress(Ifx_DMA *dma, IfxDma_ChannelId channelId, const void *address)
1436 {
1437  dma->CH[channelId].SADR.U = (uint32)address;
1438 }
1439 
1440 
1442 {
1443  Ifx_DMA_CH_ADICR adicr;
1444  adicr.U = dma->CH[channelId].ADICR.U;
1445  adicr.B.SMF = incStep;
1446  adicr.B.INCS = direction;
1447  adicr.B.CBLS = size;
1448  dma->CH[channelId].ADICR.U = adicr.U;
1449 }
1450 
1451 
1452 IFX_INLINE void IfxDma_setChannelTransferCount(Ifx_DMA *dma, IfxDma_ChannelId channelId, uint32 transferCount)
1453 {
1454  dma->CH[channelId].CHCFGR.B.TREL = transferCount;
1455 }
1456 
1457 
1459 {
1460  dma->CH[channelId].ADICR.B.SHCT &= ~(3 << 2);
1461 }
1462 
1463 
1465 {
1466  dma->CH[channelId].ADICR.B.SHCT |= (1 << 2);
1467  dma->CH[channelId].ADICR.B.SHCT &= ~(1 << 3);
1468 }
1469 
1470 
1472 {
1473  dma->TSR[channelId].B.HLTCLR = 1;
1474 }
1475 
1476 
1477 IFX_INLINE boolean IfxDma_getChannelHalt(Ifx_DMA *dma, IfxDma_ChannelId channelId)
1478 {
1479  return dma->TSR[channelId].B.HLTACK != 0;
1480 }
1481 
1482 
1484 {
1485  dma->TSR[channelId].B.HLTREQ = 1;
1486 }
1487 
1488 
1490 {
1491  boolean result;
1492 
1493  result = dma->CH[channelId].CHCSR.B.FROZEN != 0;
1494 
1495  if (result == 1)
1496  {
1497  dma->CH[channelId].CHCSR.B.FROZEN = FALSE;
1498  }
1499 
1500  return result;
1501 }
1502 
1503 
1505 {
1506  return dma->CH[channelId].CHCSR.B.BUFFER != 0;
1507 }
1508 
1509 
1511 {
1512  dma->CH[channelId].CHCSR.U = 0U << IFX_DMA_CH_CHCSR_FROZEN_OFF;
1513 }
1514 
1515 
1517 {
1518  dma->CH[channelId].CHCSR.B.SWB = 1;
1519 }
1520 
1521 
1523 {
1524  dma->CH[channelId].CHCSR.B.CICH = 1;
1525 }
1526 
1527 
1529 {
1530  dma->CH[channelId].ADICR.B.INTCT &= ~(1 << 0); // TODO: should we define a special bitmask for this bit manipulation?
1531 }
1532 
1533 
1535 {
1536  dma->CH[channelId].ADICR.B.INTCT |= (1 << 0); // TODO: should we define a special bitmask for this bit manipulation?
1537 }
1538 
1539 
1541 {
1542  boolean result;
1543 
1544  result = dma->CH[channelId].CHCSR.B.ICH != 0;
1545 
1546  if (result == 1)
1547  {
1548  dma->CH[channelId].CHCSR.B.CICH = TRUE;
1549  }
1550 
1551  return result;
1552 }
1553 
1554 
1556 {
1557  boolean result;
1558 
1559  result = dma->CH[channelId].CHCSR.B.IPM != 0;
1560 
1561  if (result == 1)
1562  {
1563  dma->CH[channelId].CHCSR.B.CICH = TRUE;
1564  }
1565 
1566  return result;
1567 }
1568 
1569 
1571 {
1572  boolean result;
1573 
1574  result = dma->CH[channelId].CHCSR.B.WRPD != 0;
1575 
1576  if (result == 1)
1577  {
1578  dma->CH[channelId].CHCSR.B.CWRP = TRUE;
1579  }
1580 
1581  return result;
1582 }
1583 
1584 
1586 {
1587  boolean result;
1588 
1589  result = dma->CH[channelId].CHCSR.B.WRPS != 0;
1590 
1591  if (result == 1)
1592  {
1593  dma->CH[channelId].CHCSR.B.CWRP = TRUE;
1594  }
1595 
1596  return result;
1597 }
1598 
1599 
1601 {
1602  boolean result;
1603 
1604  result = dma->CH[channelId].CHCSR.B.ICH;
1605 
1606  return result;
1607 }
1608 
1609 
1611 {
1612  return dma->CH[channelId].CHCSR.B.LXO != 0;
1613 }
1614 
1615 
1616 IFX_INLINE volatile Ifx_SRC_SRCR *IfxDma_getSrcPointer(Ifx_DMA *dma, IfxDma_ChannelId channelId)
1617 {
1618  // only a single DMA available, therefore no check for the dma pointer required
1619  return &MODULE_SRC.DMA.DMA[0].CH[channelId];
1620 }
1621 
1622 
1624 {
1625  dma->CH[channelId].CHCSR.B.SIT = 1;
1626 }
1627 
1628 
1629 #endif /* IFXDMA_H */