iLLD_TC27xC  1.0
IfxPsi5s.h
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1 /**
2  * \file IfxPsi5s.h
3  * \brief PSI5S basic functionality
4  * \ingroup IfxLld_Psi5s
5  *
6  * \version iLLD_0_1_0_10
7  * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
8  *
9  *
10  * IMPORTANT NOTICE
11  *
12  *
13  * Infineon Technologies AG (Infineon) is supplying this file for use
14  * exclusively with Infineon's microcontroller products. This file can be freely
15  * distributed within development tools that are supporting such microcontroller
16  * products.
17  *
18  * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
19  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
20  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
21  * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
22  * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
23  *
24  * \defgroup IfxLld_Psi5s PSI5S
25  * \ingroup IfxLld
26  * \defgroup IfxLld_Psi5s_Std Standard Driver
27  * \ingroup IfxLld_Psi5s
28  * \defgroup IfxLld_Psi5s_Std_Enumerations Enumerations
29  * \ingroup IfxLld_Psi5s_Std
30  * \defgroup IfxLld_Psi5s_Std_Channel Channel Operative Functions
31  * \ingroup IfxLld_Psi5s_Std
32  * \defgroup IfxLld_Psi5s_Std_IO IO Pin Configuration Functions
33  * \ingroup IfxLld_Psi5s_Std
34  */
35 
36 #ifndef IFXPSI5S_H
37 #define IFXPSI5S_H 1
38 
39 /******************************************************************************/
40 /*----------------------------------Includes----------------------------------*/
41 /******************************************************************************/
42 
43 #include "_Impl/IfxPsi5s_cfg.h"
45 
46 /******************************************************************************/
47 /*--------------------------------Enumerations--------------------------------*/
48 /******************************************************************************/
49 
50 /** \addtogroup IfxLld_Psi5s_Std_Enumerations
51  * \{ */
52 /** \brief MODULE_PSI5S.IOCR.ALTI:Alternate input
53  */
54 typedef enum
55 {
56  IfxPsi5s_AlternateInput_0 = 0, /**< \brief Alternate Input 0 */
57  IfxPsi5s_AlternateInput_1, /**< \brief Alternate Input 1 */
58  IfxPsi5s_AlternateInput_2, /**< \brief Alternate Input 2 */
59  IfxPsi5s_AlternateInput_3, /**< \brief Alternate Input 3 */
61 
62 /** \brief MODULE_PSI5S.BG.BR_VALUE:Baudrate prescalar select
63  */
64 typedef enum
65 {
66  IfxPsi5s_AscBaudratePrescalar_divideBy2 = 0, /**< \brief Divide by 2 is selected for baudrate timer prescalar */
67  IfxPsi5s_AscBaudratePrescalar_divideBy3 = 1 /**< \brief Divide by 3 is selected for baudrate timer prescalar */
69 
70 /** \brief MODULE_PSI5S.CON.M:ASC mode of operation
71  */
72 typedef enum
73 {
74  IfxPsi5s_AscMode_sync = 0, /**< \brief Synchronous mode */
75  IfxPsi5s_AscMode_async_8bitData = 1, /**< \brief Asynchronous mode with 8 bit data */
76  IfxPsi5s_AscMode_async_7bitDataWithParity = 3, /**< \brief Asynchronous mode with 7 bit data with parity */
77  IfxPsi5s_AscMode_async_9bitData = 4, /**< \brief Asynchronous mode with 9 bit data */
78  IfxPsi5s_AscMode_async_8bitDataWithWakeup = 5, /**< \brief Asynchronous mode with 8 bit data with wakeup */
79  IfxPsi5s_AscMode_async_8bitDataWithParity = 7 /**< \brief Asynchronous mode with 8 bit data with parity */
81 
82 /** \brief MODULE_PSI5S.CON.STP: Number of stop bits
83  */
84 typedef enum
85 {
86  IfxPsi5s_AscStopBits_1 = 0, /**< \brief 1 stop bit */
87  IfxPsi5s_AscStopBits_2, /**< \brief 2 stop bit */
89 
90 /** \brief PSI5S Channel Id defined in MODULE_PSI5S.RDS.B.CID.
91  */
92 typedef enum
93 {
94  IfxPsi5s_ChannelId_0 = 0, /**< \brief Ifx_PSI5S Channel 0 */
95  IfxPsi5s_ChannelId_1, /**< \brief Ifx_PSI5S Channel 1 */
96  IfxPsi5s_ChannelId_2, /**< \brief Ifx_PSI5S Channel 2 */
97  IfxPsi5s_ChannelId_3, /**< \brief Ifx_PSI5S Channel 3 */
98  IfxPsi5s_ChannelId_4, /**< \brief Ifx_PSI5S Channel 4 */
99  IfxPsi5s_ChannelId_5, /**< \brief Ifx_PSI5S Channel 5 */
100  IfxPsi5s_ChannelId_6, /**< \brief Ifx_PSI5S Channel 6 */
101  IfxPsi5s_ChannelId_7, /**< \brief Ifx_PSI5S Channel 7 */
102  IfxPsi5s_ChannelId_none = -1 /**< \brief None of the Ifx_PSI5S Channels */
104 
105 /** \brief Clock Selection
106  */
107 typedef enum
108 {
109  IfxPsi5s_ClockType_fracDiv = 0, /**< \brief Fractional Divide clock */
110  IfxPsi5s_ClockType_timeStamp = 1, /**< \brief Timestamp clock */
111  IfxPsi5s_ClockType_ascFracDiv = 2, /**< \brief Asc Fractional divider clock */
112  IfxPsi5s_ClockType_ascOutput = 3 /**< \brief Asc output clock */
114 
115 /** \brief MODULE_PSI5S.RCRAx.CRCy(x= 0,1,..7:y=0,1,..,5),MODULE_PSI5S.RCRBx.CRCy(x= 0,1,..7:y=0,1,..,5)CRC or parity
116  */
117 typedef enum
118 {
119  IfxPsi5s_CrcOrParity_parity = 0, /**< \brief parity selection */
120  IfxPsi5s_CrcOrParity_crc = 1 /**< \brief CRC selection */
122 
123 /** \brief MODULE_PSI5S.FDR.DM;MODULE_PSI5S.FDRT.B.DM:Divider mode
124  */
125 typedef enum
126 {
127  IfxPsi5s_DividerMode_spb = 0, /**< \brief divider mode is off */
128  IfxPsi5s_DividerMode_normal = 1, /**< \brief divider mode is normal */
129  IfxPsi5s_DividerMode_fractional = 2, /**< \brief divider mode is fractional */
130  IfxPsi5s_DividerMode_off = 3 /**< \brief divider mode is off */
132 
133 /** \brief MODULE_PSI5S.SCRx.EPS(x=0,1,...,7):Enhanced protocol types
134  */
135 typedef enum
136 {
137  IfxPsi5s_EnhancedProtocol_toothGapMethod = 0, /**< \brief toothGapMethod Enhanced protocol type */
138  IfxPsi5s_EnhancedProtocol_pulseWidth_frameFormat_1to3 = 1, /**< \brief pulseWidth_frameFormat_1to3 Enhanced protocol type */
139  IfxPsi5s_EnhancedProtocol_pulseWidth_frameFormat_4 = 3 /**< \brief pulseWidth_frameFormat_4 Enhanced protocol type */
141 
142 /** \brief MODULE_PSI5S.RCRAx.FIDS(x=0,1,....,7):.Frame ID updation
143  */
144 typedef enum
145 {
146  IfxPsi5s_FrameId_frameHeader = 0, /**< \brief Frame ID is updated from packet frame header (Sync mode) */
147  IfxPsi5s_FrameId_rollingNumber = 1 /**< \brief Frame ID is a rolling number 0 .. 5 copied from FCNT */
149 
150 /** \brief MODULE_PSI5S.GCR.IDT:Idle time bit count
151  */
152 typedef enum
153 {
154  IfxPsi5s_IdleTime_1 = 0, /**< \brief 1 bit Idle time */
155  IfxPsi5s_IdleTime_2, /**< \brief 2 bit Idle time */
156  IfxPsi5s_IdleTime_3, /**< \brief 3 bit Idle time */
157  IfxPsi5s_IdleTime_4, /**< \brief 4 bit Idle time */
158  IfxPsi5s_IdleTime_5, /**< \brief 5 bit Idle time */
159  IfxPsi5s_IdleTime_6, /**< \brief 6 bit Idle time */
160  IfxPsi5s_IdleTime_7, /**< \brief 7 bit Idle time */
161  IfxPsi5s_IdleTime_8, /**< \brief 8 bit Idle time */
162  IfxPsi5s_IdleTime_9, /**< \brief 9 bit Idle time */
163  IfxPsi5s_IdleTime_10, /**< \brief 10 bit Idle time */
164  IfxPsi5s_IdleTime_11, /**< \brief 11 bit Idle time */
165  IfxPsi5s_IdleTime_12, /**< \brief 12 bit Idle time */
166  IfxPsi5s_IdleTime_13, /**< \brief 13 bit Idle time */
167  IfxPsi5s_IdleTime_14, /**< \brief 14 bit Idle time */
168  IfxPsi5s_IdleTime_15, /**< \brief 15 bit Idle time */
169  IfxPsi5s_IdleTime_16, /**< \brief 16 bit Idle time */
171 
172 /** \brief Messaging bits presence
173  */
174 typedef enum
175 {
176  IfxPsi5s_MessagingBits_absent = 0, /**< \brief No messaging bits */
177  IfxPsi5s_MessagingBits_present = 1 /**< \brief 2 messaging bits */
179 
180 /** \brief MODULE_PSI5S.NFC.NFx:Expected Psi5s frames
181  */
182 typedef enum
183 {
184  IfxPsi5s_NumberExpectedFrames_1 = 1, /**< \brief 1 psi5s frame expected */
185  IfxPsi5s_NumberExpectedFrames_2, /**< \brief 2 psi5s frame expected */
186  IfxPsi5s_NumberExpectedFrames_3, /**< \brief 3 psi5s frame expected */
187  IfxPsi5s_NumberExpectedFrames_4, /**< \brief 4 psi5s frame expected */
188  IfxPsi5s_NumberExpectedFrames_5, /**< \brief 5 psi5s frame expected */
189  IfxPsi5s_NumberExpectedFrames_6, /**< \brief 6 psi5s frame expected */
191 
192 /** \brief MODULE_PSI5S.TSCNTA.B.TBS;MODULE_PSI5S.TSCNTB.B.TBS:Time base
193  */
194 typedef enum
195 {
196  IfxPsi5s_TimeBase_internal = 0, /**< \brief Internal time stamp clock */
197  IfxPsi5s_TimeBase_external = 1 /**< \brief External GTM inputs */
199 
200 /** \brief MODULE_PSI5S.TSCNTx(x= A,B):Timestamp register
201  */
202 typedef enum
203 {
204  IfxPsi5s_TimestampRegister_a = 0, /**< \brief Timestamp register A */
205  IfxPsi5s_TimestampRegister_b = 1 /**< \brief Timestamp register B */
207 
208 /** \brief MODULE_PSI5S.RCRAx.TSTS:Timestamp trigger
209  */
210 typedef enum
211 {
212  IfxPsi5s_TimestampTrigger_syncPulse = 0, /**< \brief Timestamp trigger on sync pulse */
213  IfxPsi5s_TimestampTrigger_frame = 1 /**< \brief Timestamp trigger on any frame */
215 
216 /** \brief MODULE_PSI5S.TSCNTA.B.ETB;MODULE_PSI5S.TSCNTB.B.ETB:Trigger Id
217  */
218 typedef enum
219 {
220  IfxPsi5s_Trigger_0 = 0, /**< \brief Trigger 0 */
221  IfxPsi5s_Trigger_1, /**< \brief Trigger 1 */
222  IfxPsi5s_Trigger_2, /**< \brief Trigger 2 */
223  IfxPsi5s_Trigger_3, /**< \brief Trigger 3 */
224  IfxPsi5s_Trigger_4, /**< \brief Trigger 4 */
225  IfxPsi5s_Trigger_5, /**< \brief Trigger 5 */
226  IfxPsi5s_Trigger_6, /**< \brief Trigger 6 */
227  IfxPsi5s_Trigger_7, /**< \brief Trigger 7 */
229 
230 /** \brief Trigger type defined in
231  */
232 typedef enum
233 {
234  IfxPsi5s_TriggerType_periodic = 0, /**< \brief Periodic trigger */
235  IfxPsi5s_TriggerType_external = 1 /**< \brief External trigger */
237 
238 /** \brief MODULE_PSI5S.RCRAx.UFCY(x=0,1,...7;y=0,1...5):UART frame count
239  */
240 typedef enum
241 {
242  IfxPsi5s_UartFrameCount_3 = 0, /**< \brief 3 UART frames */
243  IfxPsi5s_UartFrameCount_4, /**< \brief 4 UART frames */
244  IfxPsi5s_UartFrameCount_5, /**< \brief 5 UART frames */
245  IfxPsi5s_UartFrameCount_6, /**< \brief 6 UART frames */
247 
248 /** \brief MODULE_PSI5S.RCRAx.WDMS:Watchdog timer mode
249  */
250 typedef enum
251 {
252  IfxPsi5s_WatchdogTimerMode_frame = 0, /**< \brief Watch Dog Timer is restarted on reception of each recoverable frame (async mode) */
253  IfxPsi5s_WatchdogTimerMode_syncPulse = 1 /**< \brief Watch Dog Timer is restarted on Sync Pulse and stopped at reception of the last frame configured in NFC.NFx.(sync mode) */
255 
256 /** \} */
257 
258 /** \addtogroup IfxLld_Psi5s_Std_Channel
259  * \{ */
260 
261 /******************************************************************************/
262 /*-------------------------Global Function Prototypes-------------------------*/
263 /******************************************************************************/
264 
265 /** \brief Enable ASC receiver
266  * \param psi5s pointer to the PSI5S register space
267  * \return None
268  */
269 IFX_EXTERN void IfxPsi5s_enableAscReceiver(Ifx_PSI5S *psi5s);
270 
271 /** \brief Enable/disable any combination of channel trigger counters selected by mask parameter
272  * \param psi5s pointer to the PSI5S register space
273  * \param channels specifies the channel trigger counters which should be enabled/disabled
274  * \param mask specifies the channel trigger counters which should be modified
275  * \return None
276  */
277 IFX_EXTERN void IfxPsi5s_enableDisableChannelTriggerCounters(Ifx_PSI5S *psi5s, uint32 channels, uint32 mask);
278 
279 /** \brief Enable/disable any combination of channels selected by mask parameter
280  * \param psi5s pointer to the PSI5S register space
281  * \param channels specifies the channels which should be enabled/disabled
282  * \param mask specifies the channels which should be modified
283  * \return None
284  */
285 IFX_EXTERN void IfxPsi5s_enableDisableChannels(Ifx_PSI5S *psi5s, uint32 channels, uint32 mask);
286 
287 /** \brief Start ASC transactions
288  * \param psi5s pointer to the PSI5S register space
289  * \return None
290  */
291 IFX_EXTERN void IfxPsi5s_startAscTransactions(Ifx_PSI5S *psi5s);
292 
293 /** \} */
294 
295 /** \addtogroup IfxLld_Psi5s_Std_IO
296  * \{ */
297 
298 /******************************************************************************/
299 /*-------------------------Inline Function Prototypes-------------------------*/
300 /******************************************************************************/
301 
302 /** \brief Selects the alternate input for Rx signal
303  * \param psi5s pointer to PSI5S registers
304  * \param alti alternate input selection of Rx signal
305  * \return None
306  */
307 IFX_INLINE void IfxPsi5s_setRxInput(Ifx_PSI5S *psi5s, IfxPsi5s_AlternateInput alti);
308 
309 /** \brief Initializes a RX input
310  * \param rx the RX Pin which should be configured
311  * \param inputMode the pin input mode which should be configured
312  * \return None
313  */
315 
316 /** \brief Initializes a SCLK output
317  * \param sclk the SCLK Pin which should be configured
318  * \param outputMode the pin output mode which should be configured
319  * \param padDriver the pad driver mode which should be configured
320  * \return None
321  */
323 
324 /** \brief Initializes a TX output
325  * \param tx the TX Pin which should be configured
326  * \param outputMode the pin output mode which should be configured
327  * \param padDriver the pad driver mode which should be configured
328  * \return None
329  */
331 
332 /** \} */
333 
334 /******************************************************************************/
335 /*---------------------Inline Function Implementations------------------------*/
336 /******************************************************************************/
337 
339 {
340  psi5s->IOCR.B.ALTI = alti;
341 }
342 
343 
345 {
346  IfxPort_setPinModeInput(rx->pin.port, rx->pin.pinIndex, inputMode);
348 }
349 
350 
352 {
353  IfxPort_setPinModeOutput(sclk->pin.port, sclk->pin.pinIndex, outputMode, sclk->select);
354  IfxPort_setPinPadDriver(sclk->pin.port, sclk->pin.pinIndex, padDriver);
355 }
356 
357 
359 {
360  IfxPort_setPinModeOutput(tx->pin.port, tx->pin.pinIndex, outputMode, tx->select);
361  IfxPort_setPinPadDriver(tx->pin.port, tx->pin.pinIndex, padDriver);
362 }
363 
364 
365 #endif /* IFXPSI5S_H */