iLLD_TC27xC  1.0
IfxMsc_Msc.c
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1 /**
2  * \file IfxMsc_Msc.c
3  * \brief MSC MSC details
4  *
5  * \version iLLD_0_1_0_10
6  * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
7  *
8  *
9  * IMPORTANT NOTICE
10  *
11  *
12  * Infineon Technologies AG (Infineon) is supplying this file for use
13  * exclusively with Infineon's microcontroller products. This file can be freely
14  * distributed within development tools that are supporting such microcontroller
15  * products.
16  *
17  * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
18  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
19  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
20  * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
21  * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
22  *
23  */
24 
25 /******************************************************************************/
26 /*----------------------------------Includes----------------------------------*/
27 /******************************************************************************/
28 
29 #include "IfxMsc_Msc.h"
30 
31 /******************************************************************************/
32 /*-------------------------Function Implementations---------------------------*/
33 /******************************************************************************/
34 
36 {
37  IfxMsc_resetModule(msc->msc);
38 }
39 
40 
42 {
43  Ifx_MSC *mscSfr = msc->msc;
45 
46  if (target == IfxMsc_Msc_Target_low)
47  {
48  enX = IfxMsc_getDataLowTarget(mscSfr);
49  }
50  else if (target == IfxMsc_Msc_Target_high)
51  {
52  enX = IfxMsc_getDataHighTarget(mscSfr);
53  }
54 
55  return enX;
56 }
57 
58 
60 {
61  Ifx_MSC *mscSfr = config->msc;
62 
63  msc->msc = mscSfr;
64 
67 
68  /* Enable the MSCx Clock */
69  IfxMsc_enableModule(mscSfr);
70 
71  /* Configure MSC hadrware enable and set the divider mode */
72  {
73  Ifx_MSC_FDR fdr;
74 
75  /* Read the FDR register content */
76  fdr.U = mscSfr->FDR.U;
77  /* Select the divider mode */
78  fdr.B.DM = config->clockConfig.dividerMode;
79  /* Enable Hardware Clock Control */
80  fdr.B.ENHW = IfxMsc_HardwareClock_enabled;
81 
82  mscSfr->FDR.U = fdr.U;
83  }
84 
85  /* Configure Upstream Channel Data Format */
86  {
87  Ifx_MSC_USR usr;
88 
89  /* Read the USR register content */
90  usr.U = mscSfr->USR.U;
91  /* Service Request Delay Control */
92  usr.B.SRDC = config->upstreamConfig.serviceRequestDelay;
93  /* Select parity control Even - 0, Odd - 1 */
94  usr.B.PCTR = config->upstreamConfig.parity;
95  /* Select upstream baud rate fMSC/xx */
96  usr.B.URR = config->upstreamConfig.upstreamChannelReceivingRate;
97  /* Select 12 bit or 16 bit frame */
98  usr.B.UFT = config->upstreamConfig.upstreamChannelFrameType;
99 
100  mscSfr->USR.U = usr.U;
101  }
102 
103  /* Normal divider */
104  if (config->clockConfig.dividerMode == 1)
105  {
106  /* Initialize MSC BaudRate at 6.25MHz, Fsys = 100MHz */
107  mscSfr->FDR.B.STEP =
109  }
110  /* Fractional divider */
111  else
112  {
113  /* Initialize MSC BaudRate at 6.25MHz, Fsys = 100MHz */
114  mscSfr->FDR.B.STEP =
116  }
117 
118  IfxScuWdt_setCpuEndinit(passwd);
119 
120  /* Configure IOs */
121  {
122  IfxMsc_Msc_Io *io = &config->io;
123 
124  IfxMsc_Fclp_Out *fclp = io->fclp.pin;
125 
126  if (fclp != NULL_PTR)
127  {
128  IfxMsc_initFclpPin(fclp, io->fclp.mode, io->pinDriver);
129  }
130 
131  IfxMsc_Fcln_Out *fcln = io->fcln.pin;
132 
133  if (fcln != NULL_PTR)
134  {
135  IfxMsc_initFclnPin(fcln, io->fcln.mode, io->pinDriver);
136  }
137 
138  IfxMsc_Sop_Out *sop = io->sop.pin;
139 
140  if (sop != NULL_PTR)
141  {
142  IfxMsc_initSopPin(sop, io->sop.mode, io->pinDriver);
143  }
144 
145  IfxMsc_Son_Out *son = io->son.pin;
146 
147  if (son != NULL_PTR)
148  {
149  IfxMsc_initSonPin(son, io->son.mode, io->pinDriver);
150  }
151 
152  IfxMsc_En_Out *en0 = io->en0.pin;
153 
154  if (en0 != NULL_PTR)
155  {
156  IfxMsc_initEnPin(en0, io->en0.mode, io->pinDriver);
157  }
158 
159  IfxMsc_En_Out *en1 = io->en1.pin;
160 
161  if (en1 != NULL_PTR)
162  {
163  IfxMsc_initEnPin(en1, io->en1.mode, io->pinDriver);
164  }
165 
166  IfxMsc_Sdi_In *sdi = io->sdi.pin;
167 
168  if (sdi != NULL_PTR)
169  {
170  IfxMsc_initSdiPin(sdi, io->sdi.mode);
171  }
172 
173  IfxMsc_Inj_In *inj0 = io->inj0.pin;
174 
175  if (inj0 != NULL_PTR)
176  {
177  IfxMsc_initInjPin(inj0, io->inj0.mode);
178  }
179 
180  IfxMsc_Inj_In *inj1 = io->inj1.pin;
181 
182  if (inj1 != NULL_PTR)
183  {
184  IfxMsc_initInjPin(inj1, io->inj1.mode);
185  }
186  }
187 
188  /* Configure the control of upstream channel timeout feature */
189  {
190  Ifx_MSC_USCE usce;
191 
192  /* Read the USCE register content */
193  usce.U = mscSfr->USCE.U;
194  /* Upstream Timeout Value */
195  usce.B.USTOVAL = config->upstreamConfig.upstreamTimeoutValue;
196  /* Upstream Timeout Prescaler */
197  usce.B.USTOPRE = config->upstreamConfig.upstreamTimeoutPrescaler;
198  /* Upstream Timeout Interrupt */
199  usce.B.USTOIP = config->interruptConfig.upstreamTimeoutInterruptNode,
200  usce.B.USTOEN = config->interruptConfig.upstreamTimeoutInterrupt,
201 
202  mscSfr->USCE.U = usce.U;
203  }
204 
205  /* Control the operation mode and frame layout of the downstream channel transmission */
206  {
207  Ifx_MSC_DSC dsc;
208 
209  /* Read the DSC register content */
210  dsc.U = mscSfr->DSC.U;
211 
212  /* Passive Phase Length */
213  dsc.B.PPD = config->downstreamConfig.dataFramePassivePhaseLength;
214  /* Number of command bits transmitted */
215  dsc.B.NBC = config->downstreamConfig.commandFrameLength;
216  /* SRH Selection Bit */
217  dsc.B.ENSELH = config->downstreamConfig.srhActivePhaseSelection;
218  /* SRL Selection Bit */
219  dsc.B.ENSELL = config->downstreamConfig.srlActivePhaseSelection;
220  /* Number of SRH Bits transmitted */
221  dsc.B.NDBH = config->downstreamConfig.srhDataFrameLength;
222  /* Number of SRL Bits transmitted */
223  dsc.B.NDBL = config->downstreamConfig.srlDataFrameLength;
224  /* Transmission Mode - Triggered or data repetition */
225  dsc.B.TM = config->downstreamConfig.transmissionMode;
226 
227  mscSfr->DSC.U = dsc.U;
228  }
229 
230  /* Number Of Passive Time Frames */
231  mscSfr->DSS.B.NPTF = config->downstreamConfig.passiveTimeFrameCount;
232 
233  /* Select Source for SRL */
234  mscSfr->DSDSL.U = config->downstreamConfig.downstreamDataSourcesLow;
235  /* Select Source for SRH */
236  mscSfr->DSDSH.U = config->downstreamConfig.downstreamDataSourcesHigh;
237 
238  /* Emergency Stop Enable for Bits */
239  mscSfr->ESR.U = config->downstreamConfig.emergencyStopEnableBits;
240 
241  /* Interrupt configuration */
242  {
243  Ifx_MSC_ICR icr;
244 
245  icr.U = mscSfr->ICR.U;
246 
247  icr.B.EDIP = config->interruptConfig.dataFrameInterruptNode;
248  icr.B.EDIE = config->interruptConfig.dataFrameInterrupt;
249  icr.B.ECIP = config->interruptConfig.commandFrameInterruptNode;
250  icr.B.ECIE = config->interruptConfig.commandFrameInterrupt;
251  icr.B.TFIP = config->interruptConfig.timeFrameInterruptNode;
252  icr.B.TFIE = config->interruptConfig.timeFrameInterrupt;
253  icr.B.RDIP = config->interruptConfig.receiveDataInterruptNode;
254  icr.B.RDIE = config->interruptConfig.receiveDataInterrupt;
255 
256  /* additional interrupt configured in USCE */
257 
258  mscSfr->ICR.U = icr.U;
259 
260  /* ABRA */
261  Ifx_MSC_ABC abc;
262  abc.U = mscSfr->ABC.U;
263 
265  {
266  abc.B.OIP = 0;
267  abc.B.OASR = 1;
268  }
269  else
270  {
271  abc.B.OIP = config->interruptConfig.overflowInterruptNode;
272  abc.B.OASR = 0;
273  }
274 
275  abc.B.OIE = config->interruptConfig.overflowInterrupt;
276 
278  {
279  abc.B.UIP = 0;
280  abc.B.UASR = 1;
281  }
282  else
283  {
284  abc.B.UIP = config->interruptConfig.underflowInterruptNode;
285  abc.B.UASR = 0;
286  }
287 
288  abc.B.UIE = config->interruptConfig.underflowInterrupt;
289 
290  mscSfr->ABC.U = abc.U;
291  }
292 
293  /* MSC inputs/outputs signal polarities */
294  {
295  Ifx_MSC_OCR ocr;
296 
297  /* Read the OCR register content */
298  ocr.U = mscSfr->OCR.U;
299  /* FCL is activated during active phases or always */
300  ocr.B.CLKCTRL = config->outputControlConfig.fclClockControl;
301  /* SDI Line Polarity - SDI and SI */
302  ocr.B.ILP = config->outputControlConfig.sdiLinePolarity;
303  /* Chip Selection Lines Polarity - EN[0:3, ENL, ENH and ENC */
304  ocr.B.CSLP = config->outputControlConfig.cslpPolarity;
305  /* SOP Line Polarity - SOP, SON, SO */
306  ocr.B.SLP = config->outputControlConfig.sopPolarity;
307  /* FCLP Line Polarity - FCLP, FCLN and FCL */
308  ocr.B.CLP = config->outputControlConfig.fclpPolarity;
309 
310  mscSfr->OCR.U = ocr.U;
311  }
312  /* Chip Enable Selection for ENL */
313  IfxMsc_setDataLowTarget(mscSfr, config->target[0]);
314 
315  /* Chip Enable Selection for ENH */
316  IfxMsc_setDataHighTarget(mscSfr, config->target[0]);
317 
318  /* Chip Enable Selection for ENC */
320 
321  /* Configure the Injection Enable and number of SRHE, SRLE Bits transmitted and Extension Enable */
322  {
323  Ifx_MSC_DSCE dsce;
324 
325  /* Read the DSCE register content */
326  dsce.U = mscSfr->DSCE.U;
327  /* Command-Data-Command in Data Repetition Mode */
329  /* Injection Position of the Pin 1 Signal */
330  dsce.B.INJPOSP1 = config->downstreamConfig.injectionPositionPin1;
331  /* Injection Enable of the Pin 1 Signal */
332  dsce.B.INJENP1 = config->downstreamConfig.externalSignalInjectionPin1;
333  /* Injection Position of the Pin 0 Signal */
334  dsce.B.INJPOSP0 = config->downstreamConfig.injectionPositionPin0;
335  /* Injection Enable of the Pin 0 Signal */
336  dsce.B.INJENP0 = config->downstreamConfig.externalSignalInjectionPin0;
337 
338  mscSfr->DSCE.U = dsce.U;
339  }
340 
341  /* If enabled configure extension registers */
343  {
345  }
346 
347  /* If enabled, configure ABRA block */
349  {
350  IfxMsc_Msc_initializeAbra(msc, config);
351  }
352 }
353 
354 
356 {
357  const IfxMsc_Msc_Config defaultConfig = {
358  .msc = NULL_PTR,
359  .clockConfig = {
360  .baudrate = 3125000,
361  .dividerMode = IfxMsc_DividerMode_normal,
362  .step = 0
363  },
364  .upstreamConfig = {
365  .upstreamChannelFrameType = IfxMsc_UpstreamChannelFrameType_12bit,
366  .upstreamChannelReceivingRate = IfxMsc_UpstreamChannelReceivingRate_16,
367  .parity = IfxMsc_Parity_even,
368  .serviceRequestDelay = IfxMsc_ServiceRequestDelay_noDelay,
369  .upstreamTimeoutPrescaler = IfxMsc_UpstreamTimeoutPrescaler_32768,
370  .upstreamTimeoutValue = IfxMsc_UpstreamTimeoutValue_16
371  },
372  .interruptConfig = {
373  .dataFrameInterruptNode = IfxMsc_DataFrameInterruptNode_SR0,
374  .dataFrameInterrupt = IfxMsc_DataFrameInterrupt_disabled,
375  .commandFrameInterruptNode = IfxMsc_CommandFrameInterruptNode_SR0,
376  .commandFrameInterrupt = IfxMsc_CommandFrameInterrupt_disabled,
377  .timeFrameInterruptNode = IfxMsc_TimeFrameInterruptNode_SR0,
378  .timeFrameInterrupt = IfxMsc_TimeFrameInterrupt_disabled,
379  .receiveDataInterruptNode = IfxMsc_ReceiveDataInterruptNode_SR0,
380  .receiveDataInterrupt = IfxMsc_ReceiveDataInterrupt_disabled,
381  .upstreamTimeoutInterruptNode = IfxMsc_UpstreamTimeoutInterruptNode_SR0,
382  .upstreamTimeoutInterrupt = IfxMsc_UpstreamTimeoutInterrupt_disabled,
383  .overflowInterruptNode = IfxMsc_OverflowInterruptNode_SR0,
384  .overflowInterrupt = IfxMsc_OverflowInterrupt_disabled,
385  .underflowInterruptNode = IfxMsc_UnderflowInterruptNode_SR0,
386  .underflowInterrupt = IfxMsc_UnderflowInterrupt_disabled
387  },
388  .outputControlConfig = {
389  .fclpPolarity = IfxMsc_FclLinePolarity_nonInverted,
390  .sopPolarity = IfxMsc_SoLinePolarity_nonInverted,
391  .cslpPolarity = IfxMsc_ChipSelectActiveState_low,
392  .sdiLinePolarity = IfxMsc_SdiLinePolarity_likeSi,
394  },
395  .downstreamConfig = {
396  .transmissionMode = IfxMsc_TransmissionMode_triggered,
397  .srlDataFrameLength = IfxMsc_DataFrameLength_16,
398  .srhDataFrameLength = IfxMsc_DataFrameLength_16,
399  .srlActivePhaseSelection = IfxMsc_ActivePhaseSelection_none,
400  .srhActivePhaseSelection = IfxMsc_ActivePhaseSelection_none,
401  .commandFrameLength = IfxMsc_CommandFrameLength_32,
402  .dataFramePassivePhaseLength = IfxMsc_DataFramePassivePhaseLength_2,
403  .passiveTimeFrameCount = IfxMsc_PassiveTimeFrameCount_0,
404  .externalSignalInjectionPin0 = IfxMsc_ExternalSignalInjection_disabled,
405  .injectionPositionPin0 = IfxMsc_ExternalBitInjectionPosition_0,
406  .externalSignalInjectionPin1 = IfxMsc_ExternalSignalInjection_disabled,
407  .injectionPositionPin1 = IfxMsc_ExternalBitInjectionPosition_0,
408  .commandDataCommandReceptionMode = IfxMsc_CommandDataCommandRepetitionMode_disabled,
409  .downstreamDataSourcesLow = 0,
410  .downstreamDataSourcesHigh = 0,
411  .emergencyStopEnableBits = 0
412  },
413  .downstreamExtensionConfig = {
414  .extension = IfxMsc_Extension_disabled,
415  .srlBitsShiftedAtDataFramesExtension = IfxMsc_MsbBitDataExtension_notPresent,
416  .srhBitsShiftedAtDataFramesExtension = IfxMsc_MsbBitDataExtension_notPresent,
417  .downstreamExtensionDataSourcesLow = 0,
418  .downstreamExtensionDataSourcesHigh = 0,
419  .emergencyStopExtensionEnableBits = 0,
420  .dataFrameExtensionPassivePhaseLength = IfxMsc_DataFrameExtensionPassivePhaseLength_0,
421  .controlFrameExtensionPassivePhaseLength = IfxMsc_ControlFrameExtensionPassivePhaseLength_0,
422  .nDividerDownstream = IfxMsc_NDividerDownstream_1
423  },
424  .abraConfig = {
425  .abraDownstreamBlockBaudrate = 500000,
426  .lowPhaseOfShiftClock = IfxMsc_ShiftClockPhaseDuration_1,
427  .highPhaseOfShiftClock = IfxMsc_ShiftClockPhaseDuration_1,
428  .clockSelectAbra = IfxMsc_ClockSelect_fspb,
429  .nDividerAbra = IfxMsc_NDividerAbra_1,
430  .abraBlockBypass = IfxMsc_AsynchronousBlock_bypassed
431  },
432  .io = {
433  .fclp = {
434  .pin = NULL_PTR,
436  },
437  .fcln = {
438  .pin = NULL_PTR,
440  },
441  .sop = {
442  .pin = NULL_PTR,
444  },
445  .son = {
446  .pin = NULL_PTR,
448  },
449  .en0 = {
450  .pin = NULL_PTR,
452  },
453  .en1 = {
454  .pin = NULL_PTR,
456  },
457  .sdi = {
458  .pin = NULL_PTR,
460  },
461  .inj0 = {
462  .pin = NULL_PTR,
464  },
465  .inj1 = {
466  .pin = NULL_PTR,
468  },
470  }
471  };
472 
473  /* Default Configuration */
474  *config = defaultConfig;
475 
476  /* take over module pointer */
477  config->msc = msc;
478 }
479 
480 
482 {
483  Ifx_MSC *mscSfr = msc->msc;
484 
485  /* N Divider Downstream */
486  mscSfr->DSTE.B.NDD =
488 
489  /* Configure Asynchronous block */
490  {
491  Ifx_MSC_ABC abc;
492 
493  /* Read the ABC register content */
494  abc.U = mscSfr->ABC.U;
495  /* Asynchronous Block Bypass */
496  abc.B.ABB = config->abraConfig.abraBlockBypass;
497  /* Clock Select */
498  abc.B.CLKSEL = config->abraConfig.clockSelectAbra;
499  /* N Divider ABRA */
500  abc.B.NDA = config->abraConfig.nDividerAbra;
501  /* Duration of the High Phase of the Shift Clock */
502  abc.B.HIGH = config->abraConfig.highPhaseOfShiftClock;
503  /* Duration of the Low Phase of the Shift Clock */
504  abc.B.LOW = config->abraConfig.lowPhaseOfShiftClock;
505 
506  mscSfr->ABC.U = abc.U;
507  }
508 }
509 
510 
512 {
513  Ifx_MSC *mscSfr = msc->msc;
514 
515  /* Configure the number of SRHE, SRLE Bits transmitted and Extension Enable */
516  {
517  Ifx_MSC_DSCE dsce;
518 
519  /* Read the DSCE register content */
520  dsce.U = mscSfr->DSCE.U;
521  /* Extension Enable */
522  dsce.B.EXEN = config->downstreamExtensionConfig.extension;
523  /* Configure the number of SRLE Bits transmitted */
525  /* Configure the number of SRHE Bits transmitted */
527 
528  mscSfr->DSCE.U = dsce.U;
529  }
530 
531  /* Select Source for SRLE */
533 
534  /* Select Source for SRHE */
536 
537  /* Emergency Stop Enable for Bit */
539 
540  /* Passive Phase Length at Data and Control Frames Extension */
541  {
542  Ifx_MSC_DSTE dste;
543 
544  /* Read the DSTE register content */
545  dste.U = mscSfr->DSTE.U;
546  /* Passive Phase Length at Control Frames Extension */
548  /* Passive Phase Length at Data Frames Extension */
550  /* N Divider for Downstream */
551  dste.B.PPDE = config->downstreamExtensionConfig.nDividerDownstream;
552 
553  mscSfr->DSTE.U = dste.U;
554  }
555 }
556 
557 
559 {
560  Ifx_MSC *mscSfr = msc->msc;
561  uint16 data = 0;
562 
563  /* Check for valid flag */
564  if (!IfxMsc_getUpstreamValidFlag(mscSfr, upstreamIdx))
565  {
566  return -1;
567  }
568 
569  /* Clear the flag */
570  IfxMsc_clearUpstreamValidFlag(mscSfr, upstreamIdx);
571 
572  /* Read the data */
573  data = IfxMsc_getData(mscSfr, upstreamIdx);
574 
575  return data;
576 }
577 
578 
580 {
581  Ifx_MSC *mscSfr = msc->msc;
582 
583  /* Downstream command */
584  mscSfr->DC.U = command;
585 }
586 
587 
588 void IfxMsc_Msc_sendData(IfxMsc_Msc *msc, uint16 dataLow, uint16 dataHigh)
589 {
590  Ifx_MSC *mscSfr = msc->msc;
591 
592  {
593  Ifx_MSC_DD dd;
594  dd.B.DDL = dataLow;
595  dd.B.DDH = dataHigh;
596 
597  /* Downstream Data */
598  mscSfr->DD.U = dd.U;
599  }
600 
601  /* Send data */
602  mscSfr->ISC.B.SDP = 1;
603 }
604 
605 
606 void IfxMsc_Msc_sendDataExtension(IfxMsc_Msc *msc, uint32 data, uint32 dataExtension)
607 {
608  Ifx_MSC *mscSfr = msc->msc;
609 
610  /* Downstream Data (mirror) + extension */
611  mscSfr->DDE.U = dataExtension;
612  mscSfr->DDM.U = data;
613 
614  /* Send data */
615  mscSfr->ISC.B.SDP = 1;
616 }
617 
618 
620 {
621  Ifx_MSC *mscSfr = msc->msc;
622 
623  /* Downstream Data High only */
624  mscSfr->DD.B.DDH = data;
625 
626  /* Send data */
627  mscSfr->ISC.B.SDP = 1;
628 }
629 
630 
632 {
633  Ifx_MSC *mscSfr = msc->msc;
634 
635  /* Downstream Data Low only */
636  mscSfr->DD.B.DDL = data;
637 
638  /* Send data */
639  mscSfr->ISC.B.SDP = 1;
640 }
641 
642 
644 {
645  Ifx_MSC *mscSfr = msc->msc;
646 
647  IfxMsc_setCommandTarget(mscSfr, enX);
648 }
649 
650 
652 {
653  Ifx_MSC *mscSfr = msc->msc;
654 
655  /* Set data low target */
656  IfxMsc_setDataLowTarget(mscSfr, enXLow);
657  /* Set data high target */
658  IfxMsc_setDataHighTarget(mscSfr, enXHigh);
659 }