iLLD_TC27xC  1.0
Enumerations
Collaboration diagram for Enumerations:

Enumerations

enum  IfxDma_BusMasterMode {
  IfxDma_BusMasterMode_user = 0,
  IfxDma_BusMasterMode_supervisor = 1
}
 Bus Master Mode definition Definition in Ifx_DMA.MODE[4].B.MODE. More...
 
enum  IfxDma_ChannelBusPriority {
  IfxDma_ChannelBusPriority_low = 0,
  IfxDma_ChannelBusPriority_medium = 1,
  IfxDma_ChannelBusPriority_high = 2
}
 Channel Bus Priority definition. More...
 
enum  IfxDma_ChannelId {
  IfxDma_ChannelId_none = -1,
  IfxDma_ChannelId_0 = 0,
  IfxDma_ChannelId_1,
  IfxDma_ChannelId_2,
  IfxDma_ChannelId_3,
  IfxDma_ChannelId_4,
  IfxDma_ChannelId_5,
  IfxDma_ChannelId_6,
  IfxDma_ChannelId_7,
  IfxDma_ChannelId_8,
  IfxDma_ChannelId_9,
  IfxDma_ChannelId_10,
  IfxDma_ChannelId_11,
  IfxDma_ChannelId_12,
  IfxDma_ChannelId_13,
  IfxDma_ChannelId_14,
  IfxDma_ChannelId_15,
  IfxDma_ChannelId_16,
  IfxDma_ChannelId_17,
  IfxDma_ChannelId_18,
  IfxDma_ChannelId_19,
  IfxDma_ChannelId_20,
  IfxDma_ChannelId_21,
  IfxDma_ChannelId_22,
  IfxDma_ChannelId_23,
  IfxDma_ChannelId_24,
  IfxDma_ChannelId_25,
  IfxDma_ChannelId_26,
  IfxDma_ChannelId_27,
  IfxDma_ChannelId_28,
  IfxDma_ChannelId_29,
  IfxDma_ChannelId_30,
  IfxDma_ChannelId_31,
  IfxDma_ChannelId_32,
  IfxDma_ChannelId_33,
  IfxDma_ChannelId_34,
  IfxDma_ChannelId_35,
  IfxDma_ChannelId_36,
  IfxDma_ChannelId_37,
  IfxDma_ChannelId_38,
  IfxDma_ChannelId_39,
  IfxDma_ChannelId_40,
  IfxDma_ChannelId_41,
  IfxDma_ChannelId_42,
  IfxDma_ChannelId_43,
  IfxDma_ChannelId_44,
  IfxDma_ChannelId_45,
  IfxDma_ChannelId_46,
  IfxDma_ChannelId_47,
  IfxDma_ChannelId_48,
  IfxDma_ChannelId_49,
  IfxDma_ChannelId_50,
  IfxDma_ChannelId_51,
  IfxDma_ChannelId_52,
  IfxDma_ChannelId_53,
  IfxDma_ChannelId_54,
  IfxDma_ChannelId_55,
  IfxDma_ChannelId_56,
  IfxDma_ChannelId_57,
  IfxDma_ChannelId_58,
  IfxDma_ChannelId_59,
  IfxDma_ChannelId_60,
  IfxDma_ChannelId_61,
  IfxDma_ChannelId_62,
  IfxDma_ChannelId_63
}
 DMA channel resources definition. More...
 
enum  IfxDma_ChannelIncrementCircular {
  IfxDma_ChannelIncrementCircular_none = -1,
  IfxDma_ChannelIncrementCircular_1 = 0,
  IfxDma_ChannelIncrementCircular_2 = 1,
  IfxDma_ChannelIncrementCircular_4 = 2,
  IfxDma_ChannelIncrementCircular_8 = 3,
  IfxDma_ChannelIncrementCircular_16 = 4,
  IfxDma_ChannelIncrementCircular_32 = 5,
  IfxDma_ChannelIncrementCircular_64 = 6,
  IfxDma_ChannelIncrementCircular_128 = 7,
  IfxDma_ChannelIncrementCircular_256 = 8,
  IfxDma_ChannelIncrementCircular_512 = 9,
  IfxDma_ChannelIncrementCircular_1024 = 10,
  IfxDma_ChannelIncrementCircular_2048 = 11,
  IfxDma_ChannelIncrementCircular_4096 = 12,
  IfxDma_ChannelIncrementCircular_8192 = 13,
  IfxDma_ChannelIncrementCircular_16384 = 14,
  IfxDma_ChannelIncrementCircular_32768 = 15
}
 DMA circular buffer (wrap around) definition Definition in Ifx_DMA.CH[64].ADICR.B.CBLS. More...
 
enum  IfxDma_ChannelIncrementDirection {
  IfxDma_ChannelIncrementDirection_negative = 0,
  IfxDma_ChannelIncrementDirection_positive = 1
}
 DMA incrementation direction definition Definition in Ifx_DMA.CH[64].ADICR.B.INCS. More...
 
enum  IfxDma_ChannelIncrementStep {
  IfxDma_ChannelIncrementStep_1 = 0,
  IfxDma_ChannelIncrementStep_2 = 1,
  IfxDma_ChannelIncrementStep_4 = 2,
  IfxDma_ChannelIncrementStep_8 = 3,
  IfxDma_ChannelIncrementStep_16 = 4,
  IfxDma_ChannelIncrementStep_32 = 5,
  IfxDma_ChannelIncrementStep_64 = 6,
  IfxDma_ChannelIncrementStep_128 = 7
}
 DMA incrementation definition Definition in Ifx_DMA.CH[64].ADICR.B.SMF. More...
 
enum  IfxDma_ChannelInterruptControl {
  IfxDma_ChannelInterruptControl_thresholdLimitMatch = 0,
  IfxDma_ChannelInterruptControl_transferCountDecremented = 1
}
 Channel Transfer Interrupt generation mechanism. Definition in Ifx_DMA.CH[64].ADICR.B.INTCT (bit 0) More...
 
enum  IfxDma_ChannelMove {
  IfxDma_ChannelMove_1 = 0,
  IfxDma_ChannelMove_2 = 1,
  IfxDma_ChannelMove_4 = 2,
  IfxDma_ChannelMove_8 = 3,
  IfxDma_ChannelMove_16 = 4,
  IfxDma_ChannelMove_3 = 5,
  IfxDma_ChannelMove_5 = 6,
  IfxDma_ChannelMove_9 = 7
}
 DMA transfer definition Definition in Ifx_DMA.BLK0.ME.CHCR.B.BLKM and Ifx_DMA.BLK1.ME.CHCR.B.BLKM. More...
 
enum  IfxDma_ChannelMoveSize {
  IfxDma_ChannelMoveSize_8bit = 0,
  IfxDma_ChannelMoveSize_16bit = 1,
  IfxDma_ChannelMoveSize_32bit = 2,
  IfxDma_ChannelMoveSize_64bit = 3,
  IfxDma_ChannelMoveSize_128bit = 4,
  IfxDma_ChannelMoveSize_256bit = 5
}
 DMA move size definition Definition in Ifx_DMA.BLK0.ME.CHCR.B.CHDW and Ifx_DMA.BLK1.ME.CHCR.B.CHDW. More...
 
enum  IfxDma_ChannelOperationMode {
  IfxDma_ChannelOperationMode_single = 0,
  IfxDma_ChannelOperationMode_continuous = 1
}
 DMA operation mode Definition in Ifx_DMA.BLK0.ME.CHCR.B.CHMODE and Ifx_DMA.BLK1.ME.CHCR.B.CHMODE. More...
 
enum  IfxDma_ChannelPattern {
  IfxDma_ChannelPattern_0_disable = 0,
  IfxDma_ChannelPattern_0_mode1 = 1,
  IfxDma_ChannelPattern_0_mode2 = 2,
  IfxDma_ChannelPattern_0_mode3 = 3,
  IfxDma_ChannelPattern_1_disable = 4,
  IfxDma_ChannelPattern_1_mode1 = 5,
  IfxDma_ChannelPattern_1_mode2 = 6,
  IfxDma_ChannelPattern_1_mode3 = 7
}
 Pattern detection selection Definition in Ifx_DMA.BLK0.ME.CHCR.B.PATSEL and Ifx_DMA.BLK1.ME.CHCR.B.PATSEL. More...
 
enum  IfxDma_ChannelPriority {
  IfxDma_ChannelPriority_low = 0,
  IfxDma_ChannelPriority_medium = 1,
  IfxDma_ChannelPriority_high = 2
}
 Channel Priority definition. More...
 
enum  IfxDma_ChannelRequestMode {
  IfxDma_ChannelRequestMode_oneTransferPerRequest = 0,
  IfxDma_ChannelRequestMode_completeTransactionPerRequest = 1
}
 DMA request mode Definition in Ifx_DMA.BLK0.ME.CHCR.B.RROAT and Ifx_DMA.BLK1.ME.CHCR.B.RROAT. More...
 
enum  IfxDma_ChannelRequestSource {
  IfxDma_ChannelRequestSource_peripheral = 0,
  IfxDma_ChannelRequestSource_daisyChain = 1
}
 DMA request selection Definition in Ifx_DMA.BLK0.ME.CHCR.B.PRSEL and Ifx_DMA.BLK1.ME.CHCR.B.PRSEL. More...
 
enum  IfxDma_ChannelShadow {
  IfxDma_ChannelShadow_none = 0,
  IfxDma_ChannelShadow_src = 1,
  IfxDma_ChannelShadow_dst = 2,
  IfxDma_ChannelShadow_srcDirectWrite = 5,
  IfxDma_ChannelShadow_dstDirectWrite = 6,
  IfxDma_ChannelShadow_doubleSourceBufferingSwSwitch = 8,
  IfxDma_ChannelShadow_doubleSourceBufferingHwSwSwitch = 9,
  IfxDma_ChannelShadow_doubleDestinationBufferingSwSwitch = 10,
  IfxDma_ChannelShadow_doubleDestinationBufferingHwSwSwitch = 11,
  IfxDma_ChannelShadow_linkedList = 12,
  IfxDma_ChannelShadow_accumulatedLinkedList = 13,
  IfxDma_ChannelShadow_safeLinkedList = 14,
  IfxDma_ChannelShadow_conditionalLinkedList = 15
}
 shadow definition definition Definition in Ifx_DMA.CH[64].ADICR.B.SHCT More...
 
enum  IfxDma_HardwareResourcePartition {
  IfxDma_HardwareResourcePartition_0 = 0,
  IfxDma_HardwareResourcePartition_1,
  IfxDma_HardwareResourcePartition_2,
  IfxDma_HardwareResourcePartition_3
}
 
enum  IfxDma_MoveEngine {
  IfxDma_MoveEngine_0 = 0,
  IfxDma_MoveEngine_1 = 1
}
 DMA move engine definition. More...
 

Detailed Description

Enumeration Type Documentation

Bus Master Mode definition Definition in Ifx_DMA.MODE[4].B.MODE.

Enumerator
IfxDma_BusMasterMode_user 

Selected hardware resource performs Bus access in user mode.

IfxDma_BusMasterMode_supervisor 

Selected hardware resource performs Bus access in supervisor mode.

Definition at line 65 of file IfxDma.h.

Channel Bus Priority definition.

Enumerator
IfxDma_ChannelBusPriority_low 

low priority

IfxDma_ChannelBusPriority_medium 

medium priority

IfxDma_ChannelBusPriority_high 

high priority

Definition at line 73 of file IfxDma.h.

DMA channel resources definition.

Enumerator
IfxDma_ChannelId_none 

None of the Ifx_DMA Channels.

IfxDma_ChannelId_0 

Ifx_DMA Channel 0.

IfxDma_ChannelId_1 

Ifx_DMA Channel 1.

IfxDma_ChannelId_2 

Ifx_DMA Channel 2.

IfxDma_ChannelId_3 

Ifx_DMA Channel 3.

IfxDma_ChannelId_4 

Ifx_DMA Channel 4.

IfxDma_ChannelId_5 

Ifx_DMA Channel 5.

IfxDma_ChannelId_6 

Ifx_DMA Channel 6.

IfxDma_ChannelId_7 

Ifx_DMA Channel 7.

IfxDma_ChannelId_8 

Ifx_DMA Channel 8.

IfxDma_ChannelId_9 

Ifx_DMA Channel 9.

IfxDma_ChannelId_10 

Ifx_DMA Channel 10.

IfxDma_ChannelId_11 

Ifx_DMA Channel 11.

IfxDma_ChannelId_12 

Ifx_DMA Channel 12.

IfxDma_ChannelId_13 

Ifx_DMA Channel 13.

IfxDma_ChannelId_14 

Ifx_DMA Channel 14.

IfxDma_ChannelId_15 

Ifx_DMA Channel 15.

IfxDma_ChannelId_16 

Ifx_DMA Channel 16.

IfxDma_ChannelId_17 

Ifx_DMA Channel 17.

IfxDma_ChannelId_18 

Ifx_DMA Channel 18.

IfxDma_ChannelId_19 

Ifx_DMA Channel 19.

IfxDma_ChannelId_20 

Ifx_DMA Channel 20.

IfxDma_ChannelId_21 

Ifx_DMA Channel 21.

IfxDma_ChannelId_22 

Ifx_DMA Channel 22.

IfxDma_ChannelId_23 

Ifx_DMA Channel 23.

IfxDma_ChannelId_24 

Ifx_DMA Channel 24.

IfxDma_ChannelId_25 

Ifx_DMA Channel 25.

IfxDma_ChannelId_26 

Ifx_DMA Channel 26.

IfxDma_ChannelId_27 

Ifx_DMA Channel 27.

IfxDma_ChannelId_28 

Ifx_DMA Channel 28.

IfxDma_ChannelId_29 

Ifx_DMA Channel 29.

IfxDma_ChannelId_30 

Ifx_DMA Channel 30.

IfxDma_ChannelId_31 

Ifx_DMA Channel 31.

IfxDma_ChannelId_32 

Ifx_DMA Channel 32.

IfxDma_ChannelId_33 

Ifx_DMA Channel 33.

IfxDma_ChannelId_34 

Ifx_DMA Channel 34.

IfxDma_ChannelId_35 

Ifx_DMA Channel 35.

IfxDma_ChannelId_36 

Ifx_DMA Channel 36.

IfxDma_ChannelId_37 

Ifx_DMA Channel 37.

IfxDma_ChannelId_38 

Ifx_DMA Channel 38.

IfxDma_ChannelId_39 

Ifx_DMA Channel 39.

IfxDma_ChannelId_40 

Ifx_DMA Channel 40.

IfxDma_ChannelId_41 

Ifx_DMA Channel 41.

IfxDma_ChannelId_42 

Ifx_DMA Channel 42.

IfxDma_ChannelId_43 

Ifx_DMA Channel 43.

IfxDma_ChannelId_44 

Ifx_DMA Channel 44.

IfxDma_ChannelId_45 

Ifx_DMA Channel 45.

IfxDma_ChannelId_46 

Ifx_DMA Channel 46.

IfxDma_ChannelId_47 

Ifx_DMA Channel 47.

IfxDma_ChannelId_48 

Ifx_DMA Channel 48.

IfxDma_ChannelId_49 

Ifx_DMA Channel 49.

IfxDma_ChannelId_50 

Ifx_DMA Channel 50.

IfxDma_ChannelId_51 

Ifx_DMA Channel 51.

IfxDma_ChannelId_52 

Ifx_DMA Channel 52.

IfxDma_ChannelId_53 

Ifx_DMA Channel 53.

IfxDma_ChannelId_54 

Ifx_DMA Channel 54.

IfxDma_ChannelId_55 

Ifx_DMA Channel 55.

IfxDma_ChannelId_56 

Ifx_DMA Channel 56.

IfxDma_ChannelId_57 

Ifx_DMA Channel 57.

IfxDma_ChannelId_58 

Ifx_DMA Channel 58.

IfxDma_ChannelId_59 

Ifx_DMA Channel 59.

IfxDma_ChannelId_60 

Ifx_DMA Channel 60.

IfxDma_ChannelId_61 

Ifx_DMA Channel 61.

IfxDma_ChannelId_62 

Ifx_DMA Channel 62.

IfxDma_ChannelId_63 

Ifx_DMA Channel 63.

Definition at line 82 of file IfxDma.h.

DMA circular buffer (wrap around) definition Definition in Ifx_DMA.CH[64].ADICR.B.CBLS.

Enumerator
IfxDma_ChannelIncrementCircular_none 

no circular buffer operation

IfxDma_ChannelIncrementCircular_1 

circular buffer size is 1 byte

IfxDma_ChannelIncrementCircular_2 

circular buffer size is 2 byte

IfxDma_ChannelIncrementCircular_4 

circular buffer size is 4 byte

IfxDma_ChannelIncrementCircular_8 

circular buffer size is 8 byte

IfxDma_ChannelIncrementCircular_16 

circular buffer size is 16 byte

IfxDma_ChannelIncrementCircular_32 

circular buffer size is 32 byte

IfxDma_ChannelIncrementCircular_64 

circular buffer size is 64 byte

IfxDma_ChannelIncrementCircular_128 

circular buffer size is 128 byte

IfxDma_ChannelIncrementCircular_256 

circular buffer size is 256 byte

IfxDma_ChannelIncrementCircular_512 

circular buffer size is 512 byte

IfxDma_ChannelIncrementCircular_1024 

circular buffer size is 1024 byte

IfxDma_ChannelIncrementCircular_2048 

circular buffer size is 2048 byte

IfxDma_ChannelIncrementCircular_4096 

circular buffer size is 4096 byte

IfxDma_ChannelIncrementCircular_8192 

circular buffer size is 8192 byte

IfxDma_ChannelIncrementCircular_16384 

circular buffer size is 16384 byte

IfxDma_ChannelIncrementCircular_32768 

circular buffer size is 32768 byte

Definition at line 154 of file IfxDma.h.

DMA incrementation direction definition Definition in Ifx_DMA.CH[64].ADICR.B.INCS.

Enumerator
IfxDma_ChannelIncrementDirection_negative 

pointer is decremented

IfxDma_ChannelIncrementDirection_positive 

pointer is incremented

Definition at line 178 of file IfxDma.h.

DMA incrementation definition Definition in Ifx_DMA.CH[64].ADICR.B.SMF.

Enumerator
IfxDma_ChannelIncrementStep_1 

increment by 1 width

IfxDma_ChannelIncrementStep_2 

increment by 2 width

IfxDma_ChannelIncrementStep_4 

increment by 4 width

IfxDma_ChannelIncrementStep_8 

increment by 8 width

IfxDma_ChannelIncrementStep_16 

increment by 16 width

IfxDma_ChannelIncrementStep_32 

increment by 32 width

IfxDma_ChannelIncrementStep_64 

increment by 64 width

IfxDma_ChannelIncrementStep_128 

increment by 128 width

Definition at line 187 of file IfxDma.h.

Channel Transfer Interrupt generation mechanism. Definition in Ifx_DMA.CH[64].ADICR.B.INTCT (bit 0)

Enumerator
IfxDma_ChannelInterruptControl_thresholdLimitMatch 

interrupt when transfer count (TCOUNT) equals the threshold limit (IRDV)

IfxDma_ChannelInterruptControl_transferCountDecremented 

interrupt when transfer count (TCOUNT) is decremented

Definition at line 202 of file IfxDma.h.

DMA transfer definition Definition in Ifx_DMA.BLK0.ME.CHCR.B.BLKM and Ifx_DMA.BLK1.ME.CHCR.B.BLKM.

Enumerator
IfxDma_ChannelMove_1 

1 DMA move per DMA transfer

IfxDma_ChannelMove_2 

2 DMA move per DMA transfer

IfxDma_ChannelMove_4 

4 DMA move per DMA transfer

IfxDma_ChannelMove_8 

8 DMA move per DMA transfer

IfxDma_ChannelMove_16 

16 DMA move per DMA transfer

IfxDma_ChannelMove_3 

3 DMA move per DMA transfer

IfxDma_ChannelMove_5 

5 DMA move per DMA transfer

IfxDma_ChannelMove_9 

9 DMA move per DMA transfer

Definition at line 211 of file IfxDma.h.

DMA move size definition Definition in Ifx_DMA.BLK0.ME.CHCR.B.CHDW and Ifx_DMA.BLK1.ME.CHCR.B.CHDW.

Enumerator
IfxDma_ChannelMoveSize_8bit 

1 DMA move is 8 bit wide

IfxDma_ChannelMoveSize_16bit 

1 DMA move is 16 bit wide

IfxDma_ChannelMoveSize_32bit 

1 DMA move is 32 bit wide

IfxDma_ChannelMoveSize_64bit 

1 DMA move is 64 bit wide

IfxDma_ChannelMoveSize_128bit 

1 DMA move is 128 bit wide

IfxDma_ChannelMoveSize_256bit 

1 DMA move is 256 bit wide

Definition at line 226 of file IfxDma.h.

DMA operation mode Definition in Ifx_DMA.BLK0.ME.CHCR.B.CHMODE and Ifx_DMA.BLK1.ME.CHCR.B.CHMODE.

Enumerator
IfxDma_ChannelOperationMode_single 

channel disabled after transaction

IfxDma_ChannelOperationMode_continuous 

channel stays enabled after transaction

Definition at line 239 of file IfxDma.h.

Pattern detection selection Definition in Ifx_DMA.BLK0.ME.CHCR.B.PATSEL and Ifx_DMA.BLK1.ME.CHCR.B.PATSEL.

Enumerator
IfxDma_ChannelPattern_0_disable 

Pattern detect 0 disabled.

IfxDma_ChannelPattern_0_mode1 

Compare match configuration 1 : pattern compare of MExR.RD[0] to PAT0[0] masked by PAT0[2].

IfxDma_ChannelPattern_0_mode2 

Compare match configuration 2 : pattern compare of MExR.RD[0] to PAT0[1] masked by PAT0[3].

IfxDma_ChannelPattern_0_mode3 

Compare match configuration 3 : pattern compare of MExR.RD[0] to PAT0[0] masked by PAT0[2] of actual DMA read move and pattern compare of MExR.RD[0] to PAT0[1] masked by PAT0[3] of previous DMA read move.

IfxDma_ChannelPattern_1_disable 

Pattern detect 1 disabled.

IfxDma_ChannelPattern_1_mode1 

Compare match configuration 1 : pattern compare of MExR.RD[0] to PAT1[0] masked by PAT1[2].

IfxDma_ChannelPattern_1_mode2 

Compare match configuration 2 : pattern compare of MExR.RD[0] to PAT1[1] masked by PAT1[3].

IfxDma_ChannelPattern_1_mode3 

Compare match configuration 3 : pattern compare of MExR.RD[0] to PAT1[0] masked by PAT1[2] of actual DMA read move and pattern compare of MExR.RD[0] to PAT1[1] masked by PAT1[3] of previous DMA read move.

Definition at line 248 of file IfxDma.h.

Channel Priority definition.

Enumerator
IfxDma_ChannelPriority_low 

low priority

IfxDma_ChannelPriority_medium 

medium priority

IfxDma_ChannelPriority_high 

high priority

Definition at line 262 of file IfxDma.h.

DMA request mode Definition in Ifx_DMA.BLK0.ME.CHCR.B.RROAT and Ifx_DMA.BLK1.ME.CHCR.B.RROAT.

Enumerator
IfxDma_ChannelRequestMode_oneTransferPerRequest 

a request initiates a single transfer

IfxDma_ChannelRequestMode_completeTransactionPerRequest 

a request initiates a complete transaction

Definition at line 272 of file IfxDma.h.

DMA request selection Definition in Ifx_DMA.BLK0.ME.CHCR.B.PRSEL and Ifx_DMA.BLK1.ME.CHCR.B.PRSEL.

Enumerator
IfxDma_ChannelRequestSource_peripheral 

Transfer Request via Hardware Trigger.

IfxDma_ChannelRequestSource_daisyChain 

Transfer Request via next (higher priority) channel.

Definition at line 281 of file IfxDma.h.

shadow definition definition Definition in Ifx_DMA.CH[64].ADICR.B.SHCT

Enumerator
IfxDma_ChannelShadow_none 

shadow address register not used. Source and destination address register are written directly

IfxDma_ChannelShadow_src 

Shadow address register used for source address buffering. When writing to SADRmx, the address is buffered in SHADRmx and transferred to SADRmx with the start of the next DMA transaction.

IfxDma_ChannelShadow_dst 

Shadow address register used for destination address buffering. When writing to DADRmx, the address is buffered in SHADRmx and transferred to DADRmx with the start of the next DMA transaction.

IfxDma_ChannelShadow_srcDirectWrite 

Shadow address used for source buffering. When writing to SADRz, the address is buffered in SHADRz and transferred to SADRz with the start of the next DMA transaction.

IfxDma_ChannelShadow_dstDirectWrite 

Shadow address used for destination buffering. When writing to DADRz, the address is buffered in SHADRz and transferred to DADRz with the start of the next DMA transaction.

IfxDma_ChannelShadow_doubleSourceBufferingSwSwitch 

Software switch only. Shadow address used for double buffering.

IfxDma_ChannelShadow_doubleSourceBufferingHwSwSwitch 

Automatic Hardware and Software switch. Shadow address used for double buffering.

IfxDma_ChannelShadow_doubleDestinationBufferingSwSwitch 

Software switch only. Shadow address used for double buffering.

IfxDma_ChannelShadow_doubleDestinationBufferingHwSwSwitch 

Automatic Hardware and Software switch. Shadow address used for double buffering.

IfxDma_ChannelShadow_linkedList 

The DMA controller reads a DMA channel transaction control set and overwrites 8 X words in the corresponding DMARAM channel z.

IfxDma_ChannelShadow_accumulatedLinkedList 

The DMA controller reads a DMA channel transaction control set and overwrites 6 X words in the corresponding DMARAM channel z.

IfxDma_ChannelShadow_safeLinkedList 

The DMA controller reads a DMA channel transaction control set. The Linked List only proceeds with the next DMA transaction if the existing SDCRC checksum matches the expected SDCRC checksum in the loaded from the new DMA transaction control set.

IfxDma_ChannelShadow_conditionalLinkedList 

Shadow address register (MExSHADR) and source and destination address CRC register (MExSDCRC) are used as address pointers to a Linked List. The selection of the address pointer is determined by DMA channel pattern detection conditions.

Definition at line 290 of file IfxDma.h.

Enumerator
IfxDma_HardwareResourcePartition_0 

"Set of DMA channels are associated with hardware resource partition " + str(x)

IfxDma_HardwareResourcePartition_1 

"Set of DMA channels are associated with hardware resource partition " + str(x)

IfxDma_HardwareResourcePartition_2 

"Set of DMA channels are associated with hardware resource partition " + str(x)

IfxDma_HardwareResourcePartition_3 

"Set of DMA channels are associated with hardware resource partition " + str(x)

Definition at line 307 of file IfxDma.h.

DMA move engine definition.

Enumerator
IfxDma_MoveEngine_0 

first move engine

IfxDma_MoveEngine_1 

second move engine

Definition at line 317 of file IfxDma.h.