iLLD_TC27xC  1.0
Enumerations
Collaboration diagram for Enumerations:

Enumerations

enum  IfxMsc_ActivePhaseSelection {
  IfxMsc_ActivePhaseSelection_none = 0,
  IfxMsc_ActivePhaseSelection_lowLevel = 1
}
 Enable SRL/SRH Active Phase Selection Bit
Definition in Ifx_MSC.DSC.B.ENSELH and Ifx_MSC.DSC.B.ENSELL. More...
 
enum  IfxMsc_AsynchronousBlock {
  IfxMsc_AsynchronousBlock_bypassed = 0,
  IfxMsc_AsynchronousBlock_noBypassed = 1
}
 Asynchronous Block Configuration Register - Asynchronous Block Bypass
Definition in Ifx_MSC.ABC.B.ABB. More...
 
enum  IfxMsc_ChipSelectActiveState {
  IfxMsc_ChipSelectActiveState_high = 0,
  IfxMsc_ChipSelectActiveState_low = 1
}
 Output Control Register - Chip Selection Line Polarity
Definition in Ifx_MSC.OCR.B.CSLP. More...
 
enum  IfxMsc_ClockSelect {
  IfxMsc_ClockSelect_noClock = 0,
  IfxMsc_ClockSelect_fspb = 1,
  IfxMsc_ClockSelect_fsri = 2,
  IfxMsc_ClockSelect_feray = 4
}
 Asynchronous Block Configuration Register - Clock Select
Definition in Ifx_MSC.ABC.B.CLKSEL. More...
 
enum  IfxMsc_CommandDataCommandRepetitionMode {
  IfxMsc_CommandDataCommandRepetitionMode_disabled = 0,
  IfxMsc_CommandDataCommandRepetitionMode_enabled = 1
}
 Downstream Control Enhanced Register - Command-Data-Command in Data Repetition Mode
Definition in Ifx_MSC.DSCE.B.CDCM. More...
 
enum  IfxMsc_CommandFrameInterrupt {
  IfxMsc_CommandFrameInterrupt_disabled = 0,
  IfxMsc_CommandFrameInterrupt_enabled = 1
}
 Interrupt Control Register - Command Frame Interrupt Enable
Definition in Ifx_MSC.ICR.B.ECIE. More...
 
enum  IfxMsc_CommandFrameInterruptNode {
  IfxMsc_CommandFrameInterruptNode_SR0 = 0,
  IfxMsc_CommandFrameInterruptNode_SR1,
  IfxMsc_CommandFrameInterruptNode_SR2,
  IfxMsc_CommandFrameInterruptNode_SR3
}
 Interrupt Control Register - Command Frame Interrupt Node Pointer
Definition in Ifx_MSC.ICR.B.ECIP. More...
 
enum  IfxMsc_CommandFrameLength {
  IfxMsc_CommandFrameLength_0 = 0,
  IfxMsc_CommandFrameLength_1 = 1,
  IfxMsc_CommandFrameLength_2 = 2,
  IfxMsc_CommandFrameLength_3,
  IfxMsc_CommandFrameLength_4,
  IfxMsc_CommandFrameLength_5,
  IfxMsc_CommandFrameLength_6,
  IfxMsc_CommandFrameLength_7,
  IfxMsc_CommandFrameLength_8,
  IfxMsc_CommandFrameLength_9,
  IfxMsc_CommandFrameLength_10,
  IfxMsc_CommandFrameLength_11,
  IfxMsc_CommandFrameLength_12,
  IfxMsc_CommandFrameLength_13,
  IfxMsc_CommandFrameLength_14,
  IfxMsc_CommandFrameLength_15,
  IfxMsc_CommandFrameLength_16,
  IfxMsc_CommandFrameLength_17 = 17,
  IfxMsc_CommandFrameLength_18 = 18,
  IfxMsc_CommandFrameLength_19,
  IfxMsc_CommandFrameLength_20,
  IfxMsc_CommandFrameLength_21,
  IfxMsc_CommandFrameLength_22,
  IfxMsc_CommandFrameLength_23,
  IfxMsc_CommandFrameLength_24,
  IfxMsc_CommandFrameLength_25,
  IfxMsc_CommandFrameLength_26,
  IfxMsc_CommandFrameLength_27,
  IfxMsc_CommandFrameLength_28,
  IfxMsc_CommandFrameLength_29,
  IfxMsc_CommandFrameLength_30,
  IfxMsc_CommandFrameLength_31,
  IfxMsc_CommandFrameLength_32
}
 Number of Bits shifted at command frames
Definition in Ifx_MSC.DSC.B.NBC. More...
 
enum  IfxMsc_ControlFrameExtensionPassivePhaseLength {
  IfxMsc_ControlFrameExtensionPassivePhaseLength_0 = 0,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_1,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_2,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_3,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_4,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_5,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_6,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_7,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_8,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_9,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_10,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_11,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_12,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_13,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_14,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_15,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_16,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_17,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_18,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_19,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_20,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_21,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_22,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_23,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_24,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_25,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_26,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_27,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_28,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_29,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_30,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_31,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_32,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_33,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_34,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_35,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_36,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_37,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_38,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_39,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_40,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_41,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_42,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_43,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_44,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_45,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_46,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_47,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_48,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_49,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_50,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_51,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_52,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_53,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_54,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_55,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_56,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_57,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_58,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_59,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_60,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_61,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_62,
  IfxMsc_ControlFrameExtensionPassivePhaseLength_63
}
 Downstream Timing Extension Register - Passive Phase Length at Control Frames Extension
Definition in Ifx_MSC.DSTE.B.PPCE. More...
 
enum  IfxMsc_DataFrameExtensionPassivePhaseLength {
  IfxMsc_DataFrameExtensionPassivePhaseLength_0 = 0,
  IfxMsc_DataFrameExtensionPassivePhaseLength_1,
  IfxMsc_DataFrameExtensionPassivePhaseLength_2,
  IfxMsc_DataFrameExtensionPassivePhaseLength_3
}
 Downstream Timing Extension Register - Passive Phase Length at Data Frames Extension
Definition in Ifx_MSC.DSTE.B.PPDE. More...
 
enum  IfxMsc_DataFrameInterrupt {
  IfxMsc_DataFrameInterrupt_disabled = 0,
  IfxMsc_DataFrameInterrupt_atLastDataBit = 1,
  IfxMsc_DataFrameInterrupt_atFirstDataBit = 2
}
 Interrupt Control Register - Data Frame Interrupt Enable
Definition in Ifx_MSC.ICR.B.EDIE. More...
 
enum  IfxMsc_DataFrameInterruptNode {
  IfxMsc_DataFrameInterruptNode_SR0 = 0,
  IfxMsc_DataFrameInterruptNode_SR1,
  IfxMsc_DataFrameInterruptNode_SR2,
  IfxMsc_DataFrameInterruptNode_SR3
}
 Interrupt Control Register - Data Frame Interrupt Node Pointer
Definition in Ifx_MSC.ICR.B.EDIP. More...
 
enum  IfxMsc_DataFrameLength {
  IfxMsc_DataFrameLength_0 = 0,
  IfxMsc_DataFrameLength_1 = 1,
  IfxMsc_DataFrameLength_2 = 2,
  IfxMsc_DataFrameLength_3,
  IfxMsc_DataFrameLength_4,
  IfxMsc_DataFrameLength_5,
  IfxMsc_DataFrameLength_6,
  IfxMsc_DataFrameLength_7,
  IfxMsc_DataFrameLength_8,
  IfxMsc_DataFrameLength_9,
  IfxMsc_DataFrameLength_10,
  IfxMsc_DataFrameLength_11,
  IfxMsc_DataFrameLength_12,
  IfxMsc_DataFrameLength_13,
  IfxMsc_DataFrameLength_14,
  IfxMsc_DataFrameLength_15,
  IfxMsc_DataFrameLength_16
}
 Number of SRx[] (x->SRL/SRH) Bits Shifted at Data Frames
Definition in Ifx_MSC.DSC.B.NDBH and Ifx_MSC.DSC.B.NDBL. More...
 
enum  IfxMsc_DataFramePassivePhaseLength {
  IfxMsc_DataFramePassivePhaseLength_2 = 2,
  IfxMsc_DataFramePassivePhaseLength_3,
  IfxMsc_DataFramePassivePhaseLength_4,
  IfxMsc_DataFramePassivePhaseLength_5,
  IfxMsc_DataFramePassivePhaseLength_6,
  IfxMsc_DataFramePassivePhaseLength_7,
  IfxMsc_DataFramePassivePhaseLength_8,
  IfxMsc_DataFramePassivePhaseLength_9,
  IfxMsc_DataFramePassivePhaseLength_10,
  IfxMsc_DataFramePassivePhaseLength_11,
  IfxMsc_DataFramePassivePhaseLength_12,
  IfxMsc_DataFramePassivePhaseLength_13,
  IfxMsc_DataFramePassivePhaseLength_14,
  IfxMsc_DataFramePassivePhaseLength_15,
  IfxMsc_DataFramePassivePhaseLength_16,
  IfxMsc_DataFramePassivePhaseLength_17,
  IfxMsc_DataFramePassivePhaseLength_18,
  IfxMsc_DataFramePassivePhaseLength_19,
  IfxMsc_DataFramePassivePhaseLength_20,
  IfxMsc_DataFramePassivePhaseLength_21,
  IfxMsc_DataFramePassivePhaseLength_22,
  IfxMsc_DataFramePassivePhaseLength_23,
  IfxMsc_DataFramePassivePhaseLength_24,
  IfxMsc_DataFramePassivePhaseLength_25,
  IfxMsc_DataFramePassivePhaseLength_26,
  IfxMsc_DataFramePassivePhaseLength_27,
  IfxMsc_DataFramePassivePhaseLength_28,
  IfxMsc_DataFramePassivePhaseLength_29,
  IfxMsc_DataFramePassivePhaseLength_30,
  IfxMsc_DataFramePassivePhaseLength_31,
  IfxMsc_DataFramePassivePhaseLength_32
}
 Passive Phase Length at Data Frames
Definition in Ifx_MSC.DSC.B.PPD. More...
 
enum  IfxMsc_DividerMode {
  IfxMsc_DividerMode_normal = 1,
  IfxMsc_DividerMode_fractional = 2
}
 Divider mode. More...
 
enum  IfxMsc_EmergencyStop {
  IfxMsc_EmergencyStop_disabled = 0,
  IfxMsc_EmergencyStop_enabled = 1
}
 Emergency Stop Register - Emergency stop feature Enable or Disable - SRL and SRH
Definition in Ifx_MSC.ESR. More...
 
enum  IfxMsc_Extension {
  IfxMsc_Extension_disabled = 0,
  IfxMsc_Extension_enabled = 1
}
 Downstream Control Enhanced Register - Extension Enable
Definition in Ifx_MSC.DSCE.B.NDBLE. More...
 
enum  IfxMsc_ExternalBitInjectionPosition {
  IfxMsc_ExternalBitInjectionPosition_0 = 0,
  IfxMsc_ExternalBitInjectionPosition_1,
  IfxMsc_ExternalBitInjectionPosition_2,
  IfxMsc_ExternalBitInjectionPosition_3,
  IfxMsc_ExternalBitInjectionPosition_4,
  IfxMsc_ExternalBitInjectionPosition_5,
  IfxMsc_ExternalBitInjectionPosition_6,
  IfxMsc_ExternalBitInjectionPosition_7,
  IfxMsc_ExternalBitInjectionPosition_8,
  IfxMsc_ExternalBitInjectionPosition_9,
  IfxMsc_ExternalBitInjectionPosition_10,
  IfxMsc_ExternalBitInjectionPosition_11,
  IfxMsc_ExternalBitInjectionPosition_12,
  IfxMsc_ExternalBitInjectionPosition_13,
  IfxMsc_ExternalBitInjectionPosition_14,
  IfxMsc_ExternalBitInjectionPosition_15,
  IfxMsc_ExternalBitInjectionPosition_16,
  IfxMsc_ExternalBitInjectionPosition_17,
  IfxMsc_ExternalBitInjectionPosition_18,
  IfxMsc_ExternalBitInjectionPosition_19,
  IfxMsc_ExternalBitInjectionPosition_20,
  IfxMsc_ExternalBitInjectionPosition_21,
  IfxMsc_ExternalBitInjectionPosition_22,
  IfxMsc_ExternalBitInjectionPosition_23,
  IfxMsc_ExternalBitInjectionPosition_24,
  IfxMsc_ExternalBitInjectionPosition_25,
  IfxMsc_ExternalBitInjectionPosition_26,
  IfxMsc_ExternalBitInjectionPosition_27,
  IfxMsc_ExternalBitInjectionPosition_28,
  IfxMsc_ExternalBitInjectionPosition_29,
  IfxMsc_ExternalBitInjectionPosition_30,
  IfxMsc_ExternalBitInjectionPosition_31,
  IfxMsc_ExternalBitInjectionPosition_32,
  IfxMsc_ExternalBitInjectionPosition_33,
  IfxMsc_ExternalBitInjectionPosition_34,
  IfxMsc_ExternalBitInjectionPosition_35,
  IfxMsc_ExternalBitInjectionPosition_36,
  IfxMsc_ExternalBitInjectionPosition_37,
  IfxMsc_ExternalBitInjectionPosition_38,
  IfxMsc_ExternalBitInjectionPosition_39,
  IfxMsc_ExternalBitInjectionPosition_40,
  IfxMsc_ExternalBitInjectionPosition_41,
  IfxMsc_ExternalBitInjectionPosition_42,
  IfxMsc_ExternalBitInjectionPosition_43,
  IfxMsc_ExternalBitInjectionPosition_44,
  IfxMsc_ExternalBitInjectionPosition_45,
  IfxMsc_ExternalBitInjectionPosition_46,
  IfxMsc_ExternalBitInjectionPosition_47,
  IfxMsc_ExternalBitInjectionPosition_48,
  IfxMsc_ExternalBitInjectionPosition_49,
  IfxMsc_ExternalBitInjectionPosition_50,
  IfxMsc_ExternalBitInjectionPosition_51,
  IfxMsc_ExternalBitInjectionPosition_52,
  IfxMsc_ExternalBitInjectionPosition_53,
  IfxMsc_ExternalBitInjectionPosition_54,
  IfxMsc_ExternalBitInjectionPosition_55,
  IfxMsc_ExternalBitInjectionPosition_56,
  IfxMsc_ExternalBitInjectionPosition_57,
  IfxMsc_ExternalBitInjectionPosition_58,
  IfxMsc_ExternalBitInjectionPosition_59,
  IfxMsc_ExternalBitInjectionPosition_60,
  IfxMsc_ExternalBitInjectionPosition_61,
  IfxMsc_ExternalBitInjectionPosition_62,
  IfxMsc_ExternalBitInjectionPosition_63
}
 Downstream Control Enhanced Register - Injection Position of the Pin 0 and 1 Signal
Definition in Ifx_MSC.DSCE.B.INJPOSP0 and Ifx_MSC.DSCE.B.INJPOSP1. More...
 
enum  IfxMsc_ExternalSignalInjection {
  IfxMsc_ExternalSignalInjection_disabled = 0,
  IfxMsc_ExternalSignalInjection_enabled = 1
}
 Downstream Control Enhanced Register - Injection Enable of the Pin 0 and 1 Signal
Definition in Ifx_MSC.DSCE.B.INJENP0 and Ifx_MSC.DSCE.B.INJENP1. More...
 
enum  IfxMsc_FclClockControlEnabled {
  IfxMsc_FclClockControlEnabled_activePhaseOnly = 0,
  IfxMsc_FclClockControlEnabled_always = 1
}
 Output Control Register - Clock Control
Definition in Ifx_MSC.OCR.B.CLKCTRL. More...
 
enum  IfxMsc_FclLinePolarity {
  IfxMsc_FclLinePolarity_nonInverted = 0,
  IfxMsc_FclLinePolarity_inverted = 1
}
 Output Control Register - FCLP Line Polarity
Definition in Ifx_MSC.OCR.B.CLP. More...
 
enum  IfxMsc_HardwareClock {
  IfxMsc_HardwareClock_disabled = 0,
  IfxMsc_HardwareClock_enabled = 1
}
 Enable hardware clock control. More...
 
enum  IfxMsc_ModuleSuspendRequestBit {
  IfxMsc_ModuleSuspendRequestBit_noSuspend = 0,
  IfxMsc_ModuleSuspendRequestBit_hardSuspend = 1,
  IfxMsc_ModuleSuspendRequestBit_softSuspend = 2
}
 OCDS Control and Status - OCDS Suspend Control Definition in Ifx_MSC.OCS.B.SUS. More...
 
enum  IfxMsc_MsbBitDataExtension {
  IfxMsc_MsbBitDataExtension_notPresent = 0,
  IfxMsc_MsbBitDataExtension_present = 1
}
 Downstream Control Enhanced Register - Number of SRL/SRH Bits Shifted at Data Frames Extension (NDBL/NDBH)
Definition in Ifx_MSC.DSCE.B.NDBLE and Ifx_MSC.DSCE.B.NDBHE. More...
 
enum  IfxMsc_NDividerAbra {
  IfxMsc_NDividerAbra_1 = 0,
  IfxMsc_NDividerAbra_2,
  IfxMsc_NDividerAbra_3,
  IfxMsc_NDividerAbra_4,
  IfxMsc_NDividerAbra_5,
  IfxMsc_NDividerAbra_6,
  IfxMsc_NDividerAbra_7,
  IfxMsc_NDividerAbra_8
}
 Asynchronous Block Configuration Register - N Divider ABRA
Definition in Ifx_MSC.ABC.B.NDA. More...
 
enum  IfxMsc_NDividerDownstream {
  IfxMsc_NDividerDownstream_1 = 0,
  IfxMsc_NDividerDownstream_2,
  IfxMsc_NDividerDownstream_3,
  IfxMsc_NDividerDownstream_4,
  IfxMsc_NDividerDownstream_5,
  IfxMsc_NDividerDownstream_6,
  IfxMsc_NDividerDownstream_7,
  IfxMsc_NDividerDownstream_8,
  IfxMsc_NDividerDownstream_9,
  IfxMsc_NDividerDownstream_10,
  IfxMsc_NDividerDownstream_11,
  IfxMsc_NDividerDownstream_12,
  IfxMsc_NDividerDownstream_13,
  IfxMsc_NDividerDownstream_14,
  IfxMsc_NDividerDownstream_15,
  IfxMsc_NDividerDownstream_16
}
 Downstream Timing Extension Register - N Divider Downstream
Definition in Ifx_MSC.DSTE.B.NDD. More...
 
enum  IfxMsc_OverflowInterrupt {
  IfxMsc_OverflowInterrupt_disabled = 0,
  IfxMsc_OverflowInterrupt_enabled = 1
}
 Asynchronous Block Configuration Register - Overflow Interrupt Enable
Definition in Ifx_MSC.ABC.B.OIE. More...
 
enum  IfxMsc_OverflowInterruptNode {
  IfxMsc_OverflowInterruptNode_SR0 = 0,
  IfxMsc_OverflowInterruptNode_SR1,
  IfxMsc_OverflowInterruptNode_SR2,
  IfxMsc_OverflowInterruptNode_SR3,
  IfxMsc_OverflowInterruptNode_SR4
}
 Asynchronous Block Configuration Register - Overflow Interrupt Node Pointer
Definition in Ifx_MSC.ABC.B.OIP. More...
 
enum  IfxMsc_Parity {
  IfxMsc_Parity_even = 0,
  IfxMsc_Parity_odd = 1
}
 Parity Mode
Definition in Ifx_MSC.USR.B.PCT. More...
 
enum  IfxMsc_PassiveTimeFrameCount {
  IfxMsc_PassiveTimeFrameCount_0 = 0,
  IfxMsc_PassiveTimeFrameCount_1 = 1,
  IfxMsc_PassiveTimeFrameCount_2,
  IfxMsc_PassiveTimeFrameCount_3,
  IfxMsc_PassiveTimeFrameCount_4,
  IfxMsc_PassiveTimeFrameCount_5,
  IfxMsc_PassiveTimeFrameCount_6,
  IfxMsc_PassiveTimeFrameCount_7,
  IfxMsc_PassiveTimeFrameCount_8,
  IfxMsc_PassiveTimeFrameCount_9,
  IfxMsc_PassiveTimeFrameCount_10,
  IfxMsc_PassiveTimeFrameCount_11,
  IfxMsc_PassiveTimeFrameCount_12,
  IfxMsc_PassiveTimeFrameCount_13,
  IfxMsc_PassiveTimeFrameCount_14,
  IfxMsc_PassiveTimeFrameCount_15
}
 Downstream Status Register - Number Of Passive Time Frames
Definition in Ifx_MSC.DSS.B.NPTF. More...
 
enum  IfxMsc_ReceiveDataInterrupt {
  IfxMsc_ReceiveDataInterrupt_disabled = 0,
  IfxMsc_ReceiveDataInterrupt_onDataReceive = 1,
  IfxMsc_ReceiveDataInterrupt_onRdieSet = 2,
  IfxMsc_ReceiveDataInterrupt_onDataReceiveInUd3 = 3
}
 Interrupt Control Register - Receive Data Interrupt Enable
Definition in Ifx_MSC.ICR.B.RDIE. More...
 
enum  IfxMsc_ReceiveDataInterruptNode {
  IfxMsc_ReceiveDataInterruptNode_SR0 = 0,
  IfxMsc_ReceiveDataInterruptNode_SR1,
  IfxMsc_ReceiveDataInterruptNode_SR2,
  IfxMsc_ReceiveDataInterruptNode_SR3
}
 Interrupt Control Register - Receive Data Interrupt Pointer
Definition in Ifx_MSC.ICR.B.RDIP. More...
 
enum  IfxMsc_SdiLinePolarity {
  IfxMsc_SdiLinePolarity_likeSi = 0,
  IfxMsc_SdiLinePolarity_invertedSi = 1
}
 Output Control Register - SDI Line Polarity
Definition in Ifx_MSC.OCR.B.ILP. More...
 
enum  IfxMsc_SerialDataInput {
  IfxMsc_SerialDataInput_0 = 0,
  IfxMsc_SerialDataInput_1,
  IfxMsc_SerialDataInput_2,
  IfxMsc_SerialDataInput_3,
  IfxMsc_SerialDataInput_4,
  IfxMsc_SerialDataInput_5,
  IfxMsc_SerialDataInput_6,
  IfxMsc_SerialDataInput_7
}
 Output Control Register - Serial Data Input Selection
Definition in Ifx_MSC.OCR.B.SDISEL. More...
 
enum  IfxMsc_ServiceRequestDelay {
  IfxMsc_ServiceRequestDelay_noDelay = 0,
  IfxMsc_ServiceRequestDelay_1bit = 1
}
 Service Request Delay
Definition in Ifx_MSC.USR.B.SRDC. More...
 
enum  IfxMsc_ShiftClockPhaseDuration {
  IfxMsc_ShiftClockPhaseDuration_1 = 0,
  IfxMsc_ShiftClockPhaseDuration_2,
  IfxMsc_ShiftClockPhaseDuration_3,
  IfxMsc_ShiftClockPhaseDuration_4,
  IfxMsc_ShiftClockPhaseDuration_5,
  IfxMsc_ShiftClockPhaseDuration_6,
  IfxMsc_ShiftClockPhaseDuration_7,
  IfxMsc_ShiftClockPhaseDuration_8,
  IfxMsc_ShiftClockPhaseDuration_9,
  IfxMsc_ShiftClockPhaseDuration_10,
  IfxMsc_ShiftClockPhaseDuration_11,
  IfxMsc_ShiftClockPhaseDuration_12,
  IfxMsc_ShiftClockPhaseDuration_13,
  IfxMsc_ShiftClockPhaseDuration_14,
  IfxMsc_ShiftClockPhaseDuration_15,
  IfxMsc_ShiftClockPhaseDuration_16
}
 Asynchronous Block Configuration Register - Duration of the Low/High Phase of the Shift Clock
Definition in Ifx_MSC.ABC.B.LOW and Ifx_MSC.ABC.B.HIGH. More...
 
enum  IfxMsc_SleepMode {
  IfxMsc_SleepMode_disabled = 0,
  IfxMsc_SleepMode_enabled = 1
}
 Clock Control Register - Sleep Mode Enable Control Definition in Ifx_MSC.CLC.B.EDIS. More...
 
enum  IfxMsc_SoLinePolarity {
  IfxMsc_SoLinePolarity_nonInverted = 0,
  IfxMsc_SoLinePolarity_inverted = 1
}
 Output Control Register - SOP Line Polarity
Definition in Ifx_MSC.OCR.B.SLP. More...
 
enum  IfxMsc_Source {
  IfxMsc_Source_downstreamDataRegister = 0,
  IfxMsc_Source_alternateInputLine = 2,
  IfxMsc_Source_alternateInputLineInverted = 3
}
 Downstream Select Data Source Low Register - Select Source for - SRL and SRHNumber Of Passive Time Frames
Definition in Ifx_MSC.DSDSL and Ifx_MSC.DSDSH. More...
 
enum  IfxMsc_Target {
  IfxMsc_Target_en0 = 0,
  IfxMsc_Target_en1,
  IfxMsc_Target_en2,
  IfxMsc_Target_en3
}
 Msc Targets - use as chip enable selection for ENH, ENL and ENC. More...
 
enum  IfxMsc_TimeFrameInterrupt {
  IfxMsc_TimeFrameInterrupt_disabled = 0,
  IfxMsc_TimeFrameInterrupt_enabled = 1
}
 Interrupt Control Register - Time Frame Interrupt Enable
Definition in Ifx_MSC.ICR.B.TFIE. More...
 
enum  IfxMsc_TimeFrameInterruptNode {
  IfxMsc_TimeFrameInterruptNode_SR0 = 0,
  IfxMsc_TimeFrameInterruptNode_SR1,
  IfxMsc_TimeFrameInterruptNode_SR2,
  IfxMsc_TimeFrameInterruptNode_SR3
}
 Interrupt Control Register - Time Frame Interrupt Pointer
Definition in Ifx_MSC.ICR.B.TFIP. More...
 
enum  IfxMsc_TransmissionMode {
  IfxMsc_TransmissionMode_triggered = 0,
  IfxMsc_TransmissionMode_dataRepetition = 1
}
 Downstream Channel Transmission Mode
Definition in Ifx_MSC.DSC.B.TM. More...
 
enum  IfxMsc_UnderflowInterrupt {
  IfxMsc_UnderflowInterrupt_disabled = 0,
  IfxMsc_UnderflowInterrupt_enabled = 1
}
 Asynchronous Block Configuration Register - Underflow Interrupt Enable
Definition in Ifx_MSC.ABC.B.UIE. More...
 
enum  IfxMsc_UnderflowInterruptNode {
  IfxMsc_UnderflowInterruptNode_SR0 = 0,
  IfxMsc_UnderflowInterruptNode_SR1,
  IfxMsc_UnderflowInterruptNode_SR2,
  IfxMsc_UnderflowInterruptNode_SR3,
  IfxMsc_UnderflowInterruptNode_SR4
}
 Asynchronous Block Configuration Register - Underflow Interrupt Node Pointer
Definition in Ifx_MSC.ABC.B.UIP. More...
 
enum  IfxMsc_UpstreamChannelFrameType {
  IfxMsc_UpstreamChannelFrameType_12bit = 0,
  IfxMsc_UpstreamChannelFrameType_16bit = 1
}
 Channel Frame Type
Definition in Ifx_MSC.USR.B.UFT. More...
 
enum  IfxMsc_UpstreamChannelReceivingRate {
  IfxMsc_UpstreamChannelReceivingRate_disabled = 0,
  IfxMsc_UpstreamChannelReceivingRate_4 = 1,
  IfxMsc_UpstreamChannelReceivingRate_8 = 2,
  IfxMsc_UpstreamChannelReceivingRate_16 = 3,
  IfxMsc_UpstreamChannelReceivingRate_32 = 4,
  IfxMsc_UpstreamChannelReceivingRate_64 = 5,
  IfxMsc_UpstreamChannelReceivingRate_128 = 6,
  IfxMsc_UpstreamChannelReceivingRate_256 = 7
}
 Upstream Receiving Rate
Definition in Ifx_MSC.USR.B.URR. More...
 
enum  IfxMsc_UpstreamTimeoutInterrupt {
  IfxMsc_UpstreamTimeoutInterrupt_disabled = 0,
  IfxMsc_UpstreamTimeoutInterrupt_enabled = 1
}
 Upstream Control Enhanced Register 1 - Upstream Timeout Interrupt Enable
Definition in Ifx_MSC.USCE.B.USTOEN. More...
 
enum  IfxMsc_UpstreamTimeoutInterruptNode {
  IfxMsc_UpstreamTimeoutInterruptNode_SR0 = 0,
  IfxMsc_UpstreamTimeoutInterruptNode_SR1,
  IfxMsc_UpstreamTimeoutInterruptNode_SR2,
  IfxMsc_UpstreamTimeoutInterruptNode_SR3
}
 Upstream Control Enhanced Register 1 - Upstream Timeout Interrupt Node Pointer
Definition in Ifx_MSC.USCE.B.USTOIP. More...
 
enum  IfxMsc_UpstreamTimeoutPrescaler {
  IfxMsc_UpstreamTimeoutPrescaler_1 = 0,
  IfxMsc_UpstreamTimeoutPrescaler_2 = 1,
  IfxMsc_UpstreamTimeoutPrescaler_4 = 2,
  IfxMsc_UpstreamTimeoutPrescaler_8 = 3,
  IfxMsc_UpstreamTimeoutPrescaler_16 = 4,
  IfxMsc_UpstreamTimeoutPrescaler_32 = 5,
  IfxMsc_UpstreamTimeoutPrescaler_64 = 6,
  IfxMsc_UpstreamTimeoutPrescaler_128 = 7,
  IfxMsc_UpstreamTimeoutPrescaler_256 = 8,
  IfxMsc_UpstreamTimeoutPrescaler_512 = 9,
  IfxMsc_UpstreamTimeoutPrescaler_1024 = 10,
  IfxMsc_UpstreamTimeoutPrescaler_2048 = 11,
  IfxMsc_UpstreamTimeoutPrescaler_4096 = 12,
  IfxMsc_UpstreamTimeoutPrescaler_8192 = 13,
  IfxMsc_UpstreamTimeoutPrescaler_16384 = 14,
  IfxMsc_UpstreamTimeoutPrescaler_32768 = 15
}
 Upstream Control Enhanced Register 1 - Upstream Timeout Prescaler
Definition in Ifx_MSC.USCE.B.USTOPRE. More...
 
enum  IfxMsc_UpstreamTimeoutValue {
  IfxMsc_UpstreamTimeoutValue_1 = 0,
  IfxMsc_UpstreamTimeoutValue_2,
  IfxMsc_UpstreamTimeoutValue_3,
  IfxMsc_UpstreamTimeoutValue_4,
  IfxMsc_UpstreamTimeoutValue_5,
  IfxMsc_UpstreamTimeoutValue_6,
  IfxMsc_UpstreamTimeoutValue_7,
  IfxMsc_UpstreamTimeoutValue_8,
  IfxMsc_UpstreamTimeoutValue_9,
  IfxMsc_UpstreamTimeoutValue_10,
  IfxMsc_UpstreamTimeoutValue_11,
  IfxMsc_UpstreamTimeoutValue_12,
  IfxMsc_UpstreamTimeoutValue_13,
  IfxMsc_UpstreamTimeoutValue_14,
  IfxMsc_UpstreamTimeoutValue_15,
  IfxMsc_UpstreamTimeoutValue_16
}
 Upstream Control Enhanced Register 1 - Upstream Timeout Value
Definition in Ifx_MSC.USCE.B.USTOVAL. More...
 

Detailed Description

Enumeration Type Documentation

Enable SRL/SRH Active Phase Selection Bit
Definition in Ifx_MSC.DSC.B.ENSELH and Ifx_MSC.DSC.B.ENSELL.

Enumerator
IfxMsc_ActivePhaseSelection_none 

No selection bit inserted.

IfxMsc_ActivePhaseSelection_lowLevel 

Low level selection bit inserted.

Definition at line 69 of file IfxMsc.h.

Asynchronous Block Configuration Register - Asynchronous Block Bypass
Definition in Ifx_MSC.ABC.B.ABB.

Enumerator
IfxMsc_AsynchronousBlock_bypassed 

Asynchronous block and the n-divider of the MSC downstream path are bypassed and are disabled.

IfxMsc_AsynchronousBlock_noBypassed 

Asynchronous block and the n-divider of the MSC downstream path are active.

Definition at line 78 of file IfxMsc.h.

Output Control Register - Chip Selection Line Polarity
Definition in Ifx_MSC.OCR.B.CSLP.

Enumerator
IfxMsc_ChipSelectActiveState_high 

EN[3:0] and ENL,ENH,ENC polarities are identical.

IfxMsc_ChipSelectActiveState_low 

EN[3:0] and ENL,ENH,ENC polarities are inverted.

Definition at line 87 of file IfxMsc.h.

Asynchronous Block Configuration Register - Clock Select
Definition in Ifx_MSC.ABC.B.CLKSEL.

Enumerator
IfxMsc_ClockSelect_noClock 

no clock source for the ABRA block

IfxMsc_ClockSelect_fspb 

f_SPB is the clock source for the ABRA block

IfxMsc_ClockSelect_fsri 

f_SRI is the clock source for the ABRA block

IfxMsc_ClockSelect_feray 

f_ERAY is the clock source for the ABRA block

Definition at line 96 of file IfxMsc.h.

Downstream Control Enhanced Register - Command-Data-Command in Data Repetition Mode
Definition in Ifx_MSC.DSCE.B.CDCM.

Enumerator
IfxMsc_CommandDataCommandRepetitionMode_disabled 

Disables the automatic insertion of data.

IfxMsc_CommandDataCommandRepetitionMode_enabled 

Enables the automatic insertion of data.

Definition at line 107 of file IfxMsc.h.

Interrupt Control Register - Command Frame Interrupt Enable
Definition in Ifx_MSC.ICR.B.ECIE.

Enumerator
IfxMsc_CommandFrameInterrupt_disabled 

Interrupt generation disabled.

IfxMsc_CommandFrameInterrupt_enabled 

Interrupt generation enabled.

Definition at line 116 of file IfxMsc.h.

Interrupt Control Register - Command Frame Interrupt Node Pointer
Definition in Ifx_MSC.ICR.B.ECIP.

Enumerator
IfxMsc_CommandFrameInterruptNode_SR0 

Service request output SR0 selected.

IfxMsc_CommandFrameInterruptNode_SR1 

Service request output SR1 selected.

IfxMsc_CommandFrameInterruptNode_SR2 

Service request output SR2 selected.

IfxMsc_CommandFrameInterruptNode_SR3 

Service request output SR3 selected.

Definition at line 125 of file IfxMsc.h.

Number of Bits shifted at command frames
Definition in Ifx_MSC.DSC.B.NBC.

Enumerator
IfxMsc_CommandFrameLength_0 

No bit shifted.

IfxMsc_CommandFrameLength_1 

SRL[0] Shifted.

IfxMsc_CommandFrameLength_2 

SRL[1:0] Shifted.

IfxMsc_CommandFrameLength_3 

SRL[2:0] Shifted.

IfxMsc_CommandFrameLength_4 

SRL[3:0] Shifted.

IfxMsc_CommandFrameLength_5 

SRL[4:0] Shifted.

IfxMsc_CommandFrameLength_6 

SRL[5:0] Shifted.

IfxMsc_CommandFrameLength_7 

SRL[6:0] Shifted.

IfxMsc_CommandFrameLength_8 

SRL[7:0] Shifted.

IfxMsc_CommandFrameLength_9 

SRL[8:0] Shifted.

IfxMsc_CommandFrameLength_10 

SRL[9:0] Shifted.

IfxMsc_CommandFrameLength_11 

SRL[10:0] Shifted.

IfxMsc_CommandFrameLength_12 

SRL[11:0] Shifted.

IfxMsc_CommandFrameLength_13 

SRL[12:0] Shifted.

IfxMsc_CommandFrameLength_14 

SRL[13:0] Shifted.

IfxMsc_CommandFrameLength_15 

SRL[14:0] Shifted.

IfxMsc_CommandFrameLength_16 

SRL[15:0] Shifted.

IfxMsc_CommandFrameLength_17 

SRL[15:0] and SRH[0] Shifted.

IfxMsc_CommandFrameLength_18 

SRL[15:0] and SRH[1:0] Shifted.

IfxMsc_CommandFrameLength_19 

SRL[15:0] and SRH[2:0] Shifted.

IfxMsc_CommandFrameLength_20 

SRL[15:0] and SRH[3:0] Shifted.

IfxMsc_CommandFrameLength_21 

SRL[15:0] and SRH[4:0] Shifted.

IfxMsc_CommandFrameLength_22 

SRL[15:0] and SRH[5:0] Shifted.

IfxMsc_CommandFrameLength_23 

SRL[15:0] and SRH[6:0] Shifted.

IfxMsc_CommandFrameLength_24 

SRL[15:0] and SRH[7:0] Shifted.

IfxMsc_CommandFrameLength_25 

SRL[15:0] and SRH[8:0] Shifted.

IfxMsc_CommandFrameLength_26 

SRL[15:0] and SRH[9:0] Shifted.

IfxMsc_CommandFrameLength_27 

SRL[15:0] and SRH[10:0] Shifted.

IfxMsc_CommandFrameLength_28 

SRL[15:0] and SRH[11:0] Shifted.

IfxMsc_CommandFrameLength_29 

SRL[15:0] and SRH[12:0] Shifted.

IfxMsc_CommandFrameLength_30 

SRL[15:0] and SRH[13:0] Shifted.

IfxMsc_CommandFrameLength_31 

SRL[15:0] and SRH[14:0] Shifted.

IfxMsc_CommandFrameLength_32 

SRL[15:0] and SRH[15:0] Shifted.

Definition at line 136 of file IfxMsc.h.

Downstream Timing Extension Register - Passive Phase Length at Control Frames Extension
Definition in Ifx_MSC.DSTE.B.PPCE.

Enumerator
IfxMsc_ControlFrameExtensionPassivePhaseLength_0 

Length of Command frames passive phase is 2.

IfxMsc_ControlFrameExtensionPassivePhaseLength_1 

Length of Command frames passive phase is 3.

IfxMsc_ControlFrameExtensionPassivePhaseLength_2 

Length of Command frames passive phase is 4.

IfxMsc_ControlFrameExtensionPassivePhaseLength_3 

Length of Command frames passive phase is 5.

IfxMsc_ControlFrameExtensionPassivePhaseLength_4 

Length of Command frames passive phase is 6.

IfxMsc_ControlFrameExtensionPassivePhaseLength_5 

Length of Command frames passive phase is 7.

IfxMsc_ControlFrameExtensionPassivePhaseLength_6 

Length of Command frames passive phase is 8.

IfxMsc_ControlFrameExtensionPassivePhaseLength_7 

Length of Command frames passive phase is 9.

IfxMsc_ControlFrameExtensionPassivePhaseLength_8 

Length of Command frames passive phase is 10.

IfxMsc_ControlFrameExtensionPassivePhaseLength_9 

Length of Command frames passive phase is 11.

IfxMsc_ControlFrameExtensionPassivePhaseLength_10 

Length of Command frames passive phase is 12.

IfxMsc_ControlFrameExtensionPassivePhaseLength_11 

Length of Command frames passive phase is 13.

IfxMsc_ControlFrameExtensionPassivePhaseLength_12 

Length of Command frames passive phase is 14.

IfxMsc_ControlFrameExtensionPassivePhaseLength_13 

Length of Command frames passive phase is 15.

IfxMsc_ControlFrameExtensionPassivePhaseLength_14 

Length of Command frames passive phase is 16.

IfxMsc_ControlFrameExtensionPassivePhaseLength_15 

Length of Command frames passive phase is 17.

IfxMsc_ControlFrameExtensionPassivePhaseLength_16 

Length of Command frames passive phase is 18.

IfxMsc_ControlFrameExtensionPassivePhaseLength_17 

Length of Command frames passive phase is 19.

IfxMsc_ControlFrameExtensionPassivePhaseLength_18 

Length of Command frames passive phase is 20.

IfxMsc_ControlFrameExtensionPassivePhaseLength_19 

Length of Command frames passive phase is 21.

IfxMsc_ControlFrameExtensionPassivePhaseLength_20 

Length of Command frames passive phase is 22.

IfxMsc_ControlFrameExtensionPassivePhaseLength_21 

Length of Command frames passive phase is 23.

IfxMsc_ControlFrameExtensionPassivePhaseLength_22 

Length of Command frames passive phase is 24.

IfxMsc_ControlFrameExtensionPassivePhaseLength_23 

Length of Command frames passive phase is 25.

IfxMsc_ControlFrameExtensionPassivePhaseLength_24 

Length of Command frames passive phase is 26.

IfxMsc_ControlFrameExtensionPassivePhaseLength_25 

Length of Command frames passive phase is 27.

IfxMsc_ControlFrameExtensionPassivePhaseLength_26 

Length of Command frames passive phase is 28.

IfxMsc_ControlFrameExtensionPassivePhaseLength_27 

Length of Command frames passive phase is 29.

IfxMsc_ControlFrameExtensionPassivePhaseLength_28 

Length of Command frames passive phase is 30.

IfxMsc_ControlFrameExtensionPassivePhaseLength_29 

Length of Command frames passive phase is 31.

IfxMsc_ControlFrameExtensionPassivePhaseLength_30 

Length of Command frames passive phase is 32.

IfxMsc_ControlFrameExtensionPassivePhaseLength_31 

Length of Command frames passive phase is 33.

IfxMsc_ControlFrameExtensionPassivePhaseLength_32 

Length of Command frames passive phase is 34.

IfxMsc_ControlFrameExtensionPassivePhaseLength_33 

Length of Command frames passive phase is 35.

IfxMsc_ControlFrameExtensionPassivePhaseLength_34 

Length of Command frames passive phase is 36.

IfxMsc_ControlFrameExtensionPassivePhaseLength_35 

Length of Command frames passive phase is 37.

IfxMsc_ControlFrameExtensionPassivePhaseLength_36 

Length of Command frames passive phase is 38.

IfxMsc_ControlFrameExtensionPassivePhaseLength_37 

Length of Command frames passive phase is 39.

IfxMsc_ControlFrameExtensionPassivePhaseLength_38 

Length of Command frames passive phase is 40.

IfxMsc_ControlFrameExtensionPassivePhaseLength_39 

Length of Command frames passive phase is 41.

IfxMsc_ControlFrameExtensionPassivePhaseLength_40 

Length of Command frames passive phase is 42.

IfxMsc_ControlFrameExtensionPassivePhaseLength_41 

Length of Command frames passive phase is 43.

IfxMsc_ControlFrameExtensionPassivePhaseLength_42 

Length of Command frames passive phase is 44.

IfxMsc_ControlFrameExtensionPassivePhaseLength_43 

Length of Command frames passive phase is 45.

IfxMsc_ControlFrameExtensionPassivePhaseLength_44 

Length of Command frames passive phase is 46.

IfxMsc_ControlFrameExtensionPassivePhaseLength_45 

Length of Command frames passive phase is 47.

IfxMsc_ControlFrameExtensionPassivePhaseLength_46 

Length of Command frames passive phase is 48.

IfxMsc_ControlFrameExtensionPassivePhaseLength_47 

Length of Command frames passive phase is 49.

IfxMsc_ControlFrameExtensionPassivePhaseLength_48 

Length of Command frames passive phase is 50.

IfxMsc_ControlFrameExtensionPassivePhaseLength_49 

Length of Command frames passive phase is 51.

IfxMsc_ControlFrameExtensionPassivePhaseLength_50 

Length of Command frames passive phase is 52.

IfxMsc_ControlFrameExtensionPassivePhaseLength_51 

Length of Command frames passive phase is 53.

IfxMsc_ControlFrameExtensionPassivePhaseLength_52 

Length of Command frames passive phase is 54.

IfxMsc_ControlFrameExtensionPassivePhaseLength_53 

Length of Command frames passive phase is 55.

IfxMsc_ControlFrameExtensionPassivePhaseLength_54 

Length of Command frames passive phase is 56.

IfxMsc_ControlFrameExtensionPassivePhaseLength_55 

Length of Command frames passive phase is 57.

IfxMsc_ControlFrameExtensionPassivePhaseLength_56 

Length of Command frames passive phase is 58.

IfxMsc_ControlFrameExtensionPassivePhaseLength_57 

Length of Command frames passive phase is 59.

IfxMsc_ControlFrameExtensionPassivePhaseLength_58 

Length of Command frames passive phase is 60.

IfxMsc_ControlFrameExtensionPassivePhaseLength_59 

Length of Command frames passive phase is 61.

IfxMsc_ControlFrameExtensionPassivePhaseLength_60 

Length of Command frames passive phase is 62.

IfxMsc_ControlFrameExtensionPassivePhaseLength_61 

Length of Command frames passive phase is 63.

IfxMsc_ControlFrameExtensionPassivePhaseLength_62 

Length of Command frames passive phase is 64.

IfxMsc_ControlFrameExtensionPassivePhaseLength_63 

Length of Command frames passive phase is 65.

Definition at line 176 of file IfxMsc.h.

Downstream Timing Extension Register - Passive Phase Length at Data Frames Extension
Definition in Ifx_MSC.DSTE.B.PPDE.

Enumerator
IfxMsc_DataFrameExtensionPassivePhaseLength_0 

0 Additional MSB bits extension of the PPD bit field

IfxMsc_DataFrameExtensionPassivePhaseLength_1 

1 Additional MSB bits extension of the PPD bit field

IfxMsc_DataFrameExtensionPassivePhaseLength_2 

2 Additional MSB bits extension of the PPD bit field

IfxMsc_DataFrameExtensionPassivePhaseLength_3 

3 Additional MSB bits extension of the PPD bit field

Definition at line 247 of file IfxMsc.h.

Interrupt Control Register - Data Frame Interrupt Enable
Definition in Ifx_MSC.ICR.B.EDIE.

Enumerator
IfxMsc_DataFrameInterrupt_disabled 

Interrupt generation Disable.

IfxMsc_DataFrameInterrupt_atLastDataBit 

An interrupt is generated when the last data bit has been shifted out.

IfxMsc_DataFrameInterrupt_atFirstDataBit 

An interrupt is generated when the First data bit has been shifted out.

Definition at line 258 of file IfxMsc.h.

Interrupt Control Register - Data Frame Interrupt Node Pointer
Definition in Ifx_MSC.ICR.B.EDIP.

Enumerator
IfxMsc_DataFrameInterruptNode_SR0 

Service request output SR0 selected.

IfxMsc_DataFrameInterruptNode_SR1 

Service request output SR1 selected.

IfxMsc_DataFrameInterruptNode_SR2 

Service request output SR2 selected.

IfxMsc_DataFrameInterruptNode_SR3 

Service request output SR3 selected.

Definition at line 268 of file IfxMsc.h.

Number of SRx[] (x->SRL/SRH) Bits Shifted at Data Frames
Definition in Ifx_MSC.DSC.B.NDBH and Ifx_MSC.DSC.B.NDBL.

Enumerator
IfxMsc_DataFrameLength_0 

No SRx bit shifted.

IfxMsc_DataFrameLength_1 

SRx[0] Shifted.

IfxMsc_DataFrameLength_2 

SRx[1:0] Shifted.

IfxMsc_DataFrameLength_3 

SRx[2:0] Shifted.

IfxMsc_DataFrameLength_4 

SRx[3:0] Shifted.

IfxMsc_DataFrameLength_5 

SRx[4:0] Shifted.

IfxMsc_DataFrameLength_6 

SRx[5:0] Shifted.

IfxMsc_DataFrameLength_7 

SRx[6:0] Shifted.

IfxMsc_DataFrameLength_8 

SRx[7:0] Shifted.

IfxMsc_DataFrameLength_9 

SRx[8:0] Shifted.

IfxMsc_DataFrameLength_10 

SRx[9:0] Shifted.

IfxMsc_DataFrameLength_11 

SRx[10:0] Shifted.

IfxMsc_DataFrameLength_12 

SRx[11:0] Shifted.

IfxMsc_DataFrameLength_13 

SRx[12:0] Shifted.

IfxMsc_DataFrameLength_14 

SRx[13:0] Shifted.

IfxMsc_DataFrameLength_15 

SRx[14:0] Shifted.

IfxMsc_DataFrameLength_16 

SRx[15:0] Shifted.

Definition at line 279 of file IfxMsc.h.

Passive Phase Length at Data Frames
Definition in Ifx_MSC.DSC.B.PPD.

Enumerator
IfxMsc_DataFramePassivePhaseLength_2 

Passive phase length is 2 tFCL.

IfxMsc_DataFramePassivePhaseLength_3 

Passive phase length is 3 tFCL.

IfxMsc_DataFramePassivePhaseLength_4 

Passive phase length is 4 tFCL.

IfxMsc_DataFramePassivePhaseLength_5 

Passive phase length is 5 tFCL.

IfxMsc_DataFramePassivePhaseLength_6 

Passive phase length is 6 tFCL.

IfxMsc_DataFramePassivePhaseLength_7 

Passive phase length is 7 tFCL.

IfxMsc_DataFramePassivePhaseLength_8 

Passive phase length is 8 tFCL.

IfxMsc_DataFramePassivePhaseLength_9 

Passive phase length is 9 tFCL.

IfxMsc_DataFramePassivePhaseLength_10 

Passive phase length is 10 tFCL.

IfxMsc_DataFramePassivePhaseLength_11 

Passive phase length is 11 tFCL.

IfxMsc_DataFramePassivePhaseLength_12 

Passive phase length is 12 tFCL.

IfxMsc_DataFramePassivePhaseLength_13 

Passive phase length is 13 tFCL.

IfxMsc_DataFramePassivePhaseLength_14 

Passive phase length is 14 tFCL.

IfxMsc_DataFramePassivePhaseLength_15 

Passive phase length is 15 tFCL.

IfxMsc_DataFramePassivePhaseLength_16 

Passive phase length is 16 tFCL.

IfxMsc_DataFramePassivePhaseLength_17 

Passive phase length is 17 tFCL.

IfxMsc_DataFramePassivePhaseLength_18 

Passive phase length is 18 tFCL.

IfxMsc_DataFramePassivePhaseLength_19 

Passive phase length is 19 tFCL.

IfxMsc_DataFramePassivePhaseLength_20 

Passive phase length is 20 tFCL.

IfxMsc_DataFramePassivePhaseLength_21 

Passive phase length is 21 tFCL.

IfxMsc_DataFramePassivePhaseLength_22 

Passive phase length is 22 tFCL.

IfxMsc_DataFramePassivePhaseLength_23 

Passive phase length is 23 tFCL.

IfxMsc_DataFramePassivePhaseLength_24 

Passive phase length is 24 tFCL.

IfxMsc_DataFramePassivePhaseLength_25 

Passive phase length is 25 tFCL.

IfxMsc_DataFramePassivePhaseLength_26 

Passive phase length is 26 tFCL.

IfxMsc_DataFramePassivePhaseLength_27 

Passive phase length is 27 tFCL.

IfxMsc_DataFramePassivePhaseLength_28 

Passive phase length is 28 tFCL.

IfxMsc_DataFramePassivePhaseLength_29 

Passive phase length is 29 tFCL.

IfxMsc_DataFramePassivePhaseLength_30 

Passive phase length is 30 tFCL.

IfxMsc_DataFramePassivePhaseLength_31 

Passive phase length is 31 tFCL.

IfxMsc_DataFramePassivePhaseLength_32 

Passive phase length is 32 tFCL.

Definition at line 303 of file IfxMsc.h.

Divider mode.

Enumerator
IfxMsc_DividerMode_normal 

divider mode is normal

IfxMsc_DividerMode_fractional 

divider mode is fractional

Definition at line 340 of file IfxMsc.h.

Emergency Stop Register - Emergency stop feature Enable or Disable - SRL and SRH
Definition in Ifx_MSC.ESR.

Enumerator
IfxMsc_EmergencyStop_disabled 

Emergency stop feature for SRx bit is Disabled.

IfxMsc_EmergencyStop_enabled 

Emergency stop feature for SRx bit is Enabled.

Definition at line 349 of file IfxMsc.h.

Downstream Control Enhanced Register - Extension Enable
Definition in Ifx_MSC.DSCE.B.NDBLE.

Enumerator
IfxMsc_Extension_disabled 

Disables the extension bit fields.

IfxMsc_Extension_enabled 

Enables the extension bit fields.

Definition at line 358 of file IfxMsc.h.

Downstream Control Enhanced Register - Injection Position of the Pin 0 and 1 Signal
Definition in Ifx_MSC.DSCE.B.INJPOSP0 and Ifx_MSC.DSCE.B.INJPOSP1.

Enumerator
IfxMsc_ExternalBitInjectionPosition_0 

Injected external bit is at Position 0 of the data frame.

IfxMsc_ExternalBitInjectionPosition_1 

Injected external bit is at Position 1 of the data frame.

IfxMsc_ExternalBitInjectionPosition_2 

Injected external bit is at Position 2 of the data frame.

IfxMsc_ExternalBitInjectionPosition_3 

Injected external bit is at Position 3 of the data frame.

IfxMsc_ExternalBitInjectionPosition_4 

Injected external bit is at Position 4 of the data frame.

IfxMsc_ExternalBitInjectionPosition_5 

Injected external bit is at Position 5 of the data frame.

IfxMsc_ExternalBitInjectionPosition_6 

Injected external bit is at Position 6 of the data frame.

IfxMsc_ExternalBitInjectionPosition_7 

Injected external bit is at Position 7 of the data frame.

IfxMsc_ExternalBitInjectionPosition_8 

Injected external bit is at Position 8 of the data frame.

IfxMsc_ExternalBitInjectionPosition_9 

Injected external bit is at Position 9 of the data frame.

IfxMsc_ExternalBitInjectionPosition_10 

Injected external bit is at Position 10 of the data frame.

IfxMsc_ExternalBitInjectionPosition_11 

Injected external bit is at Position 11 of the data frame.

IfxMsc_ExternalBitInjectionPosition_12 

Injected external bit is at Position 12 of the data frame.

IfxMsc_ExternalBitInjectionPosition_13 

Injected external bit is at Position 13 of the data frame.

IfxMsc_ExternalBitInjectionPosition_14 

Injected external bit is at Position 14 of the data frame.

IfxMsc_ExternalBitInjectionPosition_15 

Injected external bit is at Position 15 of the data frame.

IfxMsc_ExternalBitInjectionPosition_16 

Injected external bit is at Position 16 of the data frame.

IfxMsc_ExternalBitInjectionPosition_17 

Injected external bit is at Position 17 of the data frame.

IfxMsc_ExternalBitInjectionPosition_18 

Injected external bit is at Position 18 of the data frame.

IfxMsc_ExternalBitInjectionPosition_19 

Injected external bit is at Position 19 of the data frame.

IfxMsc_ExternalBitInjectionPosition_20 

Injected external bit is at Position 20 of the data frame.

IfxMsc_ExternalBitInjectionPosition_21 

Injected external bit is at Position 21 of the data frame.

IfxMsc_ExternalBitInjectionPosition_22 

Injected external bit is at Position 22 of the data frame.

IfxMsc_ExternalBitInjectionPosition_23 

Injected external bit is at Position 23 of the data frame.

IfxMsc_ExternalBitInjectionPosition_24 

Injected external bit is at Position 24 of the data frame.

IfxMsc_ExternalBitInjectionPosition_25 

Injected external bit is at Position 25 of the data frame.

IfxMsc_ExternalBitInjectionPosition_26 

Injected external bit is at Position 26 of the data frame.

IfxMsc_ExternalBitInjectionPosition_27 

Injected external bit is at Position 27 of the data frame.

IfxMsc_ExternalBitInjectionPosition_28 

Injected external bit is at Position 28 of the data frame.

IfxMsc_ExternalBitInjectionPosition_29 

Injected external bit is at Position 29 of the data frame.

IfxMsc_ExternalBitInjectionPosition_30 

Injected external bit is at Position 30 of the data frame.

IfxMsc_ExternalBitInjectionPosition_31 

Injected external bit is at Position 31 of the data frame.

IfxMsc_ExternalBitInjectionPosition_32 

Injected external bit is at Position 32 of the data frame.

IfxMsc_ExternalBitInjectionPosition_33 

Injected external bit is at Position 33 of the data frame.

IfxMsc_ExternalBitInjectionPosition_34 

Injected external bit is at Position 34 of the data frame.

IfxMsc_ExternalBitInjectionPosition_35 

Injected external bit is at Position 35 of the data frame.

IfxMsc_ExternalBitInjectionPosition_36 

Injected external bit is at Position 36 of the data frame.

IfxMsc_ExternalBitInjectionPosition_37 

Injected external bit is at Position 37 of the data frame.

IfxMsc_ExternalBitInjectionPosition_38 

Injected external bit is at Position 38 of the data frame.

IfxMsc_ExternalBitInjectionPosition_39 

Injected external bit is at Position 39 of the data frame.

IfxMsc_ExternalBitInjectionPosition_40 

Injected external bit is at Position 40 of the data frame.

IfxMsc_ExternalBitInjectionPosition_41 

Injected external bit is at Position 41 of the data frame.

IfxMsc_ExternalBitInjectionPosition_42 

Injected external bit is at Position 42 of the data frame.

IfxMsc_ExternalBitInjectionPosition_43 

Injected external bit is at Position 43 of the data frame.

IfxMsc_ExternalBitInjectionPosition_44 

Injected external bit is at Position 44 of the data frame.

IfxMsc_ExternalBitInjectionPosition_45 

Injected external bit is at Position 45 of the data frame.

IfxMsc_ExternalBitInjectionPosition_46 

Injected external bit is at Position 46 of the data frame.

IfxMsc_ExternalBitInjectionPosition_47 

Injected external bit is at Position 47 of the data frame.

IfxMsc_ExternalBitInjectionPosition_48 

Injected external bit is at Position 48 of the data frame.

IfxMsc_ExternalBitInjectionPosition_49 

Injected external bit is at Position 49 of the data frame.

IfxMsc_ExternalBitInjectionPosition_50 

Injected external bit is at Position 50 of the data frame.

IfxMsc_ExternalBitInjectionPosition_51 

Injected external bit is at Position 51 of the data frame.

IfxMsc_ExternalBitInjectionPosition_52 

Injected external bit is at Position 52 of the data frame.

IfxMsc_ExternalBitInjectionPosition_53 

Injected external bit is at Position 53 of the data frame.

IfxMsc_ExternalBitInjectionPosition_54 

Injected external bit is at Position 54 of the data frame.

IfxMsc_ExternalBitInjectionPosition_55 

Injected external bit is at Position 55 of the data frame.

IfxMsc_ExternalBitInjectionPosition_56 

Injected external bit is at Position 56 of the data frame.

IfxMsc_ExternalBitInjectionPosition_57 

Injected external bit is at Position 57 of the data frame.

IfxMsc_ExternalBitInjectionPosition_58 

Injected external bit is at Position 58 of the data frame.

IfxMsc_ExternalBitInjectionPosition_59 

Injected external bit is at Position 59 of the data frame.

IfxMsc_ExternalBitInjectionPosition_60 

Injected external bit is at Position 60 of the data frame.

IfxMsc_ExternalBitInjectionPosition_61 

Injected external bit is at Position 61 of the data frame.

IfxMsc_ExternalBitInjectionPosition_62 

Injected external bit is at Position 62 of the data frame.

IfxMsc_ExternalBitInjectionPosition_63 

Injected external bit is at Position 63 of the data frame.

Definition at line 367 of file IfxMsc.h.

Downstream Control Enhanced Register - Injection Enable of the Pin 0 and 1 Signal
Definition in Ifx_MSC.DSCE.B.INJENP0 and Ifx_MSC.DSCE.B.INJENP1.

Enumerator
IfxMsc_ExternalSignalInjection_disabled 

Disables the external signal injection in a data frame.

IfxMsc_ExternalSignalInjection_enabled 

Enables the external signal injection in a data frame.

Definition at line 438 of file IfxMsc.h.

Output Control Register - Clock Control
Definition in Ifx_MSC.OCR.B.CLKCTRL.

Enumerator
IfxMsc_FclClockControlEnabled_activePhaseOnly 

FCL is active during active phases of data or command frames.

IfxMsc_FclClockControlEnabled_always 

FCL is always active.

Definition at line 447 of file IfxMsc.h.

Output Control Register - FCLP Line Polarity
Definition in Ifx_MSC.OCR.B.CLP.

Enumerator
IfxMsc_FclLinePolarity_nonInverted 

FCLP and FCL signal polarity is identical.

IfxMsc_FclLinePolarity_inverted 

FCLP signal has inverted FCL signal polarity.

Definition at line 456 of file IfxMsc.h.

Enable hardware clock control.

Enumerator
IfxMsc_HardwareClock_disabled 

Hardware clock disable.

IfxMsc_HardwareClock_enabled 

Hardware clock enable.

Definition at line 464 of file IfxMsc.h.

OCDS Control and Status - OCDS Suspend Control Definition in Ifx_MSC.OCS.B.SUS.

Enumerator
IfxMsc_ModuleSuspendRequestBit_noSuspend 

OCDS is not suspended.

IfxMsc_ModuleSuspendRequestBit_hardSuspend 

OCDS is Hard suspended. Clock is switched off immediately.

IfxMsc_ModuleSuspendRequestBit_softSuspend 

OCDS is Soft suspended.

Definition at line 473 of file IfxMsc.h.

Downstream Control Enhanced Register - Number of SRL/SRH Bits Shifted at Data Frames Extension (NDBL/NDBH)
Definition in Ifx_MSC.DSCE.B.NDBLE and Ifx_MSC.DSCE.B.NDBHE.

Enumerator
IfxMsc_MsbBitDataExtension_notPresent 

Additional MSB bit is not present in the extension of the NDBL/NDBH bit field.

IfxMsc_MsbBitDataExtension_present 

Additional MSB bit is present in the extension of the NDBL/NDBH bit field.

Definition at line 483 of file IfxMsc.h.

Asynchronous Block Configuration Register - N Divider ABRA
Definition in Ifx_MSC.ABC.B.NDA.

Enumerator
IfxMsc_NDividerAbra_1 

Division ratio is 1.

IfxMsc_NDividerAbra_2 

Division ratio is 2.

IfxMsc_NDividerAbra_3 

Division ratio is 3.

IfxMsc_NDividerAbra_4 

Division ratio is 4.

IfxMsc_NDividerAbra_5 

Division ratio is 5.

IfxMsc_NDividerAbra_6 

Division ratio is 6.

IfxMsc_NDividerAbra_7 

Division ratio is 7.

IfxMsc_NDividerAbra_8 

Division ratio is 8.

Definition at line 492 of file IfxMsc.h.

Downstream Timing Extension Register - N Divider Downstream
Definition in Ifx_MSC.DSTE.B.NDD.

Enumerator
IfxMsc_NDividerDownstream_1 

division ratio is 1

IfxMsc_NDividerDownstream_2 

division ratio is 2

IfxMsc_NDividerDownstream_3 

division ratio is 3

IfxMsc_NDividerDownstream_4 

division ratio is 4

IfxMsc_NDividerDownstream_5 

division ratio is 5

IfxMsc_NDividerDownstream_6 

division ratio is 6

IfxMsc_NDividerDownstream_7 

division ratio is 7

IfxMsc_NDividerDownstream_8 

division ratio is 8

IfxMsc_NDividerDownstream_9 

division ratio is 9

IfxMsc_NDividerDownstream_10 

division ratio is 10

IfxMsc_NDividerDownstream_11 

division ratio is 11

IfxMsc_NDividerDownstream_12 

division ratio is 12

IfxMsc_NDividerDownstream_13 

division ratio is 13

IfxMsc_NDividerDownstream_14 

division ratio is 14

IfxMsc_NDividerDownstream_15 

division ratio is 15

IfxMsc_NDividerDownstream_16 

division ratio is 16

Definition at line 507 of file IfxMsc.h.

Asynchronous Block Configuration Register - Overflow Interrupt Enable
Definition in Ifx_MSC.ABC.B.OIE.

Enumerator
IfxMsc_OverflowInterrupt_disabled 

Disables the path of the overflow interrupt towards the interrupt node.

IfxMsc_OverflowInterrupt_enabled 

Enables the path of the overflow interrupt towards the interrupt node.

Definition at line 530 of file IfxMsc.h.

Asynchronous Block Configuration Register - Overflow Interrupt Node Pointer
Definition in Ifx_MSC.ABC.B.OIP.

Enumerator
IfxMsc_OverflowInterruptNode_SR0 

Service request output SR0 selected.

IfxMsc_OverflowInterruptNode_SR1 

Service request output SR1 selected.

IfxMsc_OverflowInterruptNode_SR2 

Service request output SR2 selected.

IfxMsc_OverflowInterruptNode_SR3 

Service request output SR3 selected.

IfxMsc_OverflowInterruptNode_SR4 

Service request output SR4 selected.

Definition at line 539 of file IfxMsc.h.

Parity Mode
Definition in Ifx_MSC.USR.B.PCT.

Enumerator
IfxMsc_Parity_even 

Even Parity.

IfxMsc_Parity_odd 

Odd Parity.

Definition at line 551 of file IfxMsc.h.

Downstream Status Register - Number Of Passive Time Frames
Definition in Ifx_MSC.DSS.B.NPTF.

Enumerator
IfxMsc_PassiveTimeFrameCount_0 

No Passive time frames inserted.

IfxMsc_PassiveTimeFrameCount_1 

1 Passive time frames inserted

IfxMsc_PassiveTimeFrameCount_2 

2 Passive time frames inserted

IfxMsc_PassiveTimeFrameCount_3 

3 Passive time frames inserted

IfxMsc_PassiveTimeFrameCount_4 

4 Passive time frames inserted

IfxMsc_PassiveTimeFrameCount_5 

5 Passive time frames inserted

IfxMsc_PassiveTimeFrameCount_6 

6 Passive time frames inserted

IfxMsc_PassiveTimeFrameCount_7 

7 Passive time frames inserted

IfxMsc_PassiveTimeFrameCount_8 

8 Passive time frames inserted

IfxMsc_PassiveTimeFrameCount_9 

9 Passive time frames inserted

IfxMsc_PassiveTimeFrameCount_10 

10 Passive time frames inserted

IfxMsc_PassiveTimeFrameCount_11 

11 Passive time frames inserted

IfxMsc_PassiveTimeFrameCount_12 

12 Passive time frames inserted

IfxMsc_PassiveTimeFrameCount_13 

13 Passive time frames inserted

IfxMsc_PassiveTimeFrameCount_14 

14 Passive time frames inserted

IfxMsc_PassiveTimeFrameCount_15 

15 Passive time frames inserted

Definition at line 560 of file IfxMsc.h.

Interrupt Control Register - Receive Data Interrupt Enable
Definition in Ifx_MSC.ICR.B.RDIE.

Enumerator
IfxMsc_ReceiveDataInterrupt_disabled 

Interrupt generation disabled.

IfxMsc_ReceiveDataInterrupt_onDataReceive 

An interrupt is generated when data is received and written into the upstream data registers.

IfxMsc_ReceiveDataInterrupt_onRdieSet 

An interrupt is generated as with RDIE = 01B but only if the received data is not equal to 00H.

IfxMsc_ReceiveDataInterrupt_onDataReceiveInUd3 

An interrupt is generated as with RDIE = 01B but only if the received data is not equal to 00H.

Definition at line 583 of file IfxMsc.h.

Interrupt Control Register - Receive Data Interrupt Pointer
Definition in Ifx_MSC.ICR.B.RDIP.

Enumerator
IfxMsc_ReceiveDataInterruptNode_SR0 

Service request output SR0 selected.

IfxMsc_ReceiveDataInterruptNode_SR1 

Service request output SR1 selected.

IfxMsc_ReceiveDataInterruptNode_SR2 

Service request output SR2 selected.

IfxMsc_ReceiveDataInterruptNode_SR3 

Service request output SR3 selected.

Definition at line 594 of file IfxMsc.h.

Output Control Register - SDI Line Polarity
Definition in Ifx_MSC.OCR.B.ILP.

Enumerator
IfxMsc_SdiLinePolarity_likeSi 

SDI and SI signal polarities are identical.

IfxMsc_SdiLinePolarity_invertedSi 

SDI and SI signal polarities are inverted.

Definition at line 605 of file IfxMsc.h.

Output Control Register - Serial Data Input Selection
Definition in Ifx_MSC.OCR.B.SDISEL.

Enumerator
IfxMsc_SerialDataInput_0 

SDI0 is selected for the SDI of the upstream channel.

IfxMsc_SerialDataInput_1 

SDI1 is selected for the SDI of the upstream channel.

IfxMsc_SerialDataInput_2 

SDI2 is selected for the SDI of the upstream channel.

IfxMsc_SerialDataInput_3 

SDI3 is selected for the SDI of the upstream channel.

IfxMsc_SerialDataInput_4 

SDI4 is selected for the SDI of the upstream channel.

IfxMsc_SerialDataInput_5 

SDI5 is selected for the SDI of the upstream channel.

IfxMsc_SerialDataInput_6 

SDI6 is selected for the SDI of the upstream channel.

IfxMsc_SerialDataInput_7 

SDI7 is selected for the SDI of the upstream channel.

Definition at line 614 of file IfxMsc.h.

Service Request Delay
Definition in Ifx_MSC.USR.B.SRDC.

Enumerator
IfxMsc_ServiceRequestDelay_noDelay 

No Delay.

IfxMsc_ServiceRequestDelay_1bit 

Delay of 1 bit time.

Definition at line 629 of file IfxMsc.h.

Asynchronous Block Configuration Register - Duration of the Low/High Phase of the Shift Clock
Definition in Ifx_MSC.ABC.B.LOW and Ifx_MSC.ABC.B.HIGH.

Enumerator
IfxMsc_ShiftClockPhaseDuration_1 

Duration in periods of f_A is 1.

IfxMsc_ShiftClockPhaseDuration_2 

Duration in periods of f_A is 2.

IfxMsc_ShiftClockPhaseDuration_3 

Duration in periods of f_A is 3.

IfxMsc_ShiftClockPhaseDuration_4 

Duration in periods of f_A is 4.

IfxMsc_ShiftClockPhaseDuration_5 

Duration in periods of f_A is 5.

IfxMsc_ShiftClockPhaseDuration_6 

Duration in periods of f_A is 6.

IfxMsc_ShiftClockPhaseDuration_7 

Duration in periods of f_A is 7.

IfxMsc_ShiftClockPhaseDuration_8 

Duration in periods of f_A is 8.

IfxMsc_ShiftClockPhaseDuration_9 

Duration in periods of f_A is 9.

IfxMsc_ShiftClockPhaseDuration_10 

Duration in periods of f_A is 10.

IfxMsc_ShiftClockPhaseDuration_11 

Duration in periods of f_A is 11.

IfxMsc_ShiftClockPhaseDuration_12 

Duration in periods of f_A is 12.

IfxMsc_ShiftClockPhaseDuration_13 

Duration in periods of f_A is 13.

IfxMsc_ShiftClockPhaseDuration_14 

Duration in periods of f_A is 14.

IfxMsc_ShiftClockPhaseDuration_15 

Duration in periods of f_A is 15.

IfxMsc_ShiftClockPhaseDuration_16 

Duration in periods of f_A is 16.

Definition at line 638 of file IfxMsc.h.

Clock Control Register - Sleep Mode Enable Control Definition in Ifx_MSC.CLC.B.EDIS.

Enumerator
IfxMsc_SleepMode_disabled 

module sleep mode is disabled

IfxMsc_SleepMode_enabled 

module sleep mode is enabled

Definition at line 661 of file IfxMsc.h.

Output Control Register - SOP Line Polarity
Definition in Ifx_MSC.OCR.B.SLP.

Enumerator
IfxMsc_SoLinePolarity_nonInverted 

SOP and SO polarity is identical.

IfxMsc_SoLinePolarity_inverted 

SOP and SO polarity is inverted.

Definition at line 670 of file IfxMsc.h.

Downstream Select Data Source Low Register - Select Source for - SRL and SRHNumber Of Passive Time Frames
Definition in Ifx_MSC.DSDSL and Ifx_MSC.DSDSH.

Enumerator
IfxMsc_Source_downstreamDataRegister 

SRx[16] is taken from data Register DD.DDL[xx].

IfxMsc_Source_alternateInputLine 

SRx[16] is taken from ALTINL input line.

IfxMsc_Source_alternateInputLineInverted 

SRx[16] is taken from ALTINL input line in inverted state.

Definition at line 679 of file IfxMsc.h.

Msc Targets - use as chip enable selection for ENH, ENL and ENC.

Enumerator
IfxMsc_Target_en0 

Target EN0.

IfxMsc_Target_en1 

Target EN1.

IfxMsc_Target_en2 

Target EN2.

IfxMsc_Target_en3 

Target EN3.

Definition at line 688 of file IfxMsc.h.

Interrupt Control Register - Time Frame Interrupt Enable
Definition in Ifx_MSC.ICR.B.TFIE.

Enumerator
IfxMsc_TimeFrameInterrupt_disabled 

Interrupt generation disabled.

IfxMsc_TimeFrameInterrupt_enabled 

Interrupt generation enabled.

Definition at line 699 of file IfxMsc.h.

Interrupt Control Register - Time Frame Interrupt Pointer
Definition in Ifx_MSC.ICR.B.TFIP.

Enumerator
IfxMsc_TimeFrameInterruptNode_SR0 

Service request output SR0 selected.

IfxMsc_TimeFrameInterruptNode_SR1 

Service request output SR1 selected.

IfxMsc_TimeFrameInterruptNode_SR2 

Service request output SR2 selected.

IfxMsc_TimeFrameInterruptNode_SR3 

Service request output SR3 selected.

Definition at line 708 of file IfxMsc.h.

Downstream Channel Transmission Mode
Definition in Ifx_MSC.DSC.B.TM.

Enumerator
IfxMsc_TransmissionMode_triggered 

Triggered Mode.

IfxMsc_TransmissionMode_dataRepetition 

Data Repetition Mode.

Definition at line 719 of file IfxMsc.h.

Asynchronous Block Configuration Register - Underflow Interrupt Enable
Definition in Ifx_MSC.ABC.B.UIE.

Enumerator
IfxMsc_UnderflowInterrupt_disabled 

Disables the path of the Underflow interrupt towards the interrupt node.

IfxMsc_UnderflowInterrupt_enabled 

Enables the path of the Underflow interrupt towards the interrupt node.

Definition at line 728 of file IfxMsc.h.

Asynchronous Block Configuration Register - Underflow Interrupt Node Pointer
Definition in Ifx_MSC.ABC.B.UIP.

Enumerator
IfxMsc_UnderflowInterruptNode_SR0 

Service request output SR0 selected.

IfxMsc_UnderflowInterruptNode_SR1 

Service request output SR1 selected.

IfxMsc_UnderflowInterruptNode_SR2 

Service request output SR2 selected.

IfxMsc_UnderflowInterruptNode_SR3 

Service request output SR3 selected.

IfxMsc_UnderflowInterruptNode_SR4 

Service request output SR4 selected.

Definition at line 737 of file IfxMsc.h.

Channel Frame Type
Definition in Ifx_MSC.USR.B.UFT.

Enumerator
IfxMsc_UpstreamChannelFrameType_12bit 

12-bit Upstream frame selected

IfxMsc_UpstreamChannelFrameType_16bit 

16-bit Upstream frame selected

Definition at line 749 of file IfxMsc.h.

Upstream Receiving Rate
Definition in Ifx_MSC.USR.B.URR.

Enumerator
IfxMsc_UpstreamChannelReceivingRate_disabled 

Disabled.

IfxMsc_UpstreamChannelReceivingRate_4 

Baud rate = f_MSC / 4.

IfxMsc_UpstreamChannelReceivingRate_8 

Baud rate = f_MSC / 8.

IfxMsc_UpstreamChannelReceivingRate_16 

Baud rate = f_MSC / 16.

IfxMsc_UpstreamChannelReceivingRate_32 

Baud rate = f_MSC / 32.

IfxMsc_UpstreamChannelReceivingRate_64 

Baud rate = f_MSC / 64.

IfxMsc_UpstreamChannelReceivingRate_128 

Baud rate = f_MSC / 128.

IfxMsc_UpstreamChannelReceivingRate_256 

Baud rate = f_MSC / 256.

Definition at line 758 of file IfxMsc.h.

Upstream Control Enhanced Register 1 - Upstream Timeout Interrupt Enable
Definition in Ifx_MSC.USCE.B.USTOEN.

Enumerator
IfxMsc_UpstreamTimeoutInterrupt_disabled 

Upstream Timeout Interrupt Disabled.

IfxMsc_UpstreamTimeoutInterrupt_enabled 

Upstream Timeout Interrupt Enabled.

Definition at line 773 of file IfxMsc.h.

Upstream Control Enhanced Register 1 - Upstream Timeout Interrupt Node Pointer
Definition in Ifx_MSC.USCE.B.USTOIP.

Enumerator
IfxMsc_UpstreamTimeoutInterruptNode_SR0 

Service request output SR0 selected.

IfxMsc_UpstreamTimeoutInterruptNode_SR1 

Service request output SR1 selected.

IfxMsc_UpstreamTimeoutInterruptNode_SR2 

Service request output SR2 selected.

IfxMsc_UpstreamTimeoutInterruptNode_SR3 

Service request output SR3 selected.

Definition at line 782 of file IfxMsc.h.

Upstream Control Enhanced Register 1 - Upstream Timeout Prescaler
Definition in Ifx_MSC.USCE.B.USTOPRE.

Enumerator
IfxMsc_UpstreamTimeoutPrescaler_1 

Prescale value 1 for the upstream time-out limit.

IfxMsc_UpstreamTimeoutPrescaler_2 

Prescale value 2 for the upstream time-out limit.

IfxMsc_UpstreamTimeoutPrescaler_4 

Prescale value 4 for the upstream time-out limit.

IfxMsc_UpstreamTimeoutPrescaler_8 

Prescale value 8 for the upstream time-out limit.

IfxMsc_UpstreamTimeoutPrescaler_16 

Prescale value 16 for the upstream time-out limit.

IfxMsc_UpstreamTimeoutPrescaler_32 

Prescale value 32 for the upstream time-out limit.

IfxMsc_UpstreamTimeoutPrescaler_64 

Prescale value 64 for the upstream time-out limit.

IfxMsc_UpstreamTimeoutPrescaler_128 

Prescale value 128 for the upstream time-out limit.

IfxMsc_UpstreamTimeoutPrescaler_256 

Prescale value 256 for the upstream time-out limit.

IfxMsc_UpstreamTimeoutPrescaler_512 

Prescale value 512 for the upstream time-out limit.

IfxMsc_UpstreamTimeoutPrescaler_1024 

Prescale value 1024 for the upstream time-out limit.

IfxMsc_UpstreamTimeoutPrescaler_2048 

Prescale value 2048 for the upstream time-out limit.

IfxMsc_UpstreamTimeoutPrescaler_4096 

Prescale value 4096 for the upstream time-out limit.

IfxMsc_UpstreamTimeoutPrescaler_8192 

Prescale value 8192 for the upstream time-out limit.

IfxMsc_UpstreamTimeoutPrescaler_16384 

Prescale value 16384 for the upstream time-out limit.

IfxMsc_UpstreamTimeoutPrescaler_32768 

Prescale value 32768 for the upstream time-out limit.

Definition at line 793 of file IfxMsc.h.

Upstream Control Enhanced Register 1 - Upstream Timeout Value
Definition in Ifx_MSC.USCE.B.USTOVAL.

Enumerator
IfxMsc_UpstreamTimeoutValue_1 

Upstream timeout value for the N-Divider.

IfxMsc_UpstreamTimeoutValue_2 

Upstream timeout value for the N-Divider.

IfxMsc_UpstreamTimeoutValue_3 

Upstream timeout value for the N-Divider.

IfxMsc_UpstreamTimeoutValue_4 

Upstream timeout value for the N-Divider.

IfxMsc_UpstreamTimeoutValue_5 

Upstream timeout value for the N-Divider.

IfxMsc_UpstreamTimeoutValue_6 

Upstream timeout value for the N-Divider.

IfxMsc_UpstreamTimeoutValue_7 

Upstream timeout value for the N-Divider.

IfxMsc_UpstreamTimeoutValue_8 

Upstream timeout value for the N-Divider.

IfxMsc_UpstreamTimeoutValue_9 

Upstream timeout value for the N-Divider.

IfxMsc_UpstreamTimeoutValue_10 

Upstream timeout value for the N-Divider.

IfxMsc_UpstreamTimeoutValue_11 

Upstream timeout value for the N-Divider.

IfxMsc_UpstreamTimeoutValue_12 

Upstream timeout value for the N-Divider.

IfxMsc_UpstreamTimeoutValue_13 

Upstream timeout value for the N-Divider.

IfxMsc_UpstreamTimeoutValue_14 

Upstream timeout value for the N-Divider.

IfxMsc_UpstreamTimeoutValue_15 

Upstream timeout value for the N-Divider.

IfxMsc_UpstreamTimeoutValue_16 

Upstream timeout value for the N-Divider.

Definition at line 816 of file IfxMsc.h.