iLLD_TC27xC  1.0
IfxAsclin_Lin.c
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1 /**
2  * \file IfxAsclin_Lin.c
3  * \brief ASCLIN LIN details
4  *
5  * \version iLLD_0_1_0_10
6  * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
7  *
8  *
9  * IMPORTANT NOTICE
10  *
11  *
12  * Infineon Technologies AG (Infineon) is supplying this file for use
13  * exclusively with Infineon's microcontroller products. This file can be freely
14  * distributed within development tools that are supporting such microcontroller
15  * products.
16  *
17  * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
18  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
19  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
20  * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
21  * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
22  *
23  */
24 
25 /******************************************************************************/
26 /*----------------------------------Includes----------------------------------*/
27 /******************************************************************************/
28 
29 #include "IfxAsclin_Lin.h"
30 #include "Scu/Std/IfxScuWdt.h"
31 
32 /******************************************************************************/
33 /*-------------------------Function Implementations---------------------------*/
34 /******************************************************************************/
35 
37 {
38  Ifx_ASCLIN *asclinSFR = asclin->asclin; /* getting the pointer to ASCLIN registers from module handler*/
39 
40  /* check Rx header end acknowledgement */
41  if (IfxAsclin_getRxHeaderEndFlagStatus(asclinSFR)) /* RHE flag*/
42  {
44  asclin->acknowledgmentFlags.rxHeaderEnd = 1;
45  }
46 
47  /* check for Rx header error flags */
48  if (IfxAsclin_getHeaderTimeoutFlagStatus(asclinSFR)) /* HT flag*/
49  {
51  asclin->errorFlagsStatus.headerTimeout = 1;
52  }
53 
54  if (IfxAsclin_getCollisionDetectionErrorFlagStatus(asclinSFR)) /* CE flag*/
55  {
58  }
59 
60  if (IfxAsclin_getFrameErrorFlagStatus(asclinSFR)) /* FE flag*/
61  {
63  asclin->errorFlagsStatus.frameError = 1;
64  }
65 
66  if (IfxAsclin_getLinAutoBaudDetectionErrorFlagStatus(asclinSFR)) /* LA flag*/
67  {
70  }
71 
72  if (IfxAsclin_getLinParityErrorFlagStatus(asclinSFR)) /* LP flag*/
73  {
75  asclin->errorFlagsStatus.linParityError = 1;
76  }
77 }
78 
79 
81 {
82  Ifx_ASCLIN *asclinSFR = asclin->asclin; /* getting the pointer to ASCLIN registers from module handler*/
83 
84  /* check Rx response end acknowledgement*/
86  {
89  }
90 
91  /* check for Rx response error flags */
92  if (IfxAsclin_getRxFifoOverflowFlagStatus(asclinSFR)) /* RFO flag*/
93  {
95  asclin->errorFlagsStatus.rxFifoOverflow = 1;
96  }
97 
98  if (IfxAsclin_getCollisionDetectionErrorFlagStatus(asclinSFR)) /* CE flag*/
99  {
102  }
103 
104  if (IfxAsclin_getFrameErrorFlagStatus(asclinSFR)) /* FE flag*/
105  {
107  asclin->errorFlagsStatus.frameError = 1;
108  }
109 
110  if (IfxAsclin_getLinChecksumErrorFlagStatus(asclinSFR)) /* LC flag*/
111  {
114  }
115 
116  if (IfxAsclin_getResponseTimeoutFlagStatus(asclinSFR)) /* RT flag*/
117  {
119  asclin->errorFlagsStatus.responseTimeout = 1;
120  }
121 
122  if ((asclin->linMode == IfxAsclin_LinMode_slave) && (IfxAsclin_getBreakDetectedFlagStatus(asclinSFR))) /* BD flag only in slave mode*/
123  {
125  asclin->errorFlagsStatus.breakDetected = 1;
126  }
127 }
128 
129 
131 {
132  Ifx_ASCLIN *asclinSFR = asclin->asclin; /* getting the pointer to ASCLIN registers from module handler*/
133 
134  /* check Tx header end acknowledgement */
135  if (IfxAsclin_getTxHeaderEndFlagStatus(asclinSFR)) /* THE flag*/
136  {
138  asclin->acknowledgmentFlags.txHeaderEnd = 1;
139  }
140 
141  /* check for Tx header error flags */
142  if (IfxAsclin_getHeaderTimeoutFlagStatus(asclinSFR)) /* HT flag*/
143  {
145  asclin->errorFlagsStatus.headerTimeout = 1;
146  }
147 
148  if (IfxAsclin_getCollisionDetectionErrorFlagStatus(asclinSFR)) /* CE flag*/
149  {
152  }
153 
154  if (IfxAsclin_getFrameErrorFlagStatus(asclinSFR)) /* FE flag*/
155  {
157  asclin->errorFlagsStatus.frameError = 1;
158  }
159 
160  if (IfxAsclin_getLinParityErrorFlagStatus(asclinSFR)) /* LP flag*/
161  {
163  asclin->errorFlagsStatus.linParityError = 1;
164  }
165 }
166 
167 
169 {
170  Ifx_ASCLIN *asclinSFR = asclin->asclin; /* getting the pointer to ASCLIN registers from module handler*/
171 
172  /* check Tx response end acknowledgement */
173  if (IfxAsclin_getTxResponseEndFlagStatus(asclinSFR)) /* TRE flag*/
174  {
177  }
178 
179  /* check for Tx response error flags */
180  if (IfxAsclin_getTxFifoOverflowFlagStatus(asclinSFR)) /* TFO flag*/
181  {
183  asclin->errorFlagsStatus.txFifoOverflow = 1;
184  }
185 
186  if (IfxAsclin_getCollisionDetectionErrorFlagStatus(asclinSFR)) /* CE flag*/
187  {
190  }
191 
192  if (IfxAsclin_getResponseTimeoutFlagStatus(asclinSFR)) /* RT flag*/
193  {
195  asclin->errorFlagsStatus.responseTimeout = 1;
196  }
197 
198  if ((asclin->linMode == IfxAsclin_LinMode_slave) && (IfxAsclin_getBreakDetectedFlagStatus(asclinSFR))) /* BD flag only in slave mode*/
199  {
201  asclin->errorFlagsStatus.breakDetected = 1;
202  }
203 }
204 
205 
207 {
208  /*clear acknowledgement flags status */
209  asclin->acknowledgmentFlags.txHeaderEnd = 0;
210  asclin->acknowledgmentFlags.rxHeaderEnd = 0;
213 
214  /* clear error flags status*/
215  asclin->errorFlagsStatus.headerTimeout = 0;
217  asclin->errorFlagsStatus.frameError = 0;
218  asclin->errorFlagsStatus.responseTimeout = 0;
219  asclin->errorFlagsStatus.linParityError = 0;
220  asclin->errorFlagsStatus.breakDetected = 0;
223  asclin->errorFlagsStatus.txFifoOverflow = 0;
224  asclin->errorFlagsStatus.rxFifoOverflow = 0;
225 }
226 
227 
229 {
230  Ifx_ASCLIN *asclinSFR = asclin->asclin; /* getting the pointer to ASCLIN registers from module handler*/
232  IfxScuWdt_clearCpuEndinit(psw); /* clearing the endinit protection*/
233  IfxAsclin_setDisableModuleRequest(asclinSFR); /* disabling the module*/
234  IfxScuWdt_setCpuEndinit(psw); /* setting the endinit protection back on*/
235 }
236 
237 
239 {
240  Ifx_ASCLIN *asclinSFR = asclin->asclin; /* getting the pointer to ASCLIN registers from module handler*/
241  IfxAsclin_enableRxFifoInlet(asclinSFR, FALSE); /* disable Rx FIFO*/
243  IfxAsclin_clearAllFlags(asclinSFR); /* clear all flags*/
244 }
245 
246 
248 {
249  Ifx_ASCLIN *asclinSFR = config->asclin; /* pointer to ASCLIN registers */
251 
252  asclin->asclin = asclinSFR; /* adding register pointer to module handler*/
253  IfxAsclin_enableModule(asclinSFR); /* enabling the module*/
254 
255  /* mode initialisation */
256  IfxAsclin_setClockSource(asclinSFR, IfxAsclin_ClockSource_noClock); /* disabling the clock*/
257  IfxAsclin_setFrameMode(asclinSFR, IfxAsclin_FrameMode_initialise); /* setting the module in Initialise mode*/
258  IfxAsclin_setClockSource(asclinSFR, config->clockSource); /* setting the clock source*/
259 
260  /* lin mode initialisation */
261  IfxAsclin_setClockSource(asclinSFR, IfxAsclin_ClockSource_noClock); /* disabling the clock*/
262  IfxAsclin_setFrameMode(asclinSFR, config->frameMode); /* setting the module in Lin mode*/
263  IfxAsclin_setLinMode(asclinSFR, config->linMode); /* configuring lin mode of operation (master/slave)*/
264  IfxAsclin_setRxInput(asclinSFR, config->alti); /* selecting the Rx(alternate) input pin*/
265  IfxAsclin_setPrescaler(asclinSFR, config->btc.prescaler); /* setting the prescaler*/
266  IfxAsclin_setClockSource(asclinSFR, config->clockSource); /* setting the clock source*/
267 
268  /* baudrate generation in both modes */
269  status = (IfxAsclin_Status)IfxAsclin_setBitTiming(asclinSFR, config->brg.baudrate,
270  config->btc.oversampling,
271  config->bsc.samplePointPosition,
272  config->bsc.medianFilter); /* setting the baudrate bit fields to generate the required baudrate*/
273 
274  IfxAsclin_setClockSource(asclinSFR, IfxAsclin_ClockSource_noClock); /* disabling the clock again*/
275 
276  /* auto baud rate detection in slave mode */
277  if (config->linMode == IfxAsclin_LinMode_slave)
278  {
279  IfxAsclin_enableAutoBaudrateDetection(asclinSFR, config->brd.abd); /* setting the auto baudrate detection (enable/disable)*/
280  IfxAsclin_setBrdUpperlimt(asclinSFR, config->brd.upperLimit); /* setting the upper limit for abd*/
281  IfxAsclin_setBrdLowerlimt(asclinSFR, config->brd.lowerLimit); /* setting the lower limit for abd*/
282  }
283 
284  /* frame control initialisation */
285  IfxAsclin_enableParity(asclinSFR, config->frame.parityEnable); /* setting parity (enable/disable)*/
286  IfxAsclin_setParityType(asclinSFR, config->frame.parityType); /* setting parity type (odd/even)*/
287  IfxAsclin_setStopBit(asclinSFR, config->frame.stopBit); /* setting the stop bit*/
288  IfxAsclin_enableCollisionDetection(asclinSFR, config->frame.collisionDetectionEnable); /* setting collision detection (enable/disable)*/
289  IfxAsclin_setShiftDirection(asclinSFR, config->frame.shiftDir); /* setting the shift direction*/
290 
291  /* data control initialisation */
292  IfxAsclin_setDataLength(asclinSFR, config->data.dataLength); /* setting the number of bytes to be transfered*/
293  IfxAsclin_setHeaderResponseSelect(asclinSFR, config->data.headerOnly); /* setting the header only or header and response mode*/
294  IfxAsclin_setLinResponseTimeoutMode(asclinSFR, config->data.responseTimeoutMode); /* setting the response timeout mode (frame/response)*/
295  IfxAsclin_setChecksumMode(asclinSFR, config->data.checksum); /* setting the checksum mode (classic/enhanced)*/
296  IfxAsclin_setLinResponseTimeoutThreshold(asclinSFR, config->data.responseTimeout); /* setting the lin response timeout threshold*/
297 
298  /* lin control initialisation */
299  IfxAsclin_enableHardwareChecksum(asclinSFR, config->lin.csEnable); /* setting the hardware checksum (enable/disable)*/
300  IfxAsclin_setChecksumInjection(asclinSFR, config->lin.csi); /* setting checksum injection*/
301 
302  /* master specific initialisation */
303  if (config->linMode == IfxAsclin_LinMode_master)
304  {
305  IfxAsclin_setIdleDelay(asclinSFR, config->frame.idleDelay); /* setting idle delay for master*/
306  IfxAsclin_setLeadDelay(asclinSFR, config->frame.leadDelay); /* setting lead delay for master mode*/
307  IfxAsclin_setLinBreakLength(asclinSFR, config->lin.breakLength); /* setting the break generation length*/
308  IfxAsclin_setLinHeaderTimeout(asclinSFR, config->lin.headerTimeout); /* setting the header timeout value for master*/
309  asclin->receiveIdEnable = config->receiveIdEnable; /* echoing the selection of receiving Id in its own Rx FIFO*/
310  }
311 
312  /* slave specific initialisation */
313  if (config->linMode == IfxAsclin_LinMode_slave)
314  {
315  IfxAsclin_setIdleDelay(asclinSFR, config->frame.idleDelay); /* setting idle delay for slave */
316  IfxAsclin_setLeadDelay(asclinSFR, config->frame.leadDelay); /* setting lead delay for slave mode */
317  IfxAsclin_setLinBreakLength(asclinSFR, config->lin.breakLength); /* setting the break detection length */
318  IfxAsclin_setLinHeaderTimeout(asclinSFR, config->lin.headerTimeout); /* setting the header timeout value for slave*/
319  }
320 
321  /* fifo control initialisation */
322  IfxAsclin_setTxFifoInletWidth(asclinSFR, config->fifo.inWidth); /* setting Tx FIFO inlet width*/
323  IfxAsclin_setRxFifoOutletWidth(asclinSFR, config->fifo.outWidth); /* setting Rx FIFO outlet width*/
324  IfxAsclin_setRxBufferMode(asclinSFR, config->fifo.buffMode); /* setting Rx FIFO mode*/
325  IfxAsclin_enableTxFifoOutlet(asclinSFR, FALSE); /* disabling Rx FIFO for recieving*/
326  IfxAsclin_enableRxFifoInlet(asclinSFR, FALSE); /* disabling Tx FIFO for transmitting*/
327  IfxAsclin_flushRxFifo(asclinSFR); /* flushing Rx FIFO*/
328  IfxAsclin_flushTxFifo(asclinSFR); /* flushing Tx FIFO*/
329 
330  IfxAsclin_disableAllFlags(asclinSFR); /* disable all flags*/
331  IfxAsclin_clearAllFlags(asclinSFR); /* clear all flags*/
332 
333  /* Pin mapping*/
334  const IfxAsclin_Lin_Pins *pins = config->pins;
335 
336  if (pins != NULL_PTR)
337  {
338  IfxAsclin_Rx_In *rx = pins->rx;
339 
340  if (rx != NULL_PTR)
341  {
342  IfxAsclin_initRxPin(rx, pins->rxMode);
343  }
344 
345  IfxAsclin_Tx_Out *tx = pins->tx;
346 
347  if (tx != NULL_PTR)
348  {
349  IfxAsclin_initTxPin(tx, pins->txMode, pins->pinDriver);
350  }
351  }
352 
353  IfxAsclin_setClockSource(asclinSFR, config->clockSource); /* setting the clock source*/
354 
355  asclin->linMode = config->linMode; /* echoing the mode of operation to module handler*/
356 
357  return status;
358 }
359 
360 
361 void IfxAsclin_Lin_initModuleConfig(IfxAsclin_Lin_Config *config, Ifx_ASCLIN *asclin)
362 {
363  config->asclin = asclin;
364  config->frameMode = IfxAsclin_FrameMode_lin; /* LIN mode*/
365  config->linMode = IfxAsclin_LinMode_master; /* Lin Master mode*/
366  config->clockSource = IfxAsclin_ClockSource_kernelClock; /* kernel clock, fclc */
367  config->alti = IfxAsclin_RxInputSelect_0; /* alternate input 0;*/
368 
369  /* Default values for baudrate */
370  config->brg.baudrate = 19200.0; /* default baudrate (the fractional dividier setup will be calculated in initModule)*/
371  /* Default Values for Bit Timings */
372  config->btc.prescaler = 4; /* default prescaler*/
373  config->btc.oversampling = IfxAsclin_OversamplingFactor_16; /* default oversampling factor*/
374  /* Default Values for Bit sampling */
375  config->bsc.filterDepth = 24U; /* digital glitch filter depth 24*/
376  config->bsc.medianFilter = IfxAsclin_SamplesPerBit_one; /* one sample per bit*/
377  config->bsc.samplePointPosition = IfxAsclin_SamplePointPosition_3; /* sample point position at 3*/
378  /* Default Values for Frame Control */
379  config->frame.parityEnable = FALSE; /* disable parity*/
380  config->frame.parityType = IfxAsclin_ParityType_even; /* even parity (if parity enabled) */
381  config->frame.stopBit = IfxAsclin_StopBit_1; /* one stop bit */
382  config->frame.shiftDir = IfxAsclin_ShiftDirection_lsbFirst; /* shift diection LSB first */
384  /* Default Values for Data Control */
385  config->data.dataLength = IfxAsclin_DataLength_8; /* number of bytes of the response */
386  config->data.headerOnly = IfxAsclin_HeaderResponseSelect_headerAndResponse; /* header and response */
388  config->data.checksum = IfxAsclin_Checksum_enhanced; /* enhanced checksum */
389  config->data.responseTimeout = 255;
390  /* Default Values for fifo Control */
391  config->fifo.outWidth = IfxAsclin_RxFifoOutletWidth_1; /* 8-bit wide read */
392  config->fifo.inWidth = IfxAsclin_TxFifoInletWidth_1; /* 8-bit wide write */
393  config->fifo.buffMode = IfxAsclin_ReceiveBufferMode_rxFifo; /* RxFIFO */
394  /* Default Values for Lin Control */
395  config->lin.csEnable = TRUE; /* checksum enable */
396  config->lin.csi = IfxAsclin_ChecksumInjection_written; /* 8-bit wide write */
397 
398  /* configuration for master mode */
399  if (config->linMode == IfxAsclin_LinMode_master)
400  {
401  config->receiveIdEnable = FALSE; /* receive Id in Rx Fifo after sending */
402  config->frame.idleDelay = IfxAsclin_IdleDelay_2; /* idle dalay 2 bits */
403  config->frame.leadDelay = IfxAsclin_LeadDelay_1; /*lead delay in master 1 bit */
404  /* Default Values for Lin Control */
405  config->lin.breakLength = 13; /* break generation length 13 */
406  config->lin.headerTimeout = 56; /* header timeout value in master 56 */
407  }
408 
409  /* configuration for slave mode */
410  if (config->linMode == IfxAsclin_LinMode_slave)
411  {
412  config->frame.idleDelay = IfxAsclin_IdleDelay_2; /* idle delay 2 bits */
413  config->frame.leadDelay = IfxAsclin_LeadDelay_1; /* lead delay in slave 1 bit */
414  /* Default Values for Lin Control */
415  config->lin.breakLength = 11; /* break detection length 11 */
416  config->lin.headerTimeout = 48; /* header timeout value in slave 48*/
417  /* Default values for baudrate detection */
418  config->brd.abd = FALSE; /* auto baudrate detection disabled */
419  }
420 
421  config->pins = NULL_PTR; /* pins to null pointer*/
422 }
423 
424 
426 {
427  Ifx_ASCLIN *asclinSFR = asclin->asclin; /* getting the pointer to ASCLIN registers from module handler*/
428  IfxAsclin_clearAllFlags(asclinSFR); /* clearing all flags*/
429  IfxAsclin_flushRxFifo(asclinSFR); /* flushing Rx FIFO*/
430  IfxAsclin_enableTxFifoOutlet(asclinSFR, FALSE); /* enabling Tx FIFO for transmitting*/
431  IfxAsclin_enableRxFifoInlet(asclinSFR, TRUE); /* enabling Rx FIFO for receiving*/
432  IfxAsclin_Lin_waitForReceivedHeader(asclin); /* waiting until receive header end acknowledgemnet*/
433  IfxAsclin_read8(asclinSFR, id, 1U); /*reading the ID byte*/
434 }
435 
436 
438 {
439  Ifx_ASCLIN *asclinSFR = asclin->asclin; /* getting the pointer to ASCLIN registers from module handler*/
440  IfxAsclin_setDataLength(asclinSFR, length - 1); /* set number of bytes to be received*/
441  IfxAsclin_clearAllFlags(asclinSFR); /* clear all flags */
442  IfxAsclin_flushRxFifo(asclinSFR); /* flushing Rx FIFO */
443  IfxAsclin_enableTxFifoOutlet(asclinSFR, FALSE); /* enable Tx FIFO for transmitting */
444  IfxAsclin_enableRxFifoInlet(asclinSFR, TRUE); /* enable Rx FIFO for receiving */
445  IfxAsclin_Lin_waitForReceivedResponse(asclin); /* wait until receive response end acknowledgemnet or an error is occured*/
446  IfxAsclin_read8(asclinSFR, data, length); /* read the data bytes; */
447 }
448 
449 
451 {
452  Ifx_ASCLIN *asclinSFR = asclin->asclin; /* getting the pointer to ASCLIN registers from module handler*/
453  IfxAsclin_clearAllFlags(asclinSFR); /* clearing all flags*/
454 
455  if (asclin->receiveIdEnable) /* if receiving the sent id byte into its own Rx FIFO is selected*/
456  {
457  IfxAsclin_flushRxFifo(asclinSFR); /* flushing Rx FIFO*/
458  IfxAsclin_enableRxFifoInlet(asclinSFR, TRUE); /* enabling Rx FIFO */
459  }
460  else
461  {
462  IfxAsclin_enableRxFifoInlet(asclinSFR, FALSE); /* disabling Rx FIFO */
463  }
464 
465  IfxAsclin_flushTxFifo(asclinSFR); /* flushing Tx FIFO */
466  IfxAsclin_enableTxFifoOutlet(asclinSFR, TRUE); /* enabling Tx FIFO for transmitting*/
467  IfxAsclin_write8(asclinSFR, id, 1U); /* writing the ID byte */
468  IfxAsclin_setTransmitHeaderRequestFlag(asclinSFR); /* setting THRQS flag */
469  IfxAsclin_Lin_waitForTransmittedHeader(asclin); /* waiting until transmit header end acknowledgemnet */
470 }
471 
472 
474 {
475  Ifx_ASCLIN *asclinSFR = asclin->asclin; /* getting the pointer to ASCLIN registers from module handler*/
476  IfxAsclin_setDataLength(asclinSFR, length - 1); /* set number of bytes to be transfered */
477  IfxAsclin_clearAllFlags(asclinSFR); /* clear all flags */
478  IfxAsclin_flushTxFifo(asclinSFR); /* flushing Tx FIFO */
479  IfxAsclin_enableRxFifoInlet(asclinSFR, FALSE); /* disable Rx FIFO */
480  IfxAsclin_enableTxFifoOutlet(asclinSFR, TRUE); /* enable Tx FIFO for transmitting */
481  IfxAsclin_write8(asclinSFR, data, length); /* write the data bytes; */
482  IfxAsclin_setTransmitResponseRequestFlag(asclinSFR); /* set TRRQS flag */
483  IfxAsclin_Lin_waitForTransmittedResponse(asclin); /* wait until transmit response end acknowledgemnet */
484 }
485 
486 
488 {
489  IfxAsclin_Lin_clearFlagsStatus(asclin); /* clear all aknowledgement and error flags status */
490 
491  /* wait until receive header end acknowledgemnet has been detected */
492  while (asclin->acknowledgmentFlags.rxHeaderEnd != 1)
493  {
495  }
496 }
497 
498 
500 {
501  IfxAsclin_Lin_clearFlagsStatus(asclin); /* clear all aknowledgement and error flags status */
502 
503  /* wait until receive response end acknowledgemnet has been detected */
504  while (asclin->acknowledgmentFlags.rxResponseEnd != 1)
505  {
507  }
508 }
509 
510 
512 {
513  IfxAsclin_Lin_clearFlagsStatus(asclin); /* clear all aknowledgement and error flags status */
514 
515  /* wait until transmit header end acknowledgemnet has been detected */
516  while (asclin->acknowledgmentFlags.txHeaderEnd != 1)
517  {
519  }
520 }
521 
522 
524 {
525  IfxAsclin_Lin_clearFlagsStatus(asclin); /* clear all aknowledgement and error flags status */
526 
527  /* wait until transmit response end acknowledgemnet has been detected */
528  while (asclin->acknowledgmentFlags.txResponseEnd != 1)
529  {
531  }
532 }