iLLD_TC27xC  1.0
IfxDsadc_PinMap.c
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1 /**
2  * \file IfxDsadc_PinMap.c
3  * \brief DSADC I/O map
4  * \ingroup IfxLld_Dsadc
5  *
6  * \version iLLD_0_1_0_10
7  * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
8  *
9  *
10  * IMPORTANT NOTICE
11  *
12  *
13  * Infineon Technologies AG (Infineon) is supplying this file for use
14  * exclusively with Infineon's microcontroller products. This file can be freely
15  * distributed within development tools that are supporting such microcontroller
16  * products.
17  *
18  * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
19  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
20  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
21  * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
22  * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
23  *
24  */
25 
26 #include "IfxDsadc_PinMap.h"
27 
34 IfxDsadc_Cin_In IfxDsadc_CIN0A_P00_11_IN = {&MODULE_DSADC, 0, {&MODULE_P00,11}, Ifx_RxSel_a};
35 IfxDsadc_Cin_In IfxDsadc_CIN0B_P33_5_IN = {&MODULE_DSADC, 0, {&MODULE_P33, 5}, Ifx_RxSel_b};
36 IfxDsadc_Cin_In IfxDsadc_CIN1A_P00_9_IN = {&MODULE_DSADC, 1, {&MODULE_P00, 9}, Ifx_RxSel_a};
37 IfxDsadc_Cin_In IfxDsadc_CIN1B_P33_3_IN = {&MODULE_DSADC, 1, {&MODULE_P33, 3}, Ifx_RxSel_b};
38 IfxDsadc_Cin_In IfxDsadc_CIN2A_P00_5_IN = {&MODULE_DSADC, 2, {&MODULE_P00, 5}, Ifx_RxSel_a};
39 IfxDsadc_Cin_In IfxDsadc_CIN2B_P33_1_IN = {&MODULE_DSADC, 2, {&MODULE_P33, 1}, Ifx_RxSel_b};
40 IfxDsadc_Cin_In IfxDsadc_CIN3A_P00_3_IN = {&MODULE_DSADC, 3, {&MODULE_P00, 3}, Ifx_RxSel_a};
41 IfxDsadc_Cin_In IfxDsadc_CIN3B_P02_7_IN = {&MODULE_DSADC, 3, {&MODULE_P02, 7}, Ifx_RxSel_b};
42 IfxDsadc_Cin_In IfxDsadc_CIN4A_P00_7_IN = {&MODULE_DSADC, 4, {&MODULE_P00, 7}, Ifx_RxSel_a};
43 IfxDsadc_Cin_In IfxDsadc_CIN4B_P02_5_IN = {&MODULE_DSADC, 4, {&MODULE_P02, 5}, Ifx_RxSel_b};
44 IfxDsadc_Cin_In IfxDsadc_CIN5A_P00_1_IN = {&MODULE_DSADC, 5, {&MODULE_P00, 1}, Ifx_RxSel_a};
45 IfxDsadc_Cin_In IfxDsadc_CIN5B_P02_3_IN = {&MODULE_DSADC, 5, {&MODULE_P02, 3}, Ifx_RxSel_b};
46 IfxDsadc_Cout_Out IfxDsadc_COUT0_P00_11_OUT = {&MODULE_DSADC, 0, {&MODULE_P00,11}, IfxPort_OutputIdx_alt4};
47 IfxDsadc_Cout_Out IfxDsadc_COUT0_P33_5_OUT = {&MODULE_DSADC, 0, {&MODULE_P33, 5}, IfxPort_OutputIdx_alt4};
48 IfxDsadc_Cout_Out IfxDsadc_COUT1_P00_9_OUT = {&MODULE_DSADC, 1, {&MODULE_P00, 9}, IfxPort_OutputIdx_alt4};
49 IfxDsadc_Cout_Out IfxDsadc_COUT1_P33_3_OUT = {&MODULE_DSADC, 1, {&MODULE_P33, 3}, IfxPort_OutputIdx_alt4};
50 IfxDsadc_Cout_Out IfxDsadc_COUT2_P00_5_OUT = {&MODULE_DSADC, 2, {&MODULE_P00, 5}, IfxPort_OutputIdx_alt4};
51 IfxDsadc_Cout_Out IfxDsadc_COUT2_P33_1_OUT = {&MODULE_DSADC, 2, {&MODULE_P33, 1}, IfxPort_OutputIdx_alt4};
52 IfxDsadc_Cout_Out IfxDsadc_COUT3_P00_3_OUT = {&MODULE_DSADC, 3, {&MODULE_P00, 3}, IfxPort_OutputIdx_alt4};
53 IfxDsadc_Cout_Out IfxDsadc_COUT3_P02_7_OUT = {&MODULE_DSADC, 3, {&MODULE_P02, 7}, IfxPort_OutputIdx_alt4};
54 IfxDsadc_Cout_Out IfxDsadc_COUT4_P00_7_OUT = {&MODULE_DSADC, 4, {&MODULE_P00, 7}, IfxPort_OutputIdx_alt4};
55 IfxDsadc_Cout_Out IfxDsadc_COUT4_P02_5_OUT = {&MODULE_DSADC, 4, {&MODULE_P02, 5}, IfxPort_OutputIdx_alt4};
56 IfxDsadc_Cout_Out IfxDsadc_COUT5_P00_1_OUT = {&MODULE_DSADC, 5, {&MODULE_P00, 1}, IfxPort_OutputIdx_alt4};
57 IfxDsadc_Cout_Out IfxDsadc_COUT5_P02_3_OUT = {&MODULE_DSADC, 5, {&MODULE_P02, 3}, IfxPort_OutputIdx_alt4};
58 IfxDsadc_Din_In IfxDsadc_DIN0A_P00_12_IN = {&MODULE_DSADC, 0, {&MODULE_P00,12}, Ifx_RxSel_a};
59 IfxDsadc_Din_In IfxDsadc_DIN0B_P33_6_IN = {&MODULE_DSADC, 0, {&MODULE_P33, 6}, Ifx_RxSel_b};
60 IfxDsadc_Din_In IfxDsadc_DIN1A_P00_10_IN = {&MODULE_DSADC, 1, {&MODULE_P00,10}, Ifx_RxSel_a};
61 IfxDsadc_Din_In IfxDsadc_DIN1B_P33_4_IN = {&MODULE_DSADC, 1, {&MODULE_P33, 4}, Ifx_RxSel_b};
62 IfxDsadc_Din_In IfxDsadc_DIN2A_P00_6_IN = {&MODULE_DSADC, 2, {&MODULE_P00, 6}, Ifx_RxSel_a};
63 IfxDsadc_Din_In IfxDsadc_DIN2B_P33_2_IN = {&MODULE_DSADC, 2, {&MODULE_P33, 2}, Ifx_RxSel_b};
64 IfxDsadc_Din_In IfxDsadc_DIN3A_P00_4_IN = {&MODULE_DSADC, 3, {&MODULE_P00, 4}, Ifx_RxSel_a};
65 IfxDsadc_Din_In IfxDsadc_DIN3B_P02_8_IN = {&MODULE_DSADC, 3, {&MODULE_P02, 8}, Ifx_RxSel_b};
66 IfxDsadc_Din_In IfxDsadc_DIN4A_P00_8_IN = {&MODULE_DSADC, 4, {&MODULE_P00, 8}, Ifx_RxSel_a};
67 IfxDsadc_Din_In IfxDsadc_DIN4B_P02_6_IN = {&MODULE_DSADC, 4, {&MODULE_P02, 6}, Ifx_RxSel_b};
68 IfxDsadc_Din_In IfxDsadc_DIN5A_P00_2_IN = {&MODULE_DSADC, 5, {&MODULE_P00, 2}, Ifx_RxSel_a};
69 IfxDsadc_Din_In IfxDsadc_DIN5B_P02_4_IN = {&MODULE_DSADC, 5, {&MODULE_P02, 4}, Ifx_RxSel_b};
74 IfxDsadc_Dsn_In IfxDsadc_DS2NB_P40_1_IN = {&MODULE_DSADC, 2, {&MODULE_P40, 1}, Ifx_RxSel_b};
76 IfxDsadc_Dsn_In IfxDsadc_DS3NA_P40_7_IN = {&MODULE_DSADC, 3, {&MODULE_P40, 7}, Ifx_RxSel_a};
78 IfxDsadc_Dsn_In IfxDsadc_DS3NB_P40_9_IN = {&MODULE_DSADC, 3, {&MODULE_P40, 9}, Ifx_RxSel_b};
81 IfxDsadc_Dsn_In IfxDsadc_DS4NA_P00_7_IN = {&MODULE_DSADC, 4, {&MODULE_P00, 7}, Ifx_RxSel_a};
82 IfxDsadc_Dsn_In IfxDsadc_DS5NA_P00_1_IN = {&MODULE_DSADC, 5, {&MODULE_P00, 1}, Ifx_RxSel_a};
87 IfxDsadc_Dsp_In IfxDsadc_DS2PB_P40_0_IN = {&MODULE_DSADC, 2, {&MODULE_P40, 0}, Ifx_RxSel_b};
89 IfxDsadc_Dsp_In IfxDsadc_DS3PA_P40_6_IN = {&MODULE_DSADC, 3, {&MODULE_P40, 6}, Ifx_RxSel_a};
91 IfxDsadc_Dsp_In IfxDsadc_DS3PB_P40_8_IN = {&MODULE_DSADC, 3, {&MODULE_P40, 8}, Ifx_RxSel_b};
94 IfxDsadc_Dsp_In IfxDsadc_DS4PA_P00_8_IN = {&MODULE_DSADC, 4, {&MODULE_P00, 8}, Ifx_RxSel_a};
95 IfxDsadc_Dsp_In IfxDsadc_DS5PA_P00_2_IN = {&MODULE_DSADC, 5, {&MODULE_P00, 2}, Ifx_RxSel_a};
96 IfxDsadc_Itr_In IfxDsadc_ITR0E_P33_0_IN = {&MODULE_DSADC, 0, {&MODULE_P33, 0}, Ifx_RxSel_e};
97 IfxDsadc_Itr_In IfxDsadc_ITR0F_P33_4_IN = {&MODULE_DSADC, 0, {&MODULE_P33, 4}, Ifx_RxSel_f};
98 IfxDsadc_Itr_In IfxDsadc_ITR1E_P33_1_IN = {&MODULE_DSADC, 1, {&MODULE_P33, 1}, Ifx_RxSel_e};
99 IfxDsadc_Itr_In IfxDsadc_ITR1F_P33_5_IN = {&MODULE_DSADC, 1, {&MODULE_P33, 5}, Ifx_RxSel_f};
100 IfxDsadc_Itr_In IfxDsadc_ITR2E_P33_2_IN = {&MODULE_DSADC, 2, {&MODULE_P33, 2}, Ifx_RxSel_e};
101 IfxDsadc_Itr_In IfxDsadc_ITR2F_P33_6_IN = {&MODULE_DSADC, 2, {&MODULE_P33, 6}, Ifx_RxSel_f};
102 IfxDsadc_Itr_In IfxDsadc_ITR3E_P02_8_IN = {&MODULE_DSADC, 3, {&MODULE_P02, 8}, Ifx_RxSel_e};
103 IfxDsadc_Itr_In IfxDsadc_ITR3F_P00_9_IN = {&MODULE_DSADC, 3, {&MODULE_P00, 9}, Ifx_RxSel_f};
104 IfxDsadc_Itr_In IfxDsadc_ITR4E_P02_7_IN = {&MODULE_DSADC, 4, {&MODULE_P02, 7}, Ifx_RxSel_e};
105 IfxDsadc_Itr_In IfxDsadc_ITR4F_P00_6_IN = {&MODULE_DSADC, 4, {&MODULE_P00, 6}, Ifx_RxSel_f};
106 IfxDsadc_Itr_In IfxDsadc_ITR5E_P02_6_IN = {&MODULE_DSADC, 5, {&MODULE_P02, 6}, Ifx_RxSel_e};
107 IfxDsadc_Itr_In IfxDsadc_ITR5F_P00_3_IN = {&MODULE_DSADC, 5, {&MODULE_P00, 3}, Ifx_RxSel_f};
108 IfxDsadc_Sg_In IfxDsadc_SGNA_P00_4_IN = {&MODULE_DSADC, {&MODULE_P00, 4}, Ifx_RxSel_a};
109 IfxDsadc_Sg_In IfxDsadc_SGNB_P33_13_IN = {&MODULE_DSADC, {&MODULE_P33,13}, Ifx_RxSel_b};
110 
111 
113  {
119  &IfxDsadc_CGPWMP_P33_12_OUT
120  }
121 };
122 
124  {
125  {
127  &IfxDsadc_CIN0B_P33_5_IN
128  },
129  {
131  &IfxDsadc_CIN1B_P33_3_IN
132  },
133  {
135  &IfxDsadc_CIN2B_P33_1_IN
136  },
137  {
139  &IfxDsadc_CIN3B_P02_7_IN
140  },
141  {
143  &IfxDsadc_CIN4B_P02_5_IN
144  },
145  {
147  &IfxDsadc_CIN5B_P02_3_IN
148  }
149  }
150 };
151 
153  {
154  {
156  &IfxDsadc_COUT0_P33_5_OUT
157  },
158  {
160  &IfxDsadc_COUT1_P33_3_OUT
161  },
162  {
164  &IfxDsadc_COUT2_P33_1_OUT
165  },
166  {
168  &IfxDsadc_COUT3_P02_7_OUT
169  },
170  {
172  &IfxDsadc_COUT4_P02_5_OUT
173  },
174  {
176  &IfxDsadc_COUT5_P02_3_OUT
177  }
178  }
179 };
180 
182  {
183  {
185  &IfxDsadc_DIN0B_P33_6_IN
186  },
187  {
189  &IfxDsadc_DIN1B_P33_4_IN
190  },
191  {
193  &IfxDsadc_DIN2B_P33_2_IN
194  },
195  {
197  &IfxDsadc_DIN3B_P02_8_IN
198  },
199  {
201  &IfxDsadc_DIN4B_P02_6_IN
202  },
203  {
205  &IfxDsadc_DIN5B_P02_4_IN
206  }
207  }
208 };
209 
211  {
212  {
214  NULL_PTR,
215  NULL_PTR,
216  NULL_PTR
217  },
218  {
220  NULL_PTR,
221  NULL_PTR,
222  NULL_PTR
223  },
224  {
227  NULL_PTR,
228  NULL_PTR
229  },
230  {
234  &IfxDsadc_DS3ND_AN47_IN
235  },
236  {
238  NULL_PTR,
239  NULL_PTR,
240  NULL_PTR
241  },
242  {
244  NULL_PTR,
245  NULL_PTR,
246  NULL_PTR
247  }
248  }
249 };
250 
252  {
253  {
255  NULL_PTR,
256  NULL_PTR,
257  NULL_PTR
258  },
259  {
261  NULL_PTR,
262  NULL_PTR,
263  NULL_PTR
264  },
265  {
268  NULL_PTR,
269  NULL_PTR
270  },
271  {
275  &IfxDsadc_DS3PD_AN46_IN
276  },
277  {
279  NULL_PTR,
280  NULL_PTR,
281  NULL_PTR
282  },
283  {
285  NULL_PTR,
286  NULL_PTR,
287  NULL_PTR
288  }
289  }
290 };
291 
293  {
294  {
295  NULL_PTR,
296  NULL_PTR,
297  NULL_PTR,
298  NULL_PTR,
300  &IfxDsadc_ITR0F_P33_4_IN
301  },
302  {
303  NULL_PTR,
304  NULL_PTR,
305  NULL_PTR,
306  NULL_PTR,
308  &IfxDsadc_ITR1F_P33_5_IN
309  },
310  {
311  NULL_PTR,
312  NULL_PTR,
313  NULL_PTR,
314  NULL_PTR,
316  &IfxDsadc_ITR2F_P33_6_IN
317  },
318  {
319  NULL_PTR,
320  NULL_PTR,
321  NULL_PTR,
322  NULL_PTR,
324  &IfxDsadc_ITR3F_P00_9_IN
325  },
326  {
327  NULL_PTR,
328  NULL_PTR,
329  NULL_PTR,
330  NULL_PTR,
332  &IfxDsadc_ITR4F_P00_6_IN
333  },
334  {
335  NULL_PTR,
336  NULL_PTR,
337  NULL_PTR,
338  NULL_PTR,
340  &IfxDsadc_ITR5F_P00_3_IN
341  }
342  }
343 };
344 
346  {
348  &IfxDsadc_SGNB_P33_13_IN
349  }
350 };