iLLD_TC27xC  1.0
IfxScuCcu.h
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1 /**
2  * \file IfxScuCcu.h
3  * \brief SCU basic functionality
4  * \ingroup IfxLld_Scu
5  *
6  * \version iLLD_0_1_0_10
7  * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
8  *
9  *
10  * IMPORTANT NOTICE
11  *
12  *
13  * Infineon Technologies AG (Infineon) is supplying this file for use
14  * exclusively with Infineon's microcontroller products. This file can be freely
15  * distributed within development tools that are supporting such microcontroller
16  * products.
17  *
18  * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
19  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
20  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
21  * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
22  * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
23  *
24  *
25  * \defgroup IfxLld_Scu SCU
26  * \ingroup IfxLld
27  * \defgroup IfxLld_Scu_Std Standard Driver
28  * \ingroup IfxLld_Scu
29  * \defgroup IfxLld_Scu_Std_Ccu Clock Control Functions
30  * \ingroup IfxLld_Scu_Std
31  * \defgroup IfxLld_Scu_Std_Ccu_Operative Clock Control Operative Functions
32  * \ingroup IfxLld_Scu_Std
33  * \defgroup IfxLld_Scu_Std_Ccu_Configuration Clock Control Configuration Functions
34  * \ingroup IfxLld_Scu_Std
35  */
36 
37 #ifndef IFXSCUCCU_H
38 #define IFXSCUCCU_H 1
39 
40 /******************************************************************************/
41 /*----------------------------------Includes----------------------------------*/
42 /******************************************************************************/
43 
44 #include "_Impl/IfxScu_cfg.h"
45 #include "Scu/Std/IfxScuWdt.h"
46 #include "Cpu/Std/IfxCpu.h"
47 #include "IfxScu_reg.h"
48 
49 /******************************************************************************/
50 /*-----------------------------------Macros-----------------------------------*/
51 /******************************************************************************/
52 
53 /** \brief Oscillator stability check timeout count
54  */
55 #define IFXSCUCCU_OSC_STABLECHK_TIME (640)
56 
57 /******************************************************************************/
58 /*------------------------------Type Definitions------------------------------*/
59 /******************************************************************************/
60 
61 /** \brief Function pointer type for the hooks
62  * \return None
63  */
64 typedef void (*IfxScuCcu_PllStepsFunctionHook)(void);
65 
66 /******************************************************************************/
67 /*-------------------------------Enumerations---------------------------------*/
68 /******************************************************************************/
69 
70 /******************************************************************************/
71 /*-----------------------------Data Structures--------------------------------*/
72 /******************************************************************************/
73 
74 /** \addtogroup IfxLld_Scu_Std_Ccu
75  * \{ */
76 /** \brief Configuration structure type for CCUCON registers.
77  */
78 typedef struct
79 {
80  uint32 value; /**< \brief CCUCON Register value to be updated. */
81  uint32 mask; /**< \brief CCUCON Mask to select the bit fields to be updated. */
83 
84 /** \} */
85 
86 /** \addtogroup IfxLld_Scu_Std_Ccu
87  * \{ */
88 /** \brief Configuration structure type for all the CCUCON registers to configure clock distribution.
89  */
90 typedef struct
91 {
92  IfxScuCcu_CcuconRegConfig ccucon0; /**< \brief CCUCON0 Register configuration */
93  IfxScuCcu_CcuconRegConfig ccucon1; /**< \brief CCUCON1 Register configuration */
94  IfxScuCcu_CcuconRegConfig ccucon2; /**< \brief CCUCON2 Register configuration */
95  IfxScuCcu_CcuconRegConfig ccucon5; /**< \brief CCUCON5 Register configuration */
96  IfxScuCcu_CcuconRegConfig ccucon6; /**< \brief CCUCON6 Register configuration */
97  IfxScuCcu_CcuconRegConfig ccucon7; /**< \brief CCUCON7 Register configuration */
98  IfxScuCcu_CcuconRegConfig ccucon8; /**< \brief CCUCON8 Register configuration */
100 
101 /** \brief Configuration structure type for the Flash waitstate configuration.
102  */
103 typedef struct
104 {
105  uint32 value; /**< \brief FLASH.FCON Register value to be updated. */
106  uint32 mask; /**< \brief FLASH.FCON Mask to select the bit fields to be updated. */
108 
109 /** \brief Configuration structure type for the Pll initial step.
110  * This structure must be used to configure the P, N and K2 dividers for initial step.
111  */
112 typedef struct
113 {
114  uint8 pDivider; /**< \brief P divider value for basic (initial) step */
115  uint8 nDivider; /**< \brief N divider value for basic (initial) step */
116  uint8 k2Initial; /**< \brief K2 divider value for basic (initial) step */
117  float32 waitTime; /**< \brief Wait time for for basic (initial) step */
119 
120 /** \brief Configuration structure type for the Pll Steps for current jump control.
121  */
122 typedef struct
123 {
124  uint8 k2Step; /**< \brief K2 divider value for this step. */
125  float32 waitTime; /**< \brief Wait time for for this step. */
126  IfxScuCcu_PllStepsFunctionHook hookFunction; /**< \brief Hook function called at the end of this step. */
128 
129 /** \} */
130 
131 /** \addtogroup IfxLld_Scu_Std_Ccu
132  * \{ */
133 /** \brief Configuration structure SCU module
134  */
135 typedef struct
136 {
137  uint8 numOfPllDividerSteps; /**< \brief Number of PLL divider steps during clock throttling. */
138  IfxScuCcu_PllStepsConfig *pllDividerStep; /**< \brief Pointer to the array of Pll divider step configuration. */
139  IfxScuCcu_InitialStepConfig pllInitialStep; /**< \brief Configuration of first step which is same as internal osc frequency. */
140  IfxScuCcu_ClockDistributionConfig clockDistribution; /**< \brief Configuration of of bus clocks and other module clock distribution. */
141  IfxScuCcu_FlashWaitstateConfig flashFconWaitStateConfig; /**< \brief Configuration of flash waitstate */
143 
144 /** \brief Configuration structure for E-ray PLL
145  */
146 typedef struct
147 {
148  IfxScuCcu_InitialStepConfig pllInitialStep; /**< \brief Configuration of first step which is same as internal osc frequency. */
150 
151 /** \} */
152 
153 /** \addtogroup IfxLld_Scu_Std_Ccu_Operative
154  * \{ */
155 
156 /******************************************************************************/
157 /*-------------------------Inline Function Prototypes-------------------------*/
158 /******************************************************************************/
159 
160 /** \brief API to get EVR Oscillator frequency.
161  * This API returns the constant which is specific to the ScuCcu of the controller.
162  * \return EVR Oscillator frequency (fBACK or fEVR) in Hz.
163  */
165 
166 /** \brief API to get Oscillator 0 frequency.
167  * This API returns the fOsc0 frequency based on the divider value in CCUCON register and the input oscillator.
168  * \return Osc0 frequency (fOSC0) in Hz.
169  */
171 
172 /** \brief API to get Oscillator 0 frequency.
173  * This API returns the fOsc0 frequency based on the divider value in CCUCON register and the input oscillator.
174  * \return Osc frequency (fOSC) in Hz.
175  */
177 
178 /** \brief API to get actual PLL2 (K3 Divider for ADC clock) frequency
179  * This API returns the PLL2ERAY frequency based on the K3 divider value in PLLERAYCON and the VCO frequency. This frequency is one of the configurable inputs to ADC clock.
180  * \return PLL2ERAY (K3 Divider for ADC clock) frequency in Hz
181  */
183 
184 /** \brief API to get actual PLL2 (K3 Divider for ADC clock) frequency
185  * This API returns the PLL2 frequency based on the K3 divider value in PLLCON and the VCO frequency. This frequency is one of the configurable inputs to ADC clock.
186  * \return PLL2 (K3 Divider for ADC clock) frequency in Hz
187  */
189 
190 /** \brief API to get STM divider frequency.
191  * This API returns the based on the divider value in CCUCON register and fSOURCE.
192  * \return STM frequency (fSTM) in Hz
193  */
195 
196 /******************************************************************************/
197 /*-------------------------Global Function Prototypes-------------------------*/
198 /******************************************************************************/
199 
200 /** \brief API to get BAUD1 divider frequency.
201  * This API returns the based on the divider value in CCUCON register and the input oscillator.
202  * \return Baud1 frequency in Hz
203  */
205 
206 /** \brief API to get BAUD2 divider frequency.
207  * This API returns the Baud2 frequency based on the divider value in CCUCON register and the fMAX.
208  * \return Baud2 frequency in Hz
209  */
211 
212 /** \brief API to get BBB divider frequency.
213  * This API returns the BBBDivider frequency based on the divider value in CCUCON register and the input oscillator.
214  * \return BBB frequency (fBBB) in Hz
215  */
217 
218 /** \brief This API returns the Cpu frequency based on the divider value in CCUCON register and fSource frequency
219  * \param cpu CPU number for which effective fCPU is sought
220  * \return Cpu[x] frequency in Hz, where x is cpu number passed as parameter
221  */
223 
224 /** \brief API to get FSI2 divider frequency in Hz.
225  * This API returns the fFSI2 frequency based on the divider value in CCUCON register and the input oscillator.
226  * \return FSI2 frequency (fFSI2) in Hz.
227  */
229 
230 /** \brief API to get FSI divider frequency in Hz.
231  * This API returns the fFSI based on the divider value in CCUCON register and the input oscillator.
232  * \return FSI frequency (fFSI) in Hz.
233  */
235 
236 /** \brief API to get FMAX divider frequency.
237  * This API returns the fMax frequency based on the divider value in CCUCON register and the input oscillator.
238  * \return Max frequency (fMAX) in Hz.
239  */
241 
242 /** \brief get source frequency fSOURCE.
243  * This API returns the source frequency based on the configurations with CCUCON register configuration.
244  * \return Module frequency in Hz
245  */
247 
248 /** \brief API to get actual PLL (Eray) frequency.
249  * This API returns the based on the divider values in CCUCON, PLLCON registers and the input oscillator.
250  * \return frequency of Pll Eray (fPLLERAY) in Hz
251  */
253 
254 /** \brief API to get actual ERAY PLL Voltage Controlled Oscillator frequency.
255  * This API returns the based on the divider values in PLLERAYCON registers and the input oscillator.
256  * \return Pll (Eray) VCO frequency
257  */
259 
260 /** \brief API to get actual PLL output frequency.
261  * This API returns the based on the divider values in CCUCON, PLLCON registers and the input oscillator.
262  * \return Pll (fPLL) frequency in Hz
263  */
265 
266 /** \brief API to get actual PLL Voltage Controlled Oscillator frequency.
267  * This API returns the based on the divider values in PLLCON registers and the input oscillator.
268  * \return Pll VCO frequency
269  */
271 
272 /** \brief get source frequency fSOURCE.
273  * This API returns the source frequency based on the configurations with CCUCON register configuration.
274  * \return Effective fSOURCE in Hz
275  */
277 
278 /** \brief API to get SPB divider frequency.
279  * This API returns the based on fSOURCE and also on Low power divider mode and/or SPBDIV divider value in CCUCON registers.
280  * \return SPB frequency (fSPB) in Hz
281  */
283 
284 /** \brief API to get SRI divider frequency.
285  * This API returns the Sri frequency based on the divider values in CCUCON registers and fSOURCE.
286  * \return Sri frequency (fSRI) in Hz
287  */
289 
290 /** \brief API to set CPU frequency (with CPU divider)
291  * This API configure CPU divider values in CCUCON registers. The actual frequency is always depends on the feasibility with the divider value
292  * \param cpu CPU number for which fCPU to be configured
293  * \param cpuFreq Desired CPU frequency in Hz
294  * \return Actual CPU[x] frequency in Hz, where x is the cpu number passed as parameter
295  */
297 
298 /** \brief API to configure PLL2ERAY (K3 Divider for ADC clock) for desired frequency.
299  * This API configure K3 divider value in CCUCON. The actual frequency always depends on the feasibility with the divider value
300  * \param pll2ErayFreq PLL2ERAY (K3 Divider for ADC clock) frequency in Hz
301  * \return Actual PLL2 (K3 Divider for ADC clock) frequency in Hz
302  */
304 
305 /** \brief API to configure PLL2 (K3 Divider for ADC clock) for desired frequency.
306  * This API configure K3 divider value in CCUCON. The actual frequency always depends on the feasibility with the divider value
307  * \param pll2Freq PLL2 (K3 Divider for ADC clock) frequency in Hz
308  * \return Actual PLL2 (K3 Divider for ADC clock) frequency in Hz
309  */
311 
312 /** \brief API to set SPB frequency (with SPB divider)
313  * This API configure SPB divider values in CCUCON registers. The actual frequency always depends on the feasibility with the divider value
314  * \param spbFreq Desired SPB frequency in Hz
315  * \return Actual SPB frequency in Hz
316  */
318 
319 /** \} */
320 
321 /** \addtogroup IfxLld_Scu_Std_Ccu_Configuration
322  * \{ */
323 
324 /******************************************************************************/
325 /*-------------------------Global Function Prototypes-------------------------*/
326 /******************************************************************************/
327 
328 /** \brief API to initialize the SCU Clock Control Unit.
329  * This API initialize the PLL with ramp steps, BUS dividers for the configuration provided by the configuration structure.
330  * \param cfg Pointer to the configuration structure of the ScuCcu
331  * \return Error status of the ScuCcu initialization process.
332  * \retval TRUE: If an error occurred during initialization.
333  * \retval FALSE: If initialization was successful.
334  */
335 IFX_EXTERN boolean IfxScuCcu_init(const IfxScuCcu_Config *cfg);
336 
337 /** \brief Initializes the clock configuration with default values
338  * \param cfg Pointer to the configuration structure of the ScuCcu
339  * \return None
340  */
342 
343 /** \brief API to initialize the SCU Eray Pll
344  * This API initialize the Eray PLL for the configuration provided by the configuration structure.
345  * \param cfg Pointer to the configuration structure of the Eray Pll
346  * \return Error status of the ScuCcu Eray Pll initialization process.
347  * \retval TRUE: If an error occurred during initialization.
348  * \retval FALSE: If initialization was successful.
349  */
351 
352 /** \brief Initializes the clock configuration with default values
353  * \param cfg Pointer to the configuration structure of the ScuCcuEray Pll
354  * \return None
355  */
357 
358 /** \} */
359 
360 /******************************************************************************/
361 /*-------------------------Inline Function Prototypes-------------------------*/
362 /******************************************************************************/
363 
364 /** \brief API to get GTMdivider frequency
365  * This API returns the based on the divider value in CCUCON register and fSOURCE.
366  * return GTM frequency (fGTM) in Hz
367  */
369 
370 /******************************************************************************/
371 /*-------------------------Global Function Prototypes-------------------------*/
372 /******************************************************************************/
373 
374 /** \brief API to set GTM frequency (with GTM divider)
375  * This API configure GTM divider values in CCUCON registers. The actual frequency always depends on the feasibility with the divider value
376  * \param gtmFreq Desired GTM frequency in Hz
377  * \return Actual GTM frequency in HZ
378  */
380 
381 /******************************************************************************/
382 /*-------------------Global Exported Variables/Constants----------------------*/
383 /******************************************************************************/
384 
385 /** \brief Configuration structure for SCU CCU driver.
386  * The values of this structure are defined as # defined macros in the implementation of Scu
387  */
389 
390 /** \brief Configuration structure for SCU CCU driver.
391  * The values of this structure are defined as # defined macros in the implementation of Scu
392  */
394 
395 /******************************************************************************/
396 /*---------------------Inline Function Implementations------------------------*/
397 /******************************************************************************/
398 
400 {
402 }
403 
404 
406 {
408 }
409 
410 
412 {
413  float32 freq;
414 
415  if (SCU_CCUCON1.B.INSEL == IfxScu_CCUCON1_INSEL_fOsc1)
416  {
418  }
419  else if (SCU_CCUCON1.B.INSEL == IfxScu_CCUCON1_INSEL_fOsc0)
420  {
422  }
423  else
424  {
425  /* Reserved values, this */
426  freq = 0.0;
427  }
428 
429  return freq;
430 }
431 
432 
434 {
435  float32 pll2ErayFrequency;
436 
437  pll2ErayFrequency = IfxScuCcu_getPllErayVcoFrequency() / (SCU_PLLERAYCON1.B.K3DIV + 1);
438 
439  return pll2ErayFrequency;
440 }
441 
442 
444 {
445  float32 pll2Frequency;
446 
447  pll2Frequency = IfxScuCcu_getPllVcoFrequency() / (SCU_PLLCON1.B.K3DIV + 1);
448 
449  return pll2Frequency;
450 }
451 
452 
454 {
455  return IfxScuCcu_getSourceFrequency() / SCU_CCUCON1.B.STMDIV;
456 }
457 
458 
460 {
461  return IfxScuCcu_getSourceFrequency() / SCU_CCUCON1.B.GTMDIV;
462 }
463 
464 
465 #endif /* IFXSCUCCU_H */