iLLD_TC27xC  1.0
IfxGtm_Atom.c
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1 /**
2  * \file IfxGtm_Atom.c
3  * \brief GTM basic functionality
4  *
5  * \version iLLD_0_1_0_10
6  * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
7  *
8  *
9  * IMPORTANT NOTICE
10  *
11  *
12  * Infineon Technologies AG (Infineon) is supplying this file for use
13  * exclusively with Infineon's microcontroller products. This file can be freely
14  * distributed within development tools that are supporting such microcontroller
15  * products.
16  *
17  * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
18  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
19  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
20  * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
21  * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
22  *
23  */
24 
25 /******************************************************************************/
26 /*----------------------------------Includes----------------------------------*/
27 /******************************************************************************/
28 
29 #include "IfxGtm_Atom.h"
30 #include "_Reg/IfxGtm_bf.h"
31 
32 /******************************************************************************/
33 /*----------------------------------Macros------------------------------------*/
34 /******************************************************************************/
35 
36 /** \brief Number of channels per ATOM AGC
37  */
38 #define IFXGTM_ATOM_AGC_CHANNEL_COUNT (8)
39 
40 /** \addtogroup IfxLld_Gtm_Std_Atom_AGC_Functions
41  * \{ */
42 
43 /******************************************************************************/
44 /*-----------------------Private Function Prototypes--------------------------*/
45 /******************************************************************************/
46 
47 /** \brief Builds the register value for the feature enable/disable
48  * \param enableMask Mask for the channel feature enable (bit 0: Channel 0, bit 1: channel 1, ...)
49  * \param disableMask Mask for the channel feature disable (bit 0: Channel 0, bit 1: channel 1, ...)
50  * \param bitfieldOffset Offset of the channel 0 bitfield in the register
51  * \return The register value
52  */
53 static uint32 IfxGtm_Atom_Agc_buildFeature(uint16 enableMask, uint16 disableMask, uint8 bitfieldOffset);
54 
55 /** \} */
56 
57 /******************************************************************************/
58 /*-------------------------Function Implementations---------------------------*/
59 /******************************************************************************/
60 
61 static uint32 IfxGtm_Atom_Agc_buildFeature(uint16 enableMask, uint16 disableMask, uint8 bitfieldOffset)
62 {
63  uint8 i;
64  uint32 reg = 0;
65  uint32 mask = enableMask | (disableMask << 16);
66 
67  for (i = 0; i < IFXGTM_ATOM_AGC_CHANNEL_COUNT; i++)
68  {
69  /* Bitfield length is 2 bits */
70  uint8 shift = (i * 2) + bitfieldOffset;
71 
72  if (mask & 0x1)
73  {
74  reg |= IfxGtm_FeatureControl_enable << shift;
75  }
76 
77  if (mask & 0x10000)
78  {
79  reg |= IfxGtm_FeatureControl_disable << shift;
80  }
81 
82  mask = mask >> 1;
83  }
84 
85  return reg;
86 }
87 
88 
89 void IfxGtm_Atom_Agc_enableChannels(Ifx_GTM_ATOM_AGC *agc, uint16 enableMask, uint16 disableMask, boolean immediate)
90 {
91  uint32 value;
92 
93  /* FIXME: Alann... is it possible to optimize, not always re-calculating the value using buildFeature function ? */
94 
95  value = IfxGtm_Atom_Agc_buildFeature(enableMask, disableMask, IFX_GTM_ATOM_AGC_ENDIS_CTRL_ENDIS_CTRL0_OFF);
96 
97  if (immediate)
98  {
99  agc->ENDIS_CTRL.U = value;
100  agc->ENDIS_STAT.U = value;
101  }
102  else
103  {
104  agc->ENDIS_CTRL.U = value;
105  }
106 }
107 
108 
109 void IfxGtm_Atom_Agc_enableChannelsOutput(Ifx_GTM_ATOM_AGC *agc, uint16 enableMask, uint16 disableMask, boolean immediate)
110 {
111  uint32 value;
112 
113  value = IfxGtm_Atom_Agc_buildFeature(enableMask, disableMask, IFX_GTM_ATOM_AGC_OUTEN_CTRL_OUTEN_CTRL0_OFF);
114 
115  if (immediate)
116  {
117  agc->OUTEN_CTRL.U = value;
118  agc->OUTEN_STAT.U = value;
119  }
120  else
121  {
122  agc->OUTEN_CTRL.U = value;
123  }
124 }
125 
126 
127 void IfxGtm_Atom_Agc_enableChannelsTrigger(Ifx_GTM_ATOM_AGC *agc, uint16 enableMask, uint16 disableMask)
128 {
129  agc->INT_TRIG.U = IfxGtm_Atom_Agc_buildFeature(enableMask, disableMask, IFX_GTM_ATOM_AGC_INT_TRIG_INT_TRIG0_OFF);
130 }
131 
132 
133 void IfxGtm_Atom_Agc_enableChannelsUpdate(Ifx_GTM_ATOM_AGC *agc, uint16 enableMask, uint16 disableMask)
134 {
135  agc->GLB_CTRL.U = IfxGtm_Atom_Agc_buildFeature(enableMask, disableMask, IFX_GTM_ATOM_AGC_GLB_CTRL_UPEN_CTRL0_OFF);
136 }
137 
138 
139 void IfxGtm_Atom_Agc_enableTimeTrigger(Ifx_GTM_ATOM_AGC *agc, boolean enabled)
140 {
141  agc->ACT_TB.B.TB_TRIG = enabled ? 1 : 0;
142 }
143 
144 
145 void IfxGtm_Atom_Agc_resetChannels(Ifx_GTM_ATOM_AGC *agc, uint32 resetMask)
146 {
147  uint8 i;
148  uint32 reg = 0;
149 
150  for (i = 0; i < IFXGTM_ATOM_AGC_CHANNEL_COUNT; i++)
151  {
152  if (resetMask & 0x1)
153  {
154  reg |= 1 << i;
155  }
156 
157  resetMask = resetMask >> 1;
158  }
159 
160  agc->GLB_CTRL.U = reg << IFX_GTM_ATOM_AGC_GLB_CTRL_RST_CH0_OFF;
161 }
162 
163 
164 void IfxGtm_Atom_Agc_setChannelsForceUpdate(Ifx_GTM_ATOM_AGC *agc, uint16 enableMask, uint16 disableMask, uint16 resetEnableMask, uint16 resetDisableMask)
165 {
166  uint32 regEnable, regReset;
167 
168  regEnable = IfxGtm_Atom_Agc_buildFeature(enableMask, disableMask, IFX_GTM_ATOM_AGC_FUPD_CTRL_FUPD_CTRL0_OFF);
169  regReset =
170  IfxGtm_Atom_Agc_buildFeature(resetEnableMask, resetDisableMask, IFX_GTM_ATOM_AGC_FUPD_CTRL_RSTCN0_CH0_OFF);
171  agc->FUPD_CTRL.U = regEnable | regReset;
172 }
173 
174 
175 void IfxGtm_Atom_Agc_setTimeTrigger(Ifx_GTM_ATOM_AGC *agc, IfxGtm_Tbu_Ts base, uint32 value)
176 {
177  Ifx_GTM_ATOM_AGC_ACT_TB act_tb;
178 
179  act_tb.U = agc->ACT_TB.U;
180  act_tb.B.TBU_SEL = base;
181  act_tb.B.ACT_TB = value;
182  agc->ACT_TB.U = act_tb.U;
183 }
184 
185 
186 void IfxGtm_Atom_Agc_trigger(Ifx_GTM_ATOM_AGC *agc)
187 {
188  agc->GLB_CTRL.U = 1 << IFX_GTM_ATOM_AGC_GLB_CTRL_HOST_TRIG_OFF;
189 }
190 
191 
192 void IfxGtm_Atom_Ch_clearOneNotification(Ifx_GTM_ATOM *atom, IfxGtm_Atom_Ch channel)
193 {
194  Ifx_GTM_ATOM_CH *atomCh = (Ifx_GTM_ATOM_CH *)((uint32)&atom->CH0.RDADDR.U + 0x80 * channel);
195 
196  atomCh->IRQ_NOTIFY.B.CCU1TC = 1;
197 }
198 
199 
200 void IfxGtm_Atom_Ch_clearZeroNotification(Ifx_GTM_ATOM *atom, IfxGtm_Atom_Ch channel)
201 {
202  Ifx_GTM_ATOM_CH *atomCh = (Ifx_GTM_ATOM_CH *)((uint32)&atom->CH0.RDADDR.U + 0x80 * channel);
203  atomCh->IRQ_NOTIFY.B.CCU0TC = 1;
204 }
205 
206 
208 {
209  Ifx_GTM_ATOM_CH_CTRL_Bits ctrl = {
211  .CLK_SRC = clock,
212  .RST_CCU0 = resetEvent,
213  .SL = (activeState == Ifx_ActiveState_high ? 1 : 0),
214  .TRIGOUT = trigger,
215  };
216  Ifx_GTM_ATOM_CH *atomCh = (Ifx_GTM_ATOM_CH *)((uint32)&atom->CH0.RDADDR.U + 0x80 * channel);
217 
218  atomCh->CTRL.B = ctrl;
219 }
220 
221 
222 float32 IfxGtm_Atom_Ch_getClockFrequency(Ifx_GTM *gtm, Ifx_GTM_ATOM *atom, IfxGtm_Atom_Ch channel)
223 {
224  IfxGtm_Cmu_Clk clock;
225 
226  clock = IfxGtm_Atom_Ch_getClockSource(atom, channel);
227 
228  return IfxGtm_Cmu_getClkFrequency(gtm, clock, TRUE);
229 }
230 
231 
233 {
234  IfxGtm_Cmu_Clk clock;
235  Ifx_GTM_ATOM_CH *atomCh = (Ifx_GTM_ATOM_CH *)((uint32)&atom->CH0.RDADDR.U + 0x80 * channel);
236 
237  clock = atomCh->CTRL.B.CLK_SRC;
238 
239  return clock;
240 }
241 
242 
243 boolean IfxGtm_Atom_Ch_getOutputLevel(Ifx_GTM_ATOM *atom, IfxGtm_Atom_Ch channel)
244 {
245  boolean result;
246  Ifx_GTM_ATOM_CH *atomCh = (Ifx_GTM_ATOM_CH *)((uint32)&atom->CH0.RDADDR.U + 0x80 * channel);
247 
248  result = atomCh->STAT.B.OL == 1;
249 
250  return result;
251 }
252 
253 
254 volatile Ifx_SRC_SRCR *IfxGtm_Atom_Ch_getSrcPointer(Ifx_GTM *gtm, IfxGtm_Atom atom, IfxGtm_Atom_Ch channel)
255 {
256  return &MODULE_SRC.GTM.GTM[0].ATOM[atom][channel / 2];
257 }
258 
259 
260 volatile uint32 *IfxGtm_Atom_Ch_getTimerPointer(Ifx_GTM_ATOM *atom, IfxGtm_Atom_Ch channel)
261 {
262  return (volatile uint32 *)((uint32)&(atom->CH0.CN0.U) + channel * (offsetof(Ifx_GTM_ATOM, CH1) - offsetof(Ifx_GTM_ATOM, CH0)));
263 }
264 
265 
266 boolean IfxGtm_Atom_Ch_isOneNotification(Ifx_GTM_ATOM *atom, IfxGtm_Atom_Ch channel)
267 {
268  boolean result;
269  Ifx_GTM_ATOM_CH *atomCh = (Ifx_GTM_ATOM_CH *)((uint32)&atom->CH0.RDADDR.U + 0x80 * channel);
270 
271  result = atomCh->IRQ_NOTIFY.B.CCU1TC != 0;
272 
273  return result;
274 }
275 
276 
277 boolean IfxGtm_Atom_Ch_isZeroNotification(Ifx_GTM_ATOM *atom, IfxGtm_Atom_Ch channel)
278 {
279  boolean result;
280  Ifx_GTM_ATOM_CH *atomCh = (Ifx_GTM_ATOM_CH *)((uint32)&atom->CH0.RDADDR.U + 0x80 * channel);
281 
282  result = atomCh->IRQ_NOTIFY.B.CCU0TC != 0;
283 
284  return result;
285 }
286 
287 
288 void IfxGtm_Atom_Ch_raiseInterruptOne(Ifx_GTM_ATOM *atom, IfxGtm_Atom_Ch channel)
289 {
290  Ifx_GTM_ATOM_CH *atomCh = (Ifx_GTM_ATOM_CH *)((uint32)&atom->CH0.RDADDR.U + 0x80 * channel);
291 
292  atomCh->IRQ_FORCINT.B.TRG_CCU1TC = 1;
293 }
294 
295 
296 void IfxGtm_Atom_Ch_raiseInterruptZero(Ifx_GTM_ATOM *atom, IfxGtm_Atom_Ch channel)
297 {
298  Ifx_GTM_ATOM_CH *atomCh = (Ifx_GTM_ATOM_CH *)((uint32)&atom->CH0.RDADDR.U + 0x80 * channel);
299 
300  atomCh->IRQ_FORCINT.B.TRG_CCU0TC = 1;
301 }
302 
303 
304 void IfxGtm_Atom_Ch_setClockSource(Ifx_GTM_ATOM *atom, IfxGtm_Atom_Ch channel, IfxGtm_Cmu_Clk clock)
305 {
306  Ifx_GTM_ATOM_CH *atomCh = (Ifx_GTM_ATOM_CH *)((uint32)&atom->CH0.RDADDR.U + 0x80 * channel);
307 
308  atomCh->CTRL.B.CLK_SRC = clock;
309 }
310 
311 
312 void IfxGtm_Atom_Ch_setCompare(Ifx_GTM_ATOM *atom, IfxGtm_Atom_Ch channel, uint32 compareZero, uint32 compareOne)
313 {
314  Ifx_GTM_ATOM_CH *atomCh = (Ifx_GTM_ATOM_CH *)((uint32)&atom->CH0.RDADDR.U + 0x80 * channel);
315 
316  atomCh->CM0.U = compareZero; // TK: replaced .B access to optimize runtime
317  atomCh->CM1.U = compareOne;
318 }
319 
320 
321 void IfxGtm_Atom_Ch_setCompareOne(Ifx_GTM_ATOM *atom, IfxGtm_Atom_Ch channel, uint32 compareOne)
322 {
323  Ifx_GTM_ATOM_CH *atomCh = (Ifx_GTM_ATOM_CH *)((uint32)&atom->CH0.RDADDR.U + 0x80 * channel);
324 
325  atomCh->CM1.U = compareOne; // TK: replaced .B access to optimize runtime
326 }
327 
328 
329 void IfxGtm_Atom_Ch_setCompareOneShadow(Ifx_GTM_ATOM *atom, IfxGtm_Atom_Ch channel, uint32 shadowOne)
330 {
331  Ifx_GTM_ATOM_CH *atomCh = (Ifx_GTM_ATOM_CH *)((uint32)&atom->CH0.RDADDR.U + 0x80 * channel);
332 
333  atomCh->SR1.U = shadowOne; // TK: replaced .B access to optimize runtime
334 }
335 
336 
337 void IfxGtm_Atom_Ch_setCompareShadow(Ifx_GTM_ATOM *atom, IfxGtm_Atom_Ch channel, uint32 shadowZero, uint32 shadowOne)
338 {
339  Ifx_GTM_ATOM_CH *atomCh = (Ifx_GTM_ATOM_CH *)((uint32)&atom->CH0.RDADDR.U + 0x80 * channel);
340 
341  atomCh->SR0.U = shadowZero; // TK: replaced .B access to optimize runtime
342  atomCh->SR1.U = shadowOne;
343 }
344 
345 
346 void IfxGtm_Atom_Ch_setCompareZero(Ifx_GTM_ATOM *atom, IfxGtm_Atom_Ch channel, uint32 compareZero)
347 {
348  Ifx_GTM_ATOM_CH *atomCh = (Ifx_GTM_ATOM_CH *)((uint32)&atom->CH0.RDADDR.U + 0x80 * channel);
349 
350  atomCh->CM0.U = compareZero; // TK: replaced .B access to optimize runtime
351 }
352 
353 
354 void IfxGtm_Atom_Ch_setCompareZeroShadow(Ifx_GTM_ATOM *atom, IfxGtm_Atom_Ch channel, uint32 shadowZero)
355 {
356  Ifx_GTM_ATOM_CH *atomCh = (Ifx_GTM_ATOM_CH *)((uint32)&atom->CH0.RDADDR.U + 0x80 * channel);
357 
358  atomCh->SR0.U = shadowZero; // TK: replaced .B access to optimize runtime
359 }
360 
361 
362 void IfxGtm_Atom_Ch_setCounterValue(Ifx_GTM_ATOM *atom, IfxGtm_Atom_Ch channel, uint32 value)
363 {
364  Ifx_GTM_ATOM_CH *atomCh = (Ifx_GTM_ATOM_CH *)((uint32)&atom->CH0.RDADDR.U + 0x80 * channel);
365 
366  atomCh->CN0.U = value; // TK: replaced .B access to optimize runtime
367 }
368 
369 
370 void IfxGtm_Atom_Ch_setNotification(Ifx_GTM_ATOM *atom, IfxGtm_Atom_Ch channel, IfxGtm_IrqMode mode, boolean interruptOnCompareZero, boolean interruptOnCompareOne)
371 {
372  Ifx_GTM_ATOM_CH *atomCh = (Ifx_GTM_ATOM_CH *)((uint32)&atom->CH0.RDADDR.U + 0x80 * channel);
373 
374  Ifx_GTM_ATOM_CH_IRQ_EN en;
375 
376  en.U = atomCh->IRQ_EN.U;
377 
378  /* Disable all interrupts of the interrupt set to change mode */
379  atomCh->IRQ_EN.U = ZEROS;
380  atomCh->IRQ_MODE.B.IRQ_MODE = mode;
381  atomCh->IRQ_EN.U = en.U; /* Set the values back */
382 
383  en.B.CCU0TC_IRQ_EN = interruptOnCompareZero ? 1 : 0;
384  en.B.CCU1TC_IRQ_EN = interruptOnCompareOne ? 1 : 0;
385  atomCh->IRQ_EN.U = en.U;
386 }
387 
388 
389 void IfxGtm_Atom_Ch_setOneShotMode(Ifx_GTM_ATOM *atom, IfxGtm_Atom_Ch channel, boolean enabled)
390 {
391  Ifx_GTM_ATOM_CH *atomCh = (Ifx_GTM_ATOM_CH *)((uint32)&atom->CH0.RDADDR.U + 0x80 * channel);
392 
393  atomCh->CTRL.B.OSM = enabled ? 1 : 0;
394 }
395 
396 
398 {
399  Ifx_GTM_ATOM_CH *atomCh = (Ifx_GTM_ATOM_CH *)((uint32)&atom->CH0.RDADDR.U + 0x80 * channel);
400 
401  atomCh->CTRL.B.RST_CCU0 = event;
402 }
403 
404 
405 void IfxGtm_Atom_Ch_setSignalLevel(Ifx_GTM_ATOM *atom, IfxGtm_Atom_Ch channel, Ifx_ActiveState activeState)
406 {
407  Ifx_GTM_ATOM_CH *atomCh = (Ifx_GTM_ATOM_CH *)((uint32)&atom->CH0.RDADDR.U + 0x80 * channel);
408 
409  atomCh->CTRL.B.SL = activeState == Ifx_ActiveState_high ? 1 : 0;
410 }
411 
412 
414 {
415  Ifx_GTM_ATOM_CH *atomCh = (Ifx_GTM_ATOM_CH *)((uint32)&atom->CH0.RDADDR.U + 0x80 * channel);
416 
417  atomCh->CTRL.B.TRIGOUT = trigger;
418 }