iLLD_TC27xC  1.0
IfxVadc.c
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1 /**
2  * \file IfxVadc.c
3  * \brief VADC basic functionality
4  *
5  * \version iLLD_0_1_0_10
6  * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
7  *
8  *
9  * IMPORTANT NOTICE
10  *
11  *
12  * Infineon Technologies AG (Infineon) is supplying this file for use
13  * exclusively with Infineon's microcontroller products. This file can be freely
14  * distributed within development tools that are supporting such microcontroller
15  * products.
16  *
17  * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
18  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
19  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
20  * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
21  * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
22  *
23  */
24 
25 /******************************************************************************/
26 /*----------------------------------Includes----------------------------------*/
27 /******************************************************************************/
28 
29 #include "IfxVadc.h"
30 
31 /******************************************************************************/
32 /*-------------------------Function Implementations---------------------------*/
33 /******************************************************************************/
34 
35 void IfxVadc_disableAccess(Ifx_VADC *vadc, IfxVadc_Protection protectionSet)
36 {
38 
40 
42  {
43  vadc->ACCPROT0.U |= (0x00000001 << protectionSet);
44  }
45  else
46  {
47  vadc->ACCPROT1.U |= (0x00000001 << (protectionSet & 0x1F));
48  }
49 
51 }
52 
53 
54 void IfxVadc_disablePostCalibration(Ifx_VADC *vadc, IfxVadc_GroupId group, boolean disable)
55 {
56  if (group < IFXVADC_NUM_ADC_CAL_GROUPS)
57  {
59 
60  uint32 mask = 1 << (IFX_VADC_GLOBCFG_DPCAL0_OFF + group);
61 
62  if (disable == TRUE)
63  {
64  vadc->GLOBCFG.U |= mask;
65  }
66  else
67  {
68  vadc->GLOBCFG.U &= ~mask;
69  }
70 
72  }
73 }
74 
75 
76 void IfxVadc_enableAccess(Ifx_VADC *vadc, IfxVadc_Protection protectionSet)
77 {
79 
81 
83  {
84  vadc->ACCPROT0.U &= ~(0x00000001 << protectionSet);
85  }
86  else
87  {
88  vadc->ACCPROT1.U &= ~(0x00000001 << (protectionSet & 0x1F));
89  }
90 
92 }
93 
94 
96 {
97  return IfxScuCcu_getSpbFrequency() / (1U + vadc->GLOBCFG.B.DIVA);
98 }
99 
100 
102 {
103  return IfxScuCcu_getSpbFrequency() / (1U + vadc->GLOBCFG.B.DIVD);
104 }
105 
106 
108 {
110  uint8 i;
111 
112  for (i = 0; i < 8; i++)
113  {
114  if (vadc->BRSPND[i].U)
115  {
117  }
118  else
119  {
120  continue;
121  }
122  }
123 
124  return status;
125 }
126 
127 
129 {
131 
132  /* just fill level is checked */
133  if (0x7 == group->QSR0.B.FILL)
134  {
135  status = IfxVadc_Status_queueFull;
136  }
137  else
138  {
139  status = IfxVadc_Status_noError;
140  }
141 
142  return status;
143 }
144 
145 
146 Ifx_VADC_RES IfxVadc_getResultBasedOnRequestSource(Ifx_VADC *vadc, Ifx_VADC_G *group, IfxVadc_ChannelId channel, IfxVadc_RequestSource sourceType)
147 {
148  sint32 sourceResultRegister = -1;
149  Ifx_VADC_RES tmpResult;
150 
151  switch (sourceType)
152  {
154  sourceResultRegister = group->QCTRL0.B.SRCRESREG;
155  break;
156 
158  sourceResultRegister = group->ASCTRL.B.SRCRESREG;
159  break;
160 
162  sourceResultRegister = vadc->BRSCTRL.B.SRCRESREG;
163  break;
164  }
165 
166  if (sourceResultRegister > 0)
167  {
168  tmpResult.U = group->RES[sourceResultRegister].U;
169 
170  return tmpResult;
171  }
172  else
173  {
174  if ((sourceType == IfxVadc_RequestSource_background) && (group->CHCTR[channel].B.RESTBS == 1))
175  {
176  tmpResult.B.VF = vadc->GLOBRES.B.VF;
177  tmpResult.B.FCR = vadc->GLOBRES.B.FCR;
178  tmpResult.B.CRS = vadc->GLOBRES.B.CRS;
179  tmpResult.B.EMUX = vadc->GLOBRES.B.EMUX;
180  tmpResult.B.CHNR = vadc->GLOBRES.B.CHNR;
181  tmpResult.B.DRC = vadc->GLOBRES.B.GNR; //The bitfields are the same but interpretation is different. TODO- define a generic result register type.
182  tmpResult.B.RESULT = vadc->GLOBRES.B.RESULT;
183 
184  return tmpResult;
185  }
186  else
187  {
188  tmpResult.U = group->RES[group->CHCTR[channel].B.RESREG].U;
189 
190  return tmpResult;
191  }
192  }
193 }
194 
195 
197 {
199 
200  if (group->ASPND.U)
201  {
203  }
204  else
205  {
206  return status;
207  }
208 }
209 
210 
211 volatile Ifx_SRC_SRCR *IfxVadc_getSrcAddress(IfxVadc_GroupId group, IfxVadc_SrcNr index)
212 {
213  Ifx_SRC_SRCR *base;
214 
215  if (IfxVadc_SrcNr_shared0 <= index)
216  {
217  index -= 4;
218 
219  if ((group & 0x1) != 0)
220  {
221  group = IfxVadc_GroupId_global1; /* Shared interrupt common 1 is used */
222  }
223  else
224  {
225  group = IfxVadc_GroupId_global0; /* Shared interrupt common 0 is used */
226  }
227  }
228  else
229  {
230  /* do nothing */
231  }
232 
233  base = (Ifx_SRC_SRCR *)IfxVadc_cfg_srcAddresses[(group * 4) + index];
234 
235  return &(base[0]);
236 }
237 
238 
239 void IfxVadc_initialiseAdcArbiterClock(Ifx_VADC *vadc, uint32 arbiterClockDivider)
240 {
241  Ifx_VADC_GLOBCFG tempGLOBCFG;
242  tempGLOBCFG.U = vadc->GLOBCFG.U;
243  tempGLOBCFG.B.DIVA = arbiterClockDivider;
244  tempGLOBCFG.B.DIVWC = 1;
246  vadc->GLOBCFG.U = tempGLOBCFG.U;
248 }
249 
250 
251 void IfxVadc_initialiseAdcConverterClock(Ifx_VADC *vadc, uint32 converterClockDivider)
252 {
253  Ifx_VADC_GLOBCFG tempGLOBCFG;
254  tempGLOBCFG.U = vadc->GLOBCFG.U;
255  tempGLOBCFG.B.DIVD = converterClockDivider;
256  tempGLOBCFG.B.DIVWC = 1;
258  vadc->GLOBCFG.U = tempGLOBCFG.U;
260 }
261 
262 
263 uint32 IfxVadc_initializeFAdcD(Ifx_VADC *vadc, uint32 fAdcD)
264 {
265  uint32 divD;
266  uint32 result;
268 
269  divD = (fadc / fAdcD - 1);
270 
271  divD = __minu(divD, 0x3u);
272 
273  result = fadc / (divD + 1);
275  return result;
276 }
277 
278 
279 uint32 IfxVadc_initializeFAdcI(Ifx_VADC *vadc, uint32 fAdcI)
280 {
281  uint32 divA;
282  uint32 result;
284 
285  /* DivA = min(max(0, Fadc / FAdcI - 1), 0x3F); */
286  divA = (fadc << 2) / fAdcI;
287 
288  divA = (divA + 2) >> 2; /* Round to nearest integer */
289  divA = __minu(divA - 1, 0x1Fu);
290  result = fadc / (divA + 1);
291 
292  if (result > IFXVADC_ANALOG_FREQUENCY_MAX)
293  {
294  divA = __minu(divA + 1, 0x1Fu);
295 
296  result = fadc / (divA + 1);
297  }
298  else
299  {
300  /* do nothing */
301  }
302 
303  if (!((result >= IFXVADC_ANALOG_FREQUENCY_MIN) && (result <= IFXVADC_ANALOG_FREQUENCY_MAX)))
304  {
305  result = 0; /* Min / Max FAdcI frequency */
306  }
307  else
308  {
310  }
311 
312  return result;
313 }
314 
315 
316 void IfxVadc_resetKernel(Ifx_VADC *vadc)
317 {
320 
322  vadc->KRST1.B.RST = 1; /* Only if both Kernel reset bits are set a reset is executed */
323  vadc->KRST0.B.RST = 1;
324 
325  while (vadc->KRST0.B.RSTSTAT == 0)
326  {
327  /* Wait until reset is executed */
328  }
329 
330  vadc->KRSTCLR.B.CLR = 1; /* Clear Kernel reset status bit */
332  IfxScuWdt_setCpuEndinit(passwd);
333 }
334 
335 
337 {
338  if (slotEnable != FALSE)
339  {
340  vadcG->ARBPR.U |= slotEnable << (IFX_VADC_G_ARBPR_ASEN0_OFF + slot); /* enable Slot */
341  vadcG->ARBPR.U &= ~(IFX_VADC_G_ARBPR_PRIO0_MSK << (slot * 4u)); /* clear Priority */
342  vadcG->ARBPR.U |= (prio << (slot * 4u)); /* Set Priority */
343 
345  {
346  vadcG->ARBPR.U |= 0x1u << (IFX_VADC_G_ARBPR_CSM0_OFF + (slot * 4u)); /* Set cancel inject mode */
347  }
348  else
349  {
350  vadcG->ARBPR.U &= ~(0x1u << (IFX_VADC_G_ARBPR_CSM0_OFF + (slot * 4u))); /* Set Wait for Start mode */
351  }
352  }
353  else
354  {
355  vadcG->ARBPR.U &= ~(IFX_VADC_G_ARBPR_ASEN0_MSK << (IFX_VADC_G_ARBPR_ASEN0_OFF + slot)); /* disable Slot */
356  }
357 }
358 
359 
360 void IfxVadc_setScan(Ifx_VADC_G *group, uint32 channels, uint32 mask, boolean continuous)
361 {
362  /* select channels which should take part in the scan sequence */
363  /* the mask allows to specify the channels which should be enabled/disabled */
364  group->ASSEL.U = (group->ASSEL.U & ~mask) | (channels & mask);
365 
366  /* enable/disable continuous auto scan */
367  IfxVadc_setAutoScan(group, continuous);
368 }
369 
370 
371 void IfxVadc_startupCalibration(Ifx_VADC *vadc)
372 {
373  boolean calibrationRunning;
374  uint8 adcCalGroupNum;
375 
376  /* Start calibration */
378  /* Set SUCAL bit */
381 
382  /* Wait for hardware self-test and calibration to complete */
383  /* Wait until Calibration is done */
384  do
385  {
386  calibrationRunning = FALSE;
387 
388  for (adcCalGroupNum = 0; adcCalGroupNum < IFXVADC_NUM_ADC_CAL_GROUPS; adcCalGroupNum++)
389  {
390  if (IfxVadc_getAdcCalibrationActiveState(vadc, adcCalGroupNum) != 0) /* Check ADC Calibration Flag CAL */
391  {
392  calibrationRunning = TRUE;
393  }
394  else
395  {
396  /* do nothing */
397  }
398  }
399  } while (calibrationRunning == TRUE); /* wait until calibration of all calibrated kernels are done */
400 }