iLLD_TC27xC  1.0
IfxGpt12_PinMap.c
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1 /**
2  * \file IfxGpt12_PinMap.c
3  * \brief GPT12 I/O map
4  * \ingroup IfxLld_Gpt12
5  *
6  * \version iLLD_0_1_0_10
7  * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
8  *
9  *
10  * IMPORTANT NOTICE
11  *
12  *
13  * Infineon Technologies AG (Infineon) is supplying this file for use
14  * exclusively with Infineon's microcontroller products. This file can be freely
15  * distributed within development tools that are supporting such microcontroller
16  * products.
17  *
18  * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
19  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
20  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
21  * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
22  * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
23  *
24  */
25 
26 #include "IfxGpt12_PinMap.h"
27 
28 IfxGpt12_Capin_In IfxGpt120_CAPINA_P13_2_IN = {&MODULE_GPT120, {&MODULE_P13, 2}, Ifx_RxSel_a};
29 IfxGpt12_TxEud_In IfxGpt120_T2EUDA_P00_8_IN = {&MODULE_GPT120, 2, {&MODULE_P00, 8}, Ifx_RxSel_a};
30 IfxGpt12_TxEud_In IfxGpt120_T2EUDB_P33_6_IN = {&MODULE_GPT120, 2, {&MODULE_P33, 6}, Ifx_RxSel_b};
31 IfxGpt12_TxEud_In IfxGpt120_T3EUDA_P02_7_IN = {&MODULE_GPT120, 3, {&MODULE_P02, 7}, Ifx_RxSel_a};
32 IfxGpt12_TxEud_In IfxGpt120_T3EUDB_P10_7_IN = {&MODULE_GPT120, 3, {&MODULE_P10, 7}, Ifx_RxSel_b};
33 IfxGpt12_TxEud_In IfxGpt120_T4EUDA_P00_9_IN = {&MODULE_GPT120, 4, {&MODULE_P00, 9}, Ifx_RxSel_a};
34 IfxGpt12_TxEud_In IfxGpt120_T4EUDB_P33_5_IN = {&MODULE_GPT120, 4, {&MODULE_P33, 5}, Ifx_RxSel_b};
35 IfxGpt12_TxEud_In IfxGpt120_T5EUDA_P21_6_IN = {&MODULE_GPT120, 5, {&MODULE_P21, 6}, Ifx_RxSel_a};
36 IfxGpt12_TxEud_In IfxGpt120_T5EUDB_P10_1_IN = {&MODULE_GPT120, 5, {&MODULE_P10, 1}, Ifx_RxSel_b};
37 IfxGpt12_TxEud_In IfxGpt120_T6EUDA_P20_0_IN = {&MODULE_GPT120, 6, {&MODULE_P20, 0}, Ifx_RxSel_a};
38 IfxGpt12_TxEud_In IfxGpt120_T6EUDB_P10_0_IN = {&MODULE_GPT120, 6, {&MODULE_P10, 0}, Ifx_RxSel_b};
39 IfxGpt12_TxIn_In IfxGpt120_T2INA_P00_7_IN = {&MODULE_GPT120, 2, {&MODULE_P00, 7}, Ifx_RxSel_a};
40 IfxGpt12_TxIn_In IfxGpt120_T2INB_P33_7_IN = {&MODULE_GPT120, 2, {&MODULE_P33, 7}, Ifx_RxSel_b};
41 IfxGpt12_TxIn_In IfxGpt120_T3INA_P02_6_IN = {&MODULE_GPT120, 3, {&MODULE_P02, 6}, Ifx_RxSel_a};
42 IfxGpt12_TxIn_In IfxGpt120_T3INB_P10_4_IN = {&MODULE_GPT120, 3, {&MODULE_P10, 4}, Ifx_RxSel_b};
43 IfxGpt12_TxIn_In IfxGpt120_T4INA_P02_8_IN = {&MODULE_GPT120, 4, {&MODULE_P02, 8}, Ifx_RxSel_a};
44 IfxGpt12_TxIn_In IfxGpt120_T4INB_P10_8_IN = {&MODULE_GPT120, 4, {&MODULE_P10, 8}, Ifx_RxSel_b};
45 IfxGpt12_TxIn_In IfxGpt120_T5INA_P21_7_IN = {&MODULE_GPT120, 5, {&MODULE_P21, 7}, Ifx_RxSel_a};
46 IfxGpt12_TxIn_In IfxGpt120_T5INB_P10_3_IN = {&MODULE_GPT120, 5, {&MODULE_P10, 3}, Ifx_RxSel_b};
47 IfxGpt12_TxIn_In IfxGpt120_T6INA_P20_3_IN = {&MODULE_GPT120, 6, {&MODULE_P20, 3}, Ifx_RxSel_a};
48 IfxGpt12_TxIn_In IfxGpt120_T6INB_P10_2_IN = {&MODULE_GPT120, 6, {&MODULE_P10, 2}, Ifx_RxSel_b};
49 IfxGpt12_TxOut_Out IfxGpt120_T3OUT_P10_6_OUT = {&MODULE_GPT120, 3, {&MODULE_P10, 6}, IfxPort_OutputIdx_alt4};
50 IfxGpt12_TxOut_Out IfxGpt120_T3OUT_P21_6_OUT = {&MODULE_GPT120, 3, {&MODULE_P21, 6}, IfxPort_OutputIdx_alt7};
51 IfxGpt12_TxOut_Out IfxGpt120_T6OUT_P10_5_OUT = {&MODULE_GPT120, 6, {&MODULE_P10, 5}, IfxPort_OutputIdx_alt5};
52 IfxGpt12_TxOut_Out IfxGpt120_T6OUT_P21_7_OUT = {&MODULE_GPT120, 6, {&MODULE_P21, 7}, IfxPort_OutputIdx_alt7};
53 
54 
56  {
57  &IfxGpt120_CAPINA_P13_2_IN
58  }
59 };
60 
62  {
63  {
64  NULL_PTR,
65  NULL_PTR
66  },
67  {
68  NULL_PTR,
69  NULL_PTR
70  },
71  {
73  &IfxGpt120_T2EUDB_P33_6_IN
74  },
75  {
77  &IfxGpt120_T3EUDB_P10_7_IN
78  },
79  {
81  &IfxGpt120_T4EUDB_P33_5_IN
82  },
83  {
85  &IfxGpt120_T5EUDB_P10_1_IN
86  },
87  {
89  &IfxGpt120_T6EUDB_P10_0_IN
90  }
91  }
92 };
93 
95  {
96  {
97  NULL_PTR,
98  NULL_PTR
99  },
100  {
101  NULL_PTR,
102  NULL_PTR
103  },
104  {
106  &IfxGpt120_T2INB_P33_7_IN
107  },
108  {
110  &IfxGpt120_T3INB_P10_4_IN
111  },
112  {
114  &IfxGpt120_T4INB_P10_8_IN
115  },
116  {
118  &IfxGpt120_T5INB_P10_3_IN
119  },
120  {
122  &IfxGpt120_T6INB_P10_2_IN
123  }
124  }
125 };
126 
128  {
129  {
130  NULL_PTR,
131  NULL_PTR
132  },
133  {
134  NULL_PTR,
135  NULL_PTR
136  },
137  {
138  NULL_PTR,
139  NULL_PTR
140  },
141  {
143  &IfxGpt120_T3OUT_P21_6_OUT
144  },
145  {
146  NULL_PTR,
147  NULL_PTR
148  },
149  {
150  NULL_PTR,
151  NULL_PTR
152  },
153  {
155  &IfxGpt120_T6OUT_P21_7_OUT
156  }
157  }
158 };