iLLD_TC27xC  1.0
IfxEth_PinMap.c
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1 /**
2  * \file IfxEth_PinMap.c
3  * \brief ETH I/O map
4  * \ingroup IfxLld_Eth
5  *
6  * \version iLLD_0_1_0_10
7  * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
8  *
9  *
10  * IMPORTANT NOTICE
11  *
12  *
13  * Infineon Technologies AG (Infineon) is supplying this file for use
14  * exclusively with Infineon's microcontroller products. This file can be freely
15  * distributed within development tools that are supporting such microcontroller
16  * products.
17  *
18  * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
19  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
20  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
21  * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
22  * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
23  *
24  */
25 
26 #include "IfxEth_PinMap.h"
27 
28 IfxEth_Col_In IfxEth_COL_P11_15_IN = {&MODULE_ETH, {&MODULE_P11,15}, Ifx_RxSel_a};
29 IfxEth_Crs_In IfxEth_CRSA_P11_14_IN = {&MODULE_ETH, {&MODULE_P11,14}, Ifx_RxSel_a};
30 IfxEth_Crs_In IfxEth_CRSB_P11_11_IN = {&MODULE_ETH, {&MODULE_P11,11}, Ifx_RxSel_b};
31 IfxEth_Crsdv_In IfxEth_CRSDVA_P11_11_IN = {&MODULE_ETH, {&MODULE_P11,11}, Ifx_RxSel_a};
32 IfxEth_Crsdv_In IfxEth_CRSDVB_P11_14_IN = {&MODULE_ETH, {&MODULE_P11,14}, Ifx_RxSel_b};
33 IfxEth_Mdc_Out IfxEth_MDC_P02_8_OUT = {&MODULE_ETH, {&MODULE_P02, 8}, IfxPort_OutputIdx_alt6};
34 IfxEth_Mdc_Out IfxEth_MDC_P12_0_OUT = {&MODULE_ETH, {&MODULE_P12, 0}, IfxPort_OutputIdx_alt6};
35 IfxEth_Mdc_Out IfxEth_MDC_P21_0_OUT = {&MODULE_ETH, {&MODULE_P21, 0}, IfxPort_OutputIdx_alt6};
36 IfxEth_Mdc_Out IfxEth_MDC_P21_2_OUT = {&MODULE_ETH, {&MODULE_P21, 2}, IfxPort_OutputIdx_alt5};
41 IfxEth_Refclk_In IfxEth_REFCLK_P11_12_IN = {&MODULE_ETH, {&MODULE_P11,12}, Ifx_RxSel_a};
42 IfxEth_Rxclk_In IfxEth_RXCLKB_P11_4_IN = {&MODULE_ETH, {&MODULE_P11, 4}, Ifx_RxSel_b};
43 IfxEth_Rxclk_In IfxEth_RXCLKC_P12_0_IN = {&MODULE_ETH, {&MODULE_P12, 0}, Ifx_RxSel_c};
44 IfxEth_Rxd_In IfxEth_RXD0_P11_10_IN = {&MODULE_ETH, {&MODULE_P11,10}, Ifx_RxSel_a};
45 IfxEth_Rxd_In IfxEth_RXD1_P11_9_IN = {&MODULE_ETH, {&MODULE_P11, 9}, Ifx_RxSel_a};
46 IfxEth_Rxd_In IfxEth_RXD2_P11_8_IN = {&MODULE_ETH, {&MODULE_P11, 8}, Ifx_RxSel_a};
47 IfxEth_Rxd_In IfxEth_RXD3_P11_7_IN = {&MODULE_ETH, {&MODULE_P11, 7}, Ifx_RxSel_a};
48 IfxEth_Rxdv_In IfxEth_RXDVA_P11_11_IN = {&MODULE_ETH, {&MODULE_P11,11}, Ifx_RxSel_a};
49 IfxEth_Rxdv_In IfxEth_RXDVB_P11_14_IN = {&MODULE_ETH, {&MODULE_P11,14}, Ifx_RxSel_b};
50 IfxEth_Rxer_In IfxEth_RXERA_P11_13_IN = {&MODULE_ETH, {&MODULE_P11,13}, Ifx_RxSel_a};
51 IfxEth_Rxer_In IfxEth_RXERB_P21_7_IN = {&MODULE_ETH, {&MODULE_P21, 7}, Ifx_RxSel_b};
52 IfxEth_Txclk_In IfxEth_TXCLKA_P11_5_IN = {&MODULE_ETH, {&MODULE_P11, 5}, Ifx_RxSel_a};
53 IfxEth_Txclk_In IfxEth_TXCLKB_P11_12_IN = {&MODULE_ETH, {&MODULE_P11,12}, Ifx_RxSel_b};
54 IfxEth_Txd_Out IfxEth_TXD0_P11_3_OUT = {&MODULE_ETH, {&MODULE_P11, 3}, IfxPort_OutputIdx_alt6};
55 IfxEth_Txd_Out IfxEth_TXD1_P11_2_OUT = {&MODULE_ETH, {&MODULE_P11, 2}, IfxPort_OutputIdx_alt6};
56 IfxEth_Txd_Out IfxEth_TXD2_P11_1_OUT = {&MODULE_ETH, {&MODULE_P11, 1}, IfxPort_OutputIdx_alt6};
57 IfxEth_Txd_Out IfxEth_TXD3_P11_0_OUT = {&MODULE_ETH, {&MODULE_P11, 0}, IfxPort_OutputIdx_alt6};
60 
61 
63  {
64  &IfxEth_COL_P11_15_IN
65  }
66 };
67 
69  {
71  &IfxEth_CRSB_P11_11_IN
72  }
73 };
74 
76  {
78  &IfxEth_CRSDVB_P11_14_IN
79  }
80 };
81 
83  {
87  &IfxEth_MDC_P21_2_OUT
88  }
89 };
90 
92  {
93  NULL_PTR,
95  NULL_PTR,
96  NULL_PTR,
97  NULL_PTR,
98  NULL_PTR,
99  &IfxEth_MDIO_P21_1_INOUT
100  }
101 };
102 
104  {
105  &IfxEth_REFCLK_P11_12_IN
106  }
107 };
108 
110  {
111  NULL_PTR,
113  &IfxEth_RXCLKC_P12_0_IN
114  }
115 };
116 
118  {
119  &IfxEth_RXD3_P11_7_IN
120  }
121 };
122 
124  {
126  &IfxEth_RXDVB_P11_14_IN
127  }
128 };
129 
131  {
133  &IfxEth_RXERB_P21_7_IN
134  }
135 };
136 
138  {
140  &IfxEth_TXCLKB_P11_12_IN
141  }
142 };
143 
145  {
149  &IfxEth_TXD0_P11_3_OUT
150  }
151 };
152 
154  {
155  &IfxEth_TXEN_P11_6_OUT
156  }
157 };
158 
160  {
161  &IfxEth_TXER_P11_4_OUT
162  }
163 };