iLLD_TC27xC  1.0
IfxEth.h
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1 /**
2  * \file IfxEth.h
3  * \brief ETH basic functionality
4  * \ingroup IfxLld_Eth
5  *
6  * \version iLLD_0_1_0_10
7  * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
8  *
9  *
10  * IMPORTANT NOTICE
11  *
12  *
13  * Infineon Technologies AG (Infineon) is supplying this file for use
14  * exclusively with Infineon's microcontroller products. This file can be freely
15  * distributed within development tools that are supporting such microcontroller
16  * products.
17  *
18  * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
19  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
20  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
21  * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
22  * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
23  *
24  * \defgroup IfxLld_Eth ETH
25  * \ingroup IfxLld
26  * \defgroup IfxLld_Eth_Std Standard Driver
27  * \ingroup IfxLld_Eth
28  * \defgroup IfxLld_Eth_Std_DataStructures Data Structures
29  * \ingroup IfxLld_Eth_Std
30  * \defgroup IfxLld_Eth_Std_Unions Unions
31  * \ingroup IfxLld_Eth_Std
32  * \defgroup IfxLld_Eth_Std_Configuration Configuration Functions
33  * \ingroup IfxLld_Eth_Std
34  * \defgroup IfxLld_Eth_Std_Utility Utility Functions
35  * \ingroup IfxLld_Eth_Std
36  * \defgroup IfxLld_Eth_Std_Initialisation Initialisation Functions
37  * \ingroup IfxLld_Eth_Std
38  */
39 
40 #ifndef IFXET_H
41 #define IFXET_H 1
42 
43 /******************************************************************************/
44 /*----------------------------------Includes----------------------------------*/
45 /******************************************************************************/
46 
47 #include "_Impl/IfxEth_cfg.h"
48 #include "Cpu/Std/Ifx_Types.h"
49 #include "IfxEth_reg.h"
50 #include "Src/Std/IfxSrc.h"
51 #include "_PinMap/IfxEth_PinMap.h"
52 #include "_Utilities/Ifx_Assert.h"
53 
54 /******************************************************************************/
55 /*-----------------------------------Macros-----------------------------------*/
56 /******************************************************************************/
57 
58 /** \brief Size of one ethernet frame buffer
59  */
60 #define IFXETH_RTX_BUFFER_SIZE 1536
61 
62 #ifndef IFXETH_TX_BUFFER_BY_USER
63 #define IFXETH_TX_BUFFER_BY_USER 0
64 #endif
65 
66 #ifndef IFXETH_RX_BUFFER_BY_USER
67 #define IFXETH_RX_BUFFER_BY_USER 0
68 #endif
69 
70 /** \brief Rx buffers (ring mode)
71  */
72 #define IFXETH_MAX_RX_BUFFERS 8
73 
74 /** \brief Tx buffers (ring mode)
75  */
76 #define IFXETH_MAX_TX_BUFFERS 16
77 
78 /** \brief 4 DWORDS (16 bytes)
79  */
80 #define IFXETH_DESCR_SIZE 4
81 
82 /******************************************************************************/
83 /*-------------------------------Enumerations---------------------------------*/
84 /******************************************************************************/
85 
86 typedef enum
87 {
93 
94 /******************************************************************************/
95 /*-----------------------------Data Structures--------------------------------*/
96 /******************************************************************************/
97 
98 /** \brief Structure for Alternate/Enhanced RX descriptor DWORD 0 Bit field access
99  */
100 typedef struct
101 {
102  uint32 ext : 1; /**< \brief Extended Status Available/Rx MAC Address */
103  uint32 CE : 1; /**< \brief CRC Error */
104  uint32 DBE : 1; /**< \brief Dribble Bit Error */
105  uint32 RE : 1; /**< \brief Receive Error */
106  uint32 RWT : 1; /**< \brief Receive Watchdog Timeout */
107  uint32 FT : 1; /**< \brief Frame Type */
108  uint32 LC : 1; /**< \brief Late Collision */
109  uint32 IPC : 1; /**< \brief IPC Checksum Error/Giant Frame */
110  uint32 LS : 1; /**< \brief Last Descriptor */
111  uint32 FS : 1; /**< \brief First Descriptor */
112  uint32 VLAN : 1; /**< \brief VLAN Tag */
113  uint32 OE : 1; /**< \brief Overflow Error */
114  uint32 LE : 1; /**< \brief Length Error */
115  uint32 SAF : 1; /**< \brief Source Address Filter Fail */
116  uint32 DE : 1; /**< \brief Descriptor Error */
117  uint32 ES : 1; /**< \brief Error Summary, ES = PCE | CE | RE | RWT | LC | IPC | OE | DE */
118  uint32 FL : 14; /**< \brief Frame Length */
119  uint32 AFM : 1; /**< \brief Destination Address Filter Fail */
120  uint32 OWN : 1; /**< \brief Own Bit, 1 = own by DMA */
122 
123 /** \brief Structure for Alternate/Enhanced RX descriptor DWORD 1 Bit field access
124  */
125 typedef struct
126 {
127  uint32 RBS1 : 13; /**< \brief Receive Buffer 1 Size */
128  uint32 resv1 : 1; /**< \brief reserved */
129  uint32 RCH : 1; /**< \brief Second Address Chained */
130  uint32 RER : 1; /**< \brief Receive End of Ring */
131  uint32 RBS2 : 13; /**< \brief Receive Buffer 2 Size */
132  uint32 resv : 2; /**< \brief reserved) */
133  uint32 DIC : 1; /**< \brief Disable Interrupt on Completion */
135 
136 /** \brief Structure for Alternate/Enhanced TX descriptor DWORD 0 Bit field access
137  */
138 typedef struct
139 {
140  uint32 DB : 1; /**< \brief Deferred bit */
141  uint32 UF : 1; /**< \brief Underflow error */
142  uint32 ED : 1; /**< \brief Excessive deferral */
143  uint32 CC : 4; /**< \brief Collision count */
144  uint32 VLAN : 1; /**< \brief VLAN TAG */
145  uint32 EC : 1; /**< \brief Excessive Collision */
146  uint32 LC : 1; /**< \brief Late Collision */
147  uint32 NC : 1; /**< \brief No Carrier */
148  uint32 LOC : 1; /**< \brief Loss of Carrier */
149  uint32 PCE : 1; /**< \brief Payload Checksum Error */
150  uint32 FF : 1; /**< \brief Frame Flushed */
151  uint32 JT : 1; /**< \brief Jabber Timeout */
152  uint32 ES : 1; /**< \brief Error Summary, ES = JT | FF | LOC | NC | LC | EC | ED | UF */
153  uint32 IHE : 1; /**< \brief IP Header Error */
154  uint32 TTSS : 1; /**< \brief Transmit Time Stamp Status */
155  uint32 resv : 2; /**< \brief (reserved) */
156  uint32 TCH : 1; /**< \brief Second Address Chained */
157  uint32 TER : 1; /**< \brief Transmit End of Ring */
158  uint32 CIC : 2; /**< \brief Checksum Insertion Control */
159  uint32 resv1 : 1; /**< \brief (Reserved) */
160  uint32 TTSE : 1; /**< \brief Transmit Time Stamp Enable */
161  uint32 DP : 1; /**< \brief Disable Padding */
162  uint32 DC : 1; /**< \brief Disable CRC */
163  uint32 FS : 1; /**< \brief First Segment */
164  uint32 LS : 1; /**< \brief Last Segment */
165  uint32 IC : 1; /**< \brief Interrupt on Completion */
166  uint32 OWN : 1; /**< \brief Own Bit, 1 = own by DMA */
168 
169 /** \brief Structure for Alternate/Enhanced TX descriptor DWORD 1 Bit field access
170  */
171 typedef struct
172 {
173  uint32 TBS1 : 13; /**< \brief Transmit Buffer 1 Size */
174  uint32 resv1 : 3; /**< \brief (reserved) */
175  uint32 TBS2 : 13; /**< \brief Transmit Buffer 2 Size */
176  uint32 resv2 : 3; /**< \brief (reserved) */
178 
179 /** \addtogroup IfxLld_Eth_Std_Unions
180  * \{ */
181 /** \brief Union for RX descriptor DWORD 0
182  */
183 typedef union
184 {
185  IfxEth_AltRxDescr0_Bits A; /**< \brief Structure for RX descriptor DWORD 0 Bit field access */
186  uint32 U; /**< \brief Unsigned long access */
188 
189 /** \brief Union for RX descriptor DWORD 1
190  */
191 typedef union
192 {
193  IfxEth_AltRxDescr1_Bits A; /**< \brief Structure for RX descriptor DWORD 1 Bit field access */
194  uint32 U; /**< \brief unsigned long access */
196 
197 /** \brief Union for RX descriptor DWORD 2
198  */
199 typedef union
200 {
201  uint32 U; /**< \brief unsigned long access */
203 
204 /** \brief Union for RX descriptor DWORD 3
205  */
206 typedef union
207 {
208  uint32 U; /**< \brief unsigned long access */
210 
211 /** \brief Union for TX descriptor DWORD 0
212  */
213 typedef union
214 {
215  IfxEth_AltTxDescr0_Bits A; /**< \brief Structure for TX descriptor DWORD 0 Bit field access */
216  uint32 U; /**< \brief Unsigned long access */
218 
219 /** \brief Union for TX descriptor DWORD 1
220  */
221 typedef union
222 {
223  IfxEth_AltTxDescr1_Bits A; /**< \brief Structure for RX descriptor DWORD 1 Bit field access */
224  uint32 U; /**< \brief unsigned long access */
226 
227 /** \brief Union for TX descriptor DWORD 2
228  */
229 typedef union
230 {
231  uint32 U; /**< \brief unsigned long access */
233 
234 /** \brief Union for TX descriptor DWORD 3
235  */
236 typedef union
237 {
238  uint32 U; /**< \brief unsigned long access */
240 
241 /** \} */
242 
243 /** \addtogroup IfxLld_Eth_Std_DataStructures
244  * \{ */
245 /** \brief Normal RX descriptor
246  */
247 typedef struct
248 {
249  IfxEth_RxDescr0 RDES0; /**< \brief RX descriptor DWORD 0 */
250  IfxEth_RxDescr1 RDES1; /**< \brief RX descriptor DWORD 1 */
251  IfxEth_RxDescr2 RDES2; /**< \brief RX descriptor DWORD 2 */
252  IfxEth_RxDescr3 RDES3; /**< \brief RX descriptor DWORD 3 */
254 
255 /** \brief Normal TX descriptor
256  */
257 typedef struct
258 {
259  IfxEth_TxDescr0 TDES0; /**< \brief TX descriptor DWORD 0 */
260  IfxEth_TxDescr1 TDES1; /**< \brief TX descriptor DWORD 1 */
261  IfxEth_TxDescr2 TDES2; /**< \brief TX descriptor DWORD 2 */
262  IfxEth_TxDescr3 TDES3; /**< \brief TX descriptor DWORD 3 */
264 
265 /** \} */
266 
267 /** \brief Port pins configuration
268  */
269 typedef struct
270 {
271  IfxEth_Crsdv_In *crsDiv; /**< \brief pointer to CRSDIV input pin configtring_here */
272  IfxEth_Refclk_In *refClk; /**< \brief Pointer to REFCLK input pin config */
273  IfxEth_Rxd_In *rxd0; /**< \brief Pointer to RXD0 input pin config */
274  IfxEth_Rxd_In *rxd1; /**< \brief Pointer to RXD1 input pin config */
275  IfxEth_Mdc_Out *mdc; /**< \brief Pointer to MDC output pin config */
276  IfxEth_Mdio_InOut *mdio; /**< \brief Pointer to MDIO pin config */
277  IfxEth_Txd_Out *txd0; /**< \brief Pointer to TXD0 output pin config */
278  IfxEth_Txd_Out *txd1; /**< \brief Pointer to TXD1 output pin config */
279  IfxEth_Txen_Out *txEn; /**< \brief Pointer to TXEN output pin config */
281 
282 /** \addtogroup IfxLld_Eth_Std_DataStructures
283  * \{ */
284 /** \brief ETH configuration structure
285  */
286 typedef struct
287 {
288  uint8 macAddress[6]; /**< \brief MAC address for the ethernet, should be unique in the network */
289  uint32 (*phyInit)(void); /**< \brief Pointer to the transceiver init function */
290  boolean (*phyLink)(void); /**< \brief Pointer to the transceiver link function */
291  const IfxEth_PortPins *portPins; /**< \brief Pointer to port pins configuration */
292  Ifx_Priority isrPriority; /**< \brief Interrupt service priority */
293  IfxSrc_Tos isrProvider; /**< \brief Interrupt service provider */
294 } IfxEth_Config;
295 
296 /** \} */
297 
298 typedef union
299 {
303 
304 typedef union
305 {
309 
310 /** \addtogroup IfxLld_Eth_Std_DataStructures
311  * \{ */
312 /** \brief ETH driver structure
313  */
314 typedef struct
315 {
316  Ifx_ETH_STATUS status; /**< \brief Intermediate variable to use register content in control structure */
317  uint32 rxCount; /**< \brief Number of frames received */
318  uint32 txCount; /**< \brief Number of frames transmitted */
319  uint32 error; /**< \brief Indicate an error has occurred during execution */
320  sint32 isrRxCount; /**< \brief Count of RX ISR */
321  sint32 isrTxCount; /**< \brief Count of TX ISR */
322  sint32 txDiff; /**< \brief Difference between isrTxCount and txCount */
323  sint32 rxDiff; /**< \brief Difference between isrRxCount and rxCount */
324  sint32 isrCount; /**< \brief count of all ISR */
325  IfxEth_Config config; /**< \brief Copy of the configuration passed through IfxEth_init() */
326  IfxEth_RxDescrList *rxDescr; /**< \brief pointer to RX descriptor RAM */
327  IfxEth_TxDescrList *txDescr; /**< \brief pointer to TX descriptor RAM */
330 } IfxEth;
331 
332 /** \brief Structure for RX descriptor DWORD 0 Bit field access
333  */
334 typedef struct
335 {
336  uint32 PCE : 1; /**< \brief Rx MAC Address/Payload Checksum Error */
337  uint32 CE : 1; /**< \brief CRC Error */
338  uint32 DBE : 1; /**< \brief Dribble Bit Error */
339  uint32 RE : 1; /**< \brief Receive Error */
340  uint32 RWT : 1; /**< \brief Receive Watchdog Timeout */
341  uint32 FT : 1; /**< \brief Frame Type */
342  uint32 LC : 1; /**< \brief Late Collision */
343  uint32 IPC : 1; /**< \brief IPC Checksum Error/Giant Frame */
344  uint32 LS : 1; /**< \brief Last Descriptor */
345  uint32 FS : 1; /**< \brief First Descriptor */
346  uint32 VLAN : 1; /**< \brief VLAN Tag */
347  uint32 OE : 1; /**< \brief Overflow Error */
348  uint32 LE : 1; /**< \brief Length Error */
349  uint32 SAF : 1; /**< \brief Source Address Filter Fail */
350  uint32 DE : 1; /**< \brief Descriptor Error */
351  uint32 ES : 1; /**< \brief Error Summary, ES = PCE | CE | RE | RWT | LC | IPC | OE | DE */
352  uint32 FL : 14; /**< \brief Frame Length */
353  uint32 AFM : 1; /**< \brief Destination Address Filter Fail */
354  uint32 OWN : 1; /**< \brief Own Bit, 1 = own by DMA */
356 
357 /** \brief Structure for RX descriptor DWORD 1 Bit field access
358  */
359 typedef struct
360 {
361  uint32 RBS1 : 11; /**< \brief Receive Buffer 1 Size */
362  uint32 RBS2 : 11; /**< \brief Receive Buffer 2 Size */
363  uint32 resv : 2; /**< \brief (reserved) */
364  uint32 RCH : 1; /**< \brief Second Address Chained */
365  uint32 RER : 1; /**< \brief Receive End of Ring */
366  uint32 resv2 : 5; /**< \brief (reserved) */
367  uint32 DIC : 1; /**< \brief Disable Interrupt on Completion */
369 
370 /** \brief Structure for TX descriptor DWORD 0 Bit field access
371  */
372 typedef struct
373 {
374  uint32 DB : 1; /**< \brief Deferred Bit */
375  uint32 UF : 1; /**< \brief Underflow Error */
376  uint32 ED : 1; /**< \brief Excessive Deferral */
377  uint32 CC : 4; /**< \brief Collision Count */
378  uint32 VLAN : 1; /**< \brief VLAN Tag */
379  uint32 EC : 1; /**< \brief Excessive Collision */
380  uint32 LC : 1; /**< \brief Late Collision */
381  uint32 NC : 1; /**< \brief No Carrier */
382  uint32 LOC : 1; /**< \brief Loss of Carrier */
383  uint32 PCE : 1; /**< \brief Payload Checksum Error */
384  uint32 FF : 1; /**< \brief Frame Flushed */
385  uint32 JT : 1; /**< \brief Jabber Timeout */
386  uint32 ES : 1; /**< \brief Error Summary, ES = JT | FF | LOC | NC | LC | EC | ED | UF */
387  uint32 IHE : 1; /**< \brief IP Header Error */
388  uint32 TTSS : 1; /**< \brief Tx Time Stamp Status */
389  uint32 resv : 13; /**< \brief (reserved) */
390  uint32 OWN : 1; /**< \brief Own Bit, 1 = own by DMA */
392 
393 /** \brief Structure for TX descriptor DWORD 1 Bit field access
394  */
395 typedef struct
396 {
397  uint32 TBS1 : 11; /**< \brief Transmit Buffer 1 Size */
398  uint32 TBS2 : 11; /**< \brief Transmit Buffer 2 Size */
399  uint32 TTSE : 1; /**< \brief Transmit Time Stamp Enable */
400  uint32 DP : 1; /**< \brief Disable Padding */
401  uint32 TCH : 1; /**< \brief Second Address Chained */
402  uint32 TER : 1; /**< \brief Transmit End of Ring */
403  uint32 DC : 1; /**< \brief Disable CRC */
404  uint32 CIC : 2; /**< \brief Checksum Insertion Control */
405  uint32 FS : 1; /**< \brief First Segment */
406  uint32 LS : 1; /**< \brief Last Segment */
407  uint32 IC : 1; /**< \brief Interrupt on Completion */
409 
410 /** \} */
411 
412 /** \addtogroup IfxLld_Eth_Std_Configuration
413  * \{ */
414 
415 /******************************************************************************/
416 /*-------------------------Inline Function Prototypes-------------------------*/
417 /******************************************************************************/
418 
419 /** \brief Waits for one TX buffer becomes available
420  * \param eth ETH driver structure
421  * retval non NULL_PTR TX buffer is available at the address pointed by the returned value
422  * retval NULL_PTR TX buffer is busy.
423  */
425 
426 /** \brief Sets the MAC address
427  * \param eth ETH driver structure
428  * \param loopbackMode loopback mode enable/disbale
429  * \return None
430  */
431 IFX_INLINE void IfxEth_setLoopbackMode(IfxEth *eth, boolean loopbackMode);
432 
433 /** \brief Clear transmit interrupt request
434  * \param eth ETH driver structure
435  * \return None
436  */
438 
439 /** \brief Clear receive interrupt request
440  * \param eth ETH driver structure
441  * \return None
442  */
444 
445 /** \brief Set buffer of a TX descriptor
446  * \param descr Entdescr Pointer to a TX descriptorer_String_here
447  * \return None
448  */
449 IFX_INLINE void IfxEth_TxDescr_setBuffer(IfxEth_TxDescr *descr, void *buffer);
450 
451 /** \brief Return TRUE if a TX descriptor is available for setup
452  */
454 
455 /** \brief Get pointer to next TX descriptor
456  * \param descr descr Pointer to a TX descriptor
457  */
459 
460 /** \brief Set buffer of an RX descriptor
461  * \param descr descr Pointer to an RX descriptor
462  * \return None
463  */
464 IFX_INLINE void IfxEth_RxDescr_setBuffer(IfxEth_RxDescr *descr, void *buffer);
465 
466 /******************************************************************************/
467 /*-------------------------Global Function Prototypes-------------------------*/
468 /******************************************************************************/
469 
470 /** \brief Start the receiver functions
471  * \param eth ETH driver structure
472  * \return None
473  */
475 
476 /** \brief Sets the MAC address
477  * \param eth ETH driver structure
478  * \param macAddress MAC address
479  * \return None
480  */
481 IFX_EXTERN void IfxEth_setMacAddress(IfxEth *eth, const uint8 *macAddress);
482 
483 /** \brief Request to send the transmit buffer
484  *
485  * The transmit buffer is the last one specified by IfxEth_getTransmitBuffer()
486  * \param eth ETH driver structure
487  * \param len Length of the data put in the transmit buffer (in bytes)
488  * \return None
489  */
491 
492 /** \brief Free the receive buffer, enabling it for the further reception
493  * \param eth ETH driver structure
494  * \return None
495  */
497 
498 /** \} */
499 
500 /** \addtogroup IfxLld_Eth_Std_Utility
501  * \{ */
502 
503 /******************************************************************************/
504 /*-------------------------Inline Function Prototypes-------------------------*/
505 /******************************************************************************/
506 
507 /** \brief Get pointer to next RX descriptor
508  * \param descr descr Pointer to an RX descriptor
509  */
511 
512 /** \brief Get pointer to actual RX descriptor
513  * \param eth eth ETH driver structure
514  */
516 
517 /** \brief Shuffle to next TX descriptor
518  * \param eth eth ETH driver structure
519  * \return None
520  */
522 
523 /** \brief Shuffle to next RX descriptor
524  * \param eth eth ETH driver structure
525  * \return None
526  */
528 
529 /** \brief Checks whether transmit interrupt is requested
530  * \param eth ETH driver structure
531  * \return TRUE/FALSE
532  */
534 
535 /** \brief Checks whether receive interrupt is requested
536  * \param eth ETH driver structure
537  * \return TRUE/FALSE
538  */
540 
541 /** \brief Checks whether one or more RX data is available
542  * \param eth ETH driver structure
543  * \return retval TRUE one or more RX data is available
544  * retval FALSE no RX data is available
545  */
547 
548 /**
549  * \param eth pointer to ETH driver structure
550  */
552 
553 /** \brief Checks whether physical connection is active
554  * \param eth ETH driver structure
555  * \return retval zero Connection is inactive
556  * retval non zero Connection is active
557  */
559 
560 /** \brief Returns length of the oldest available RX data
561  * \param eth ETH driver structure
562  * \return Data length
563  */
565 
566 /** \brief Returns pointer to the MAC address configured for this ETH
567  * \param eth ETH driver structure
568  */
570 
571 /** \brief Get a free transmit buffer
572  * \param eth ETH driver structure
573  * \return Loop back mode status (TRUE / FALSE)
574  */
576 
577 /** \brief Get pointer to base TX descriptor
578  * \param eth eth ETH driver structure
579  */
581 
582 /** \brief Get pointer to base RX descriptor
583  * \param eth eth ETH driver structure
584  */
586 
587 /** \brief Get pointer to actual TX descriptor
588  * \param eth eth ETH driver structure
589  */
591 
592 /**
593  */
595 
596 /** \brief Release a TX descriptor for transmit queue
597  * \param descr Enter_String_herdescr Pointer to a TX descriptore
598  * \return None
599  */
601 
602 /** \brief release RX descriptor
603  * \return None
604  */
606 
607 /******************************************************************************/
608 /*-------------------------Global Function Prototypes-------------------------*/
609 /******************************************************************************/
610 
611 /** \brief Wakeup the transmitter functions
612  * \param eth eth ETH driver structure
613  * \return None
614  */
616 
617 /** \brief Wakeup the receiver functions
618  * \param eth eth ETH driver structure
619  * \return None
620  */
622 
623 /** \brief Stop the transmitter functions
624  * \param eth eth ETH driver structure
625  * \return None
626  */
628 
629 /** \brief Start the transmitter functions
630  * \param eth eth ETH driver structure
631  * \return None
632  */
634 
635 /** \brief Set up checksum Engine
636  * \param eth eth ETH driver structure
637  * \return None
638  */
640 
641 /**
642  * \param eth pointer to ETH driver structure
643  * \param len length of buffer
644  * \return None
645  */
646 IFX_EXTERN void IfxEth_setAndSendTransmitBuffer(IfxEth *eth, void *buffer, uint16 len);
647 
648 /** \brief Reads the MAC address from module register
649  * \param eth ETH driver structure
650  * \param macAddress MAC address
651  * \return None
652  */
653 IFX_EXTERN void IfxEth_readMacAddress(IfxEth *eth, uint8 *macAddress);
654 
655 /** \brief Get a free transmit buffer
656  * \param eth ETH driver structure
657  * \return retval NULL_PTR no free transmit buffer is available
658  * retval !NULL_PTR a free transmit buffer is available
659  */
661 
662 /** \brief Gets receive buffer\n
663  * note: IfxEth_freeReceiveBuffer() shall be called after the data from the RX buffer has been processed
664  * \param eth ETH driver structure
665  * \return retval NULL_PTR no received frame
666  * retval !NULL_PTR a frame has been received
667  */
669 
670 /** \brief Enable ETH Module
671  * \return None
672  */
674 
675 /** \} */
676 
677 /** \addtogroup IfxLld_Eth_Std_Initialisation
678  * \{ */
679 
680 /******************************************************************************/
681 /*-------------------------Inline Function Prototypes-------------------------*/
682 /******************************************************************************/
683 
684 /** \brief Setup some properties of a TX descriptor
685  * \param descr Enter_Sdescr Pointer to a TX descriptortring_here
686  * \return None
687  */
688 IFX_INLINE void IfxEth_TxDescr_setup(IfxEth_TxDescr *descr, uint16 length, boolean firstSegment, boolean lastSegment);
689 
690 /******************************************************************************/
691 /*-------------------------Global Function Prototypes-------------------------*/
692 /******************************************************************************/
693 
694 /** \brief set output pin of port
695  * \param eth eth pointer to ETH driver structure
696  * \param portPins portPins pin of port to be set
697  * \return None
698  */
699 IFX_EXTERN void IfxEth_setupOutputPins(IfxEth *eth, const IfxEth_PortPins *portPins);
700 
701 /** \brief Set up input pins
702  * \param eth eth pointer to ETH driver structure
703  * \param portPins portPins pin of port to be set
704  * \return None
705  */
706 IFX_EXTERN void IfxEth_setupInputPins(IfxEth *eth, const IfxEth_PortPins *portPins);
707 
708 /** \brief Initialises the driver
709  * \param eth ETH driver structure
710  * \param config ETH configuration structure
711  * \return None
712  */
713 IFX_EXTERN void IfxEth_init(IfxEth *eth, const IfxEth_Config *config);
714 
715 /** \} */
716 
717 /******************************************************************************/
718 /*-------------------Global Exported Variables/Constants----------------------*/
719 /******************************************************************************/
720 
721 /** \brief receive buffers
722  */
724 
726 
727 /** \brief Transmit buffers
728  */
730 
732 
733 /******************************************************************************/
734 /*---------------------Inline Function Implementations------------------------*/
735 /******************************************************************************/
736 
738 {
739  void *tx;
740 
741  do
742  {
743  tx = IfxEth_getTransmitBuffer(eth);
744  } while (tx == NULL_PTR);
745 
746  return tx;
747 }
748 
749 
750 IFX_INLINE void IfxEth_setLoopbackMode(IfxEth *eth, boolean loopbackMode)
751 {
752  (void)eth;
753  ETH_MAC_CONFIGURATION.B.LM = loopbackMode ? 1 : 0;
754 }
755 
756 
758 {
759  (void)eth;
760  MODULE_ETH.STATUS.B.TI = 1;
761 }
762 
763 
765 {
766  (void)eth;
767  MODULE_ETH.STATUS.B.RI = 1;
768 }
769 
770 
772 {
773  descr->TDES2.U = (uint32)buffer;
774 }
775 
776 
778 {
779  return (descr->TDES0.A.OWN == 0) ? TRUE : FALSE;
780 }
781 
782 
784 {
785  return (IfxEth_TxDescr *)(descr->TDES3.U);
786 }
787 
788 
790 {
791  descr->RDES2.U = (uint32)buffer;
792 }
793 
794 
796 {
797  return (IfxEth_RxDescr *)(descr->RDES3.U);
798 }
799 
800 
802 {
803  return eth->pRxDescr;
804 }
805 
806 
808 {
810 }
811 
812 
814 {
816 }
817 
818 
820 {
821  (void)eth;
822 
823  return MODULE_ETH.STATUS.B.TI != 0;
824 }
825 
826 
828 {
829  (void)eth;
830 
831  return MODULE_ETH.STATUS.B.RI != 0;
832 }
833 
834 
836 {
837  //return (IfxEth_rxDescr[eth->rxIndex][0] & (1U << 31)) == 0);
838  return IfxEth_getActualRxDescriptor(eth)->RDES0.A.OWN == 0;
839 }
840 
841 
843 {
845  boolean error = (descr->RDES0.A.IPC != 0);
846  descr->RDES0.A.IPC = 0;
847 
848  return error;
849 }
850 
851 
853 {
854  return eth->config.phyLink() != 0;
855 }
856 
857 
859 {
860  uint16 length = 0;
861 
862  if (IfxEth_isRxDataAvailable(eth) != FALSE)
863  {
864  length = (uint16)IfxEth_getActualRxDescriptor(eth)->RDES0.A.FL;
865  }
866 
867  return length;
868 }
869 
870 
872 {
873  return (void *)eth->config.macAddress;
874 }
875 
876 
878 {
879  (void)eth;
880  return (ETH_MAC_CONFIGURATION.B.LM != 0) ? TRUE : FALSE;
881 }
882 
883 
885 {
886  return eth->txDescr->items;
887 }
888 
889 
891 {
892  return eth->rxDescr->items;
893 }
894 
895 
897 {
898  return eth->pTxDescr;
899 }
900 
901 
903 {
904  uint32 offset = (uint32)eth->pRxDescr - (uint32)IfxEth_getBaseRxDescriptor(eth);
905  return offset / sizeof(IfxEth_RxDescr);
906 }
907 
908 
910 {
911  descr->TDES0.A.OWN = 1U;
912 }
913 
914 
916 {
917  descr->RDES0.A.OWN = 1U;
918 }
919 
920 
921 IFX_INLINE void IfxEth_TxDescr_setup(IfxEth_TxDescr *descr, uint16 length, boolean firstSegment, boolean lastSegment)
922 {
923  IfxEth_TxDescr0 tdes0;
924 
925  tdes0.U = descr->TDES0.U;
926  tdes0.A.FS = firstSegment;
927  tdes0.A.LS = lastSegment;
928  descr->TDES0.U = tdes0.U;
929  descr->TDES1.U = length;
930 }
931 
932 
933 #endif /* IFXET_H */