iLLD_TC27xC  1.0
IfxQspi.h
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1 /**
2  * \file IfxQspi.h
3  * \brief QSPI basic functionality
4  * \ingroup IfxLld_Qspi
5  *
6  * \version iLLD_0_1_0_10
7  * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
8  *
9  *
10  * IMPORTANT NOTICE
11  *
12  *
13  * Infineon Technologies AG (Infineon) is supplying this file for use
14  * exclusively with Infineon's microcontroller products. This file can be freely
15  * distributed within development tools that are supporting such microcontroller
16  * products.
17  *
18  * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
19  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
20  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
21  * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
22  * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
23  *
24  * \defgroup IfxLld_Qspi QSPI
25  * \ingroup IfxLld
26  * \defgroup IfxLld_Qspi_Std Standard Driver
27  * \ingroup IfxLld_Qspi
28  * \defgroup IfxLld_Qspi_Std_Enum Enumerations
29  * \ingroup IfxLld_Qspi_Std
30  * \defgroup IfxLld_Qspi_Std_Operative Operative Functions
31  * \ingroup IfxLld_Qspi_Std
32  * \defgroup IfxLld_Qspi_Std_Support Support Functions
33  * \ingroup IfxLld_Qspi_Std
34  * \defgroup IfxLld_Qspi_Std_Interrupt Interrupt Functions
35  * \ingroup IfxLld_Qspi_Std
36  * \defgroup IfxLld_Qspi_Std_IO IO Pin Configuration Functions
37  * \ingroup IfxLld_Qspi_Std
38  */
39 
40 #ifndef IFXQSPI_H
41 #define IFXQSPI_H 1
42 
43 /******************************************************************************/
44 /*----------------------------------Includes----------------------------------*/
45 /******************************************************************************/
46 
47 #include "_Impl/IfxQspi_cfg.h"
48 #include "Src/Std/IfxSrc.h"
49 #include "If/SpiIf.h"
50 #include "_PinMap/IfxQspi_PinMap.h"
51 
52 /******************************************************************************/
53 /*--------------------------------Enumerations--------------------------------*/
54 /******************************************************************************/
55 
56 /** \addtogroup IfxLld_Qspi_Std_Enum
57  * \{ */
58 /** \brief QSPI channel Number (BACON.CS)
59  */
60 typedef enum
61 {
62  IfxQspi_ChannelId_0, /**< \brief Channel #0 */
63  IfxQspi_ChannelId_1, /**< \brief Channel #1 */
64  IfxQspi_ChannelId_2, /**< \brief Channel #2 */
65  IfxQspi_ChannelId_3, /**< \brief Channel #3 */
66  IfxQspi_ChannelId_4, /**< \brief Channel #4 */
67  IfxQspi_ChannelId_5, /**< \brief Channel #5 */
68  IfxQspi_ChannelId_6, /**< \brief Channel #6 */
69  IfxQspi_ChannelId_7, /**< \brief Channel #7 */
70  IfxQspi_ChannelId_8, /**< \brief Channel #8 */
71  IfxQspi_ChannelId_9, /**< \brief Channel #9 */
72  IfxQspi_ChannelId_10, /**< \brief Channel #10 */
73  IfxQspi_ChannelId_11, /**< \brief Channel #11 */
74  IfxQspi_ChannelId_12, /**< \brief Channel #12 */
75  IfxQspi_ChannelId_13, /**< \brief Channel #13 */
76  IfxQspi_ChannelId_14, /**< \brief Channel #14 */
78 
79 /** \brief Data length unit of a frame (BACON.BYTE)
80  */
81 typedef enum
82 {
83  IfxQspi_DataLengthUnit_bit = 0, /**< \brief Data Length in Bits */
84  IfxQspi_DataLengthUnit_byte = 1 /**< \brief Data length in Bytes */
86 
87 /** \brief Frame Expect phase time out value
88  */
89 typedef enum
90 {
91  IfxQspi_ExpectTimeout_64 = 0, /**< \brief Expect phse time out 64 */
92  IfxQspi_ExpectTimeout_128 = 1, /**< \brief Expect phse time out 128 */
93  IfxQspi_ExpectTimeout_256 = 2, /**< \brief Expect phse time out 256 */
94  IfxQspi_ExpectTimeout_512 = 3, /**< \brief Expect phse time out 512 */
95  IfxQspi_ExpectTimeout_1024 = 4, /**< \brief Expect phse time out 1024 */
96  IfxQspi_ExpectTimeout_2048 = 5, /**< \brief Expect phse time out 2048 */
97  IfxQspi_ExpectTimeout_4096 = 6, /**< \brief Expect phse time out 4096 */
98  IfxQspi_ExpectTimeout_8192 = 7, /**< \brief Expect phse time out 8192 */
99  IfxQspi_ExpectTimeout_16384 = 8, /**< \brief Expect phse time out 16384 */
100  IfxQspi_ExpectTimeout_32768 = 9, /**< \brief Expect phse time out 32768 */
101  IfxQspi_ExpectTimeout_65536 = 10, /**< \brief Expect phse time out 65536 */
102  IfxQspi_ExpectTimeout_131072 = 11, /**< \brief Expect phse time out 131072 */
103  IfxQspi_ExpectTimeout_262144 = 12, /**< \brief Expect phse time out 262144 */
104  IfxQspi_ExpectTimeout_524288 = 13, /**< \brief Expect phse time out 524288 */
105  IfxQspi_ExpectTimeout_1048576 = 14, /**< \brief Expect phse time out 1048576 */
106  IfxQspi_ExpectTimeout_2097152 = 15 /**< \brief Expect phse time out 2097152 */
108 
109 /** \brief QSPI controller mode (GLOBALCON.MODE)
110  */
111 typedef enum
112 {
113  IfxQspi_Mode_master = 0, /**< \brief QSPI in "master" mode */
114  IfxQspi_Mode_pwmOverQspi = 1, /**< \brief QSPI in "PWM over QSPI" mode */
115  IfxQspi_Mode_slave = 2 /**< \brief QSPI in "slave" mode */
116 } IfxQspi_Mode;
117 
118 /** \brief Request between pause and Run transition
119  */
120 typedef enum
121 {
122  IfxQspi_PauseRunTransition_pause = 0, /**< \brief Request value for pause */
123  IfxQspi_PauseRunTransition_run = 1 /**< \brief Request value for Run */
125 
126 /** \brief QSPI frame phase (STATUS.PHASE)
127  */
128 typedef enum
129 {
130  IfxQspi_Phase_wait = 0, /**< \brief Frame wait phase */
131  IfxQspi_Phase_idleA = 1, /**< \brief Frame idleA phase */
132  IfxQspi_Phase_idleB = 2, /**< \brief frame idleB phase */
133  IfxQspi_Phase_lead = 3, /**< \brief Frame lead phase */
134  IfxQspi_Phase_data = 4, /**< \brief Frame data phase */
135  IfxQspi_Phase_trail = 5, /**< \brief Frame trail phase */
136  IfxQspi_Phase_expect = 6, /**< \brief Frame expect phase */
137  IfxQspi_Phase_leadStrobe = 7, /**< \brief Frame leadstrobe phase */
138  IfxQspi_Phase_trailStrobe = 8 /**< \brief Frame trailstrobe phase */
139 } IfxQspi_Phase;
140 
141 /** \brief Receive Fifo Interrupt Threshold
142  */
143 typedef enum
144 {
145  IfxQspi_RxFifoInt_0, /**< \brief RxFifo Interrupt Threshold #0 */
146  IfxQspi_RxFifoInt_1, /**< \brief RxFifo Interrupt Threshold #1 */
147  IfxQspi_RxFifoInt_2, /**< \brief RxFifo Interrupt Threshold #2 */
148  IfxQspi_RxFifoInt_3, /**< \brief RxFifo Interrupt Threshold #3 */
150 
151 /** \brief Enable/disable the sensitivity of the module to sleep signal\n
152  * Definition in Ifx_QSPI.CLC.B.EDIS
153  */
154 typedef enum
155 {
156  IfxQspi_SleepMode_enable = 0, /**< \brief Sleep Mode enabled */
157  IfxQspi_SleepMode_disable = 1 /**< \brief Sleep Mode disabled */
159 
160 /** \brief STROBE delay for SLSO in delayed mode (GLOBALCON.STROBE)
161  */
162 typedef enum
163 {
164  IfxQspi_StrobeDelay_1, /**< \brief SLSO delay 1 cycle(s) */
165  IfxQspi_StrobeDelay_2, /**< \brief SLSO delay 2 cycle(s) */
166  IfxQspi_StrobeDelay_3, /**< \brief SLSO delay 3 cycle(s) */
167  IfxQspi_StrobeDelay_4, /**< \brief SLSO delay 4 cycle(s) */
168  IfxQspi_StrobeDelay_5, /**< \brief SLSO delay 5 cycle(s) */
169  IfxQspi_StrobeDelay_6, /**< \brief SLSO delay 6 cycle(s) */
170  IfxQspi_StrobeDelay_7, /**< \brief SLSO delay 7 cycle(s) */
171  IfxQspi_StrobeDelay_8, /**< \brief SLSO delay 8 cycle(s) */
172  IfxQspi_StrobeDelay_9, /**< \brief SLSO delay 9 cycle(s) */
173  IfxQspi_StrobeDelay_10, /**< \brief SLSO delay 10 cycle(s) */
174  IfxQspi_StrobeDelay_11, /**< \brief SLSO delay 11 cycle(s) */
175  IfxQspi_StrobeDelay_12, /**< \brief SLSO delay 12 cycle(s) */
176  IfxQspi_StrobeDelay_13, /**< \brief SLSO delay 13 cycle(s) */
177  IfxQspi_StrobeDelay_14, /**< \brief SLSO delay 14 cycle(s) */
178  IfxQspi_StrobeDelay_15, /**< \brief SLSO delay 15 cycle(s) */
179  IfxQspi_StrobeDelay_16, /**< \brief SLSO delay 16 cycle(s) */
180  IfxQspi_StrobeDelay_17, /**< \brief SLSO delay 17 cycle(s) */
181  IfxQspi_StrobeDelay_18, /**< \brief SLSO delay 18 cycle(s) */
182  IfxQspi_StrobeDelay_19, /**< \brief SLSO delay 19 cycle(s) */
183  IfxQspi_StrobeDelay_20, /**< \brief SLSO delay 20 cycle(s) */
184  IfxQspi_StrobeDelay_21, /**< \brief SLSO delay 21 cycle(s) */
185  IfxQspi_StrobeDelay_22, /**< \brief SLSO delay 22 cycle(s) */
186  IfxQspi_StrobeDelay_23, /**< \brief SLSO delay 23 cycle(s) */
187  IfxQspi_StrobeDelay_24, /**< \brief SLSO delay 24 cycle(s) */
188  IfxQspi_StrobeDelay_25, /**< \brief SLSO delay 25 cycle(s) */
189  IfxQspi_StrobeDelay_26, /**< \brief SLSO delay 26 cycle(s) */
190  IfxQspi_StrobeDelay_27, /**< \brief SLSO delay 27 cycle(s) */
191  IfxQspi_StrobeDelay_28, /**< \brief SLSO delay 28 cycle(s) */
192  IfxQspi_StrobeDelay_29, /**< \brief SLSO delay 29 cycle(s) */
193  IfxQspi_StrobeDelay_30, /**< \brief SLSO delay 30 cycle(s) */
194  IfxQspi_StrobeDelay_31, /**< \brief SLSO delay 31 cycle(s) */
195  IfxQspi_StrobeDelay_32, /**< \brief SLSO delay 32 cycle(s) */
197 
198 /** \brief Transmit Fifo Interrupt Threshold
199  */
200 typedef enum
201 {
202  IfxQspi_TxFifoInt_1, /**< \brief TxFifo Interrupt Threshold #1 */
203  IfxQspi_TxFifoInt_2, /**< \brief TxFifo Interrupt Threshold #2 */
204  IfxQspi_TxFifoInt_3, /**< \brief TxFifo Interrupt Threshold #3 */
205  IfxQspi_TxFifoInt_4, /**< \brief TxFifo Interrupt Threshold #4 */
207 
208 /** \} */
209 
210 /** \addtogroup IfxLld_Qspi_Std_Operative
211  * \{ */
212 
213 /******************************************************************************/
214 /*-------------------------Inline Function Prototypes-------------------------*/
215 /******************************************************************************/
216 
217 /** \brief Clear ALL service requests
218  * \param qspi Pointer to QSPI module registers
219  * \return None
220  */
221 IFX_INLINE void IfxQspi_clearAllEventFlags(Ifx_QSPI *qspi);
222 
223 /** \brief Clear RX service requests
224  * \param qspi Pointer to QSPI module registers
225  * \return None
226  */
227 IFX_INLINE void IfxQspi_clearRxReq(Ifx_QSPI *qspi);
228 
229 /** \brief Clear TX service requests
230  * \param qspi Pointer to QSPI module registers
231  * \return None
232  */
233 IFX_INLINE void IfxQspi_clearTxReq(Ifx_QSPI *qspi);
234 
235 /**
236  * \param qspi Pointer to QSPI module registers
237  * \return Error Flags
238  */
239 IFX_INLINE uint32 IfxQspi_getErrorFlags(Ifx_QSPI *qspi);
240 
241 /** \brief Request for Module in Pause state
242  * no interrupts
243  * no communication
244  * \param qspi Pointer to QSPI module registers
245  * \return None
246  */
247 IFX_INLINE void IfxQspi_pause(Ifx_QSPI *qspi);
248 
249 /** \brief Read the oldest data from RXFIFO
250  * \param qspi Pointer to QSPI module registers
251  */
253 
254 /** \brief Request for QSPI in Run state
255  * \param qspi Pointer to QSPI module registers
256  * \return None
257  */
258 IFX_INLINE void IfxQspi_run(Ifx_QSPI *qspi);
259 
260 /** \brief Write Data into DATAENTRY register
261  * \param qspi Pointer to QSPI module registers
262  * \param channelId QSPI channel number to which the entered data belongs
263  * \param data Data to be entered into TxFIFO
264  * \return None
265  */
266 IFX_INLINE void IfxQspi_writeTransmitFifo(Ifx_QSPI *qspi, IfxQspi_ChannelId channelId, uint32 data);
267 
268 /******************************************************************************/
269 /*-------------------------Global Function Prototypes-------------------------*/
270 /******************************************************************************/
271 
272 /** \brief Reads 16bit data from the Rx FIFO
273  * \param qspi Pointer to QSPI module registers
274  * \param data Received data will be copied into this array
275  * \param count Number of items to be received
276  * \return None
277  */
278 IFX_EXTERN void IfxQspi_read16(Ifx_QSPI *qspi, uint16 *data, Ifx_SizeT count);
279 
280 /** \brief Reads 32bit data from the Rx FIFO
281  * \param qspi Pointer to QSPI module registers
282  * \param data Received data will be copied into this array
283  * \param count Number of items to be received
284  * \return None
285  */
286 IFX_EXTERN void IfxQspi_read32(Ifx_QSPI *qspi, uint32 *data, Ifx_SizeT count);
287 
288 /** \brief Reads 8bit data from the Rx FIFO
289  * \param qspi Pointer to QSPI module registers
290  * \param data Received data will be copied into this array
291  * \param count Number of items to be received
292  * \return None
293  */
294 IFX_EXTERN void IfxQspi_read8(Ifx_QSPI *qspi, uint8 *data, Ifx_SizeT count);
295 
296 /** \brief Writes 16bit data into the Tx FIFO
297  * \param qspi Pointer to QSPI module registers
298  * \param channelId Channel number to which econ val belongs
299  * \param data Array of data to be sent
300  * \param count Number of items to be sent
301  * \return None
302  */
303 IFX_EXTERN void IfxQspi_write16(Ifx_QSPI *qspi, IfxQspi_ChannelId channelId, uint16 *data, Ifx_SizeT count);
304 
305 /** \brief Writes 32bit data into the Tx FIFO
306  * \param qspi Pointer to QSPI module registers
307  * \param channelId Channel number to which econ val belongs
308  * \param data Array of data to be sent
309  * \param count Number of items to be sent
310  * \return None
311  */
312 IFX_EXTERN void IfxQspi_write32(Ifx_QSPI *qspi, IfxQspi_ChannelId channelId, uint32 *data, Ifx_SizeT count);
313 
314 /** \brief Writes 8bit data into the Tx FIFO
315  * \param qspi Pointer to QSPI module registers
316  * \param channelId Channel number to which econ val belongs
317  * \param data Array of data to be sent
318  * \param count Number of items to be sent
319  * \return None
320  */
321 IFX_EXTERN void IfxQspi_write8(Ifx_QSPI *qspi, IfxQspi_ChannelId channelId, uint8 *data, Ifx_SizeT count);
322 
323 /** \} */
324 
325 /** \addtogroup IfxLld_Qspi_Std_Support
326  * \{ */
327 
328 /******************************************************************************/
329 /*-------------------------Inline Function Prototypes-------------------------*/
330 /******************************************************************************/
331 
332 /** \brief flush the receive FIFO
333  * \param qspi Pointer to QSPI module registers
334  * \return None
335  */
336 IFX_INLINE void IfxQspi_flushReceiveFifo(Ifx_QSPI *qspi);
337 
338 /** \brief flush the transmit FIFO
339  * \param qspi Pointer to QSPI module registers
340  * \return None
341  */
342 IFX_INLINE void IfxQspi_flushTransmitFifo(Ifx_QSPI *qspi);
343 
344 /** \brief Gets the current mode of QSPI
345  * \param qspi Pointer to QSPI module registers
346  * \return The current mode
347  */
348 IFX_INLINE IfxQspi_Mode IfxQspi_getMode(Ifx_QSPI *qspi);
349 
350 /** \brief Specifies function to get module frequency
351  * \param qspi Pointer to QSPI module registers
352  * \return Module frequency in Float value
353  */
354 IFX_INLINE float IfxQspi_getModuleFrequency(Ifx_QSPI *qspi);
355 
356 /** \brief Gets actual transmission phase
357  * \param qspi Pointer to QSPI module registers
358  * \return Actual transmission phase
359  */
361 
362 /** \brief Gets the filling level of RXFIFO
363  * \param qspi Pointer to QSPI module registers
364  * \return RxFIFO level
365  */
367 
368 /** \brief Gets Time Quanta frequency
369  * \param qspi Pointer to QSPI module registers
370  * \return TQ frequency in float
371  */
372 IFX_INLINE float IfxQspi_getTimeQuantaFrequency(Ifx_QSPI *qspi);
373 
374 /** \brief Gets the filling level of TXFIFO
375  * \param qspi Pointer to QSPI module registers
376  * \return TxFIFO level
377  */
379 
380 /** \brief Specifies the Module enable or disable status
381  * \param qspi Pointer to QSPI module registers
382  * \return TRUE if module is enabled otherwise FALSE
383  */
384 IFX_INLINE boolean IfxQspi_isModuleEnabled(Ifx_QSPI *qspi);
385 
386 /** \brief Sets the disable module request
387  * \param qspi Pointer to QSPI module registers
388  * \return None
389  */
390 IFX_INLINE void IfxQspi_setDisableModuleRequest(Ifx_QSPI *qspi);
391 
392 /** \brief Sets the enable module request
393  * \param qspi Pointer to QSPI module registers
394  * \return None
395  */
396 IFX_INLINE void IfxQspi_setEnableModuleRequest(Ifx_QSPI *qspi);
397 
398 /** \brief Set the threshold of RXFIFO for service request generation
399  * \param qspi Pointer to QSPI module registers
400  * \param rxFifoInt RxFIFO Interrupt threshold to set
401  * \return None
402  */
404 
405 /** \brief Sets the disable module request
406  * \param qspi Pointer to QSPI module registers
407  * \param mode Sleep mode selection
408  * \return None
409  */
410 IFX_INLINE void IfxQspi_setSleepMode(Ifx_QSPI *qspi, IfxQspi_SleepMode mode);
411 
412 /** \brief Set the threshold of TXFIFO for service request generation
413  * \param qspi Pointer to QSPI module registers
414  * \param txFifoInt TxFifo Interrupt threshold to set
415  * \return None
416  */
418 
419 /** \brief Write configuration into BACON register
420  * \param qspi Pointer to QSPI module registers
421  * \param baconVal baconVal Value to be entered in BACON register
422  * \return None
423  */
424 IFX_INLINE void IfxQspi_writeBasicConfiguration(Ifx_QSPI *qspi, uint32 baconVal);
425 
426 /** \brief Write configuration into BACON register with .LAST flag set to 0
427  * \param qspi Pointer to QSPI module registers
428  * \param baconVal baconVal Value to be entered in BACON register
429  * \return None
430  */
431 IFX_INLINE void IfxQspi_writeBasicConfigurationBeginStream(Ifx_QSPI *qspi, uint32 baconVal);
432 
433 /** \brief Write configuration into BACON register with .LAST flag set to 1
434  * \param qspi Pointer to QSPI module registers
435  * \param baconVal baconVal Value to be entered in BACON register
436  * \return None
437  */
438 IFX_INLINE void IfxQspi_writeBasicConfigurationEndStream(Ifx_QSPI *qspi, uint32 baconVal);
439 
440 /** \brief Writes channel timing configuration into ECON register
441  * \param qspi Pointer to QSPI module registers
442  * \param channelId Channel number to which econ val belongs
443  * \param econVal Extended configuration value
444  * \return None
445  */
446 IFX_INLINE void IfxQspi_writeExtendedConfiguration(Ifx_QSPI *qspi, IfxQspi_ChannelId channelId, uint32 econVal);
447 
448 /** \brief Writes Data and Configuration into MIXEDENTRY register
449  * \param qspi Pointer to QSPI module registers
450  * \param mixEntryVal Data and configuration in mixed
451  * \return None
452  */
453 IFX_INLINE void IfxQspi_writeMixedDataTransmitFifo(Ifx_QSPI *qspi, uint32 mixEntryVal);
454 
455 /******************************************************************************/
456 /*-------------------------Global Function Prototypes-------------------------*/
457 /******************************************************************************/
458 
459 /** \brief Function to calculate baudrate of specified channel
460  * \param qspi Pointer to QSPI module registers
461  * \param channelId QSPI channel number
462  * \return Actual baudrate in float
463  */
464 IFX_EXTERN float IfxQspi_calcRealBaudrate(Ifx_QSPI *qspi, IfxQspi_ChannelId channelId);
465 
466 /** \brief Function to calculate BACON register values
467  * \param qspi Pointer to QSPI module registers
468  * \param channelId QSPI Channel Number
469  * \param chMode Frame configuration
470  * \param baudrate The desired baudrate
471  * \return Calculated BACON value
472  */
473 IFX_EXTERN uint32 IfxQspi_calculateBasicConfigurationValue(Ifx_QSPI *qspi, const IfxQspi_ChannelId channelId, const SpiIf_ChMode *chMode, const float baudrate);
474 
475 /** \brief Function to calculate ECON register values
476  * \param qspi Pointer to QSPI module registers
477  * \param cs QSPI channel Number : 8->0,9->1,.......
478  * \param chConfig SPI Channel Configuration
479  * \return Calculated ECON[CS] value
480  */
481 IFX_EXTERN uint32 IfxQspi_calculateExtendedConfigurationValue(Ifx_QSPI *qspi, const uint8 cs, const SpiIf_ChConfig *chConfig);
482 
483 /** \brief Function to calculate prescaler
484  * \param qspi Pointer to QSPI module registers
485  * \param baudrate Maximum baudrate in Float
486  * \return Prescaler in integer
487  */
488 IFX_EXTERN uint32 IfxQspi_calculatePrescaler(Ifx_QSPI *qspi, float baudrate);
489 
490 /** \brief Specifies the function to calculate Time quantum length
491  * \param qspi Pointer to QSPI module registers
492  * \param maxBaudrate Maximum baudrate in Float
493  * \return Time quantum length in integer
494  */
495 IFX_EXTERN uint32 IfxQspi_calculateTimeQuantumLength(Ifx_QSPI *qspi, float maxBaudrate);
496 
497 /** \brief Re-calculated BACON from the oldBACON
498  * \param oldBACON Old BACON value
499  * \param numOfData numOfData in LONG or CONTINUOUS mode
500  * \param shortData Specifies SHORT mode (TRUE) or other modes (FALSE)
501  * \param lastData Specifies last data in LONG or CONTINUOUS
502  * \return Re-calculated BACON
503  */
504 IFX_EXTERN uint32 IfxQspi_recalcBasicConfiguration(uint32 oldBACON, Ifx_SizeT numOfData, boolean shortData, boolean lastData);
505 
506 /** \brief Configures a Slave Select Output
507  * \param qspi Pointer to QSPI module registers
508  * \param channelId Channel number to which econ val belongs
509  * \param outputEnable chip select output will be enabled during transaction
510  * \param activeLevel TRUE: active-high, FALSE: active-low
511  * \return None
512  */
513 IFX_EXTERN void IfxQspi_setSlaveSelectOutputControl(Ifx_QSPI *qspi, IfxQspi_ChannelId channelId, boolean outputEnable, boolean activeLevel);
514 
515 /** \} */
516 
517 /** \addtogroup IfxLld_Qspi_Std_Interrupt
518  * \{ */
519 
520 /******************************************************************************/
521 /*-------------------------Inline Function Prototypes-------------------------*/
522 /******************************************************************************/
523 
524 /** \brief Specifies the function to get Index
525  * \param qspi Pointer to QSPI module registers
526  * \return Index in Integer
527  */
528 IFX_INLINE uint32 IfxQspi_getIndex(Ifx_QSPI *qspi);
529 
530 /** \brief Gets the Error request value
531  * \param qspi Pointer to QSPI module registers
532  * \return Error request value
533  */
534 IFX_INLINE volatile Ifx_SRC_SRCR *IfxQspi_getErrorSrc(Ifx_QSPI *qspi);
535 
536 /** \brief Gets the RXFIFO service request
537  * \param qspi Pointer to QSPI module registers
538  * \return Receive service request value
539  */
540 IFX_INLINE volatile Ifx_SRC_SRCR *IfxQspi_getReceiveSrc(Ifx_QSPI *qspi);
541 
542 /** \brief Gets the TXFIFO service request
543  * \param qspi Pointer to QSPI module registers
544  * \return Transmission service request value
545  */
546 IFX_INLINE volatile Ifx_SRC_SRCR *IfxQspi_getTransmitSrc(Ifx_QSPI *qspi);
547 
548 /** \} */
549 
550 /** \addtogroup IfxLld_Qspi_Std_IO
551  * \{ */
552 
553 /******************************************************************************/
554 /*-------------------------Inline Function Prototypes-------------------------*/
555 /******************************************************************************/
556 
557 /** \brief Initializes a MRST input
558  * \param mrstIn the MRST Pin which should be configured
559  * \param mrstInMode the pin input mode which should be configured
560  * \return None
561  */
562 IFX_INLINE void IfxQspi_initMrstInPin(const IfxQspi_Mrst_In *mrstIn, IfxPort_InputMode mrstInMode);
563 
564 /** \brief Initializes a MRST output
565  * \param mrstOut the MRST Pin which should be configured
566  * \param mrstOutMode the pin output mode which should be configured
567  * \param padDriver the pad driver mode which should be configured
568  * \return None
569  */
570 IFX_INLINE void IfxQspi_initMrstOutPin(const IfxQspi_Mrst_Out *mrstOut, IfxPort_OutputMode mrstOutMode, IfxPort_PadDriver padDriver);
571 
572 /** \brief Initializes a MTSR input
573  * \param mtsrIn the MTSR Pin which should be configured
574  * \param mtsrInMode the pin input mode which should be configured
575  * \return None
576  */
577 IFX_INLINE void IfxQspi_initMtsrInPin(const IfxQspi_Mtsr_In *mtsrIn, IfxPort_InputMode mtsrInMode);
578 
579 /** \brief Initializes a MTSR output
580  * \param mtsrOut the MTSR Pin which should be configured
581  * \param mtsrOutMode the pin output mode which should be configured
582  * \param padDriver the pad driver mode which should be configured
583  * \return None
584  */
585 IFX_INLINE void IfxQspi_initMtsrOutPin(const IfxQspi_Mtsr_Out *mtsrOut, IfxPort_OutputMode mtsrOutMode, IfxPort_PadDriver padDriver);
586 
587 /** \brief Initializes a SCLK input
588  * \param sclkIn the SCLK Pin which should be configured
589  * \param sclkInMode the pin input mode which should be configured
590  * \return None
591  */
592 IFX_INLINE void IfxQspi_initSclkInPin(const IfxQspi_Sclk_In *sclkIn, IfxPort_InputMode sclkInMode);
593 
594 /** \brief Initializes a SCLK output
595  * \param sclkOut the SCLK Pin which should be configured
596  * \param sclkOutMode the pin output mode which should be configured
597  * \param padDriver the pad driver mode which should be configured
598  * \return None
599  */
600 IFX_INLINE void IfxQspi_initSclkOutPin(const IfxQspi_Sclk_Out *sclkOut, IfxPort_OutputMode sclkOutMode, IfxPort_PadDriver padDriver);
601 
602 /** \brief Initializes a SLSI input
603  * \param slsi the SLSI Pin which should be configured
604  * \param slsiMode the pin input mode which should be configured
605  * \return None
606  */
608 
609 /** \brief Initializes a SLSO output
610  * \param slso the SLSO Pin which should be configured
611  * \param slsoMode the pin output mode which should be configured
612  * \param padDriver the pad driver mode which should be configured
613  * \param outIndex Pin Pad driver index
614  * \return None
615  */
617 
618 /** \} */
619 
620 /******************************************************************************/
621 /*---------------------Inline Function Implementations------------------------*/
622 /******************************************************************************/
623 
625 {
626  qspi->FLAGSCLEAR.U = 0xFFFFU;
627 }
628 
629 
630 IFX_INLINE void IfxQspi_clearRxReq(Ifx_QSPI *qspi)
631 {
632  qspi->FLAGSCLEAR.B.RXC = 1U;
633 }
634 
635 
636 IFX_INLINE void IfxQspi_clearTxReq(Ifx_QSPI *qspi)
637 {
638  qspi->FLAGSCLEAR.B.TXC = 1U;
639 }
640 
641 
643 {
644  return qspi->STATUS.B.ERRORFLAGS;
645 }
646 
647 
648 IFX_INLINE void IfxQspi_pause(Ifx_QSPI *qspi)
649 {
650  qspi->GLOBALCON.B.EN = 0;
651 
652  while (IfxQspi_getPhase(qspi) != IfxQspi_Phase_wait)
653  {}
654 }
655 
656 
658 {
659  return qspi->RXEXIT.U;
660 }
661 
662 
663 IFX_INLINE void IfxQspi_run(Ifx_QSPI *qspi)
664 {
665  qspi->GLOBALCON.B.EN = 1;
666 }
667 
668 
669 IFX_INLINE void IfxQspi_writeTransmitFifo(Ifx_QSPI *qspi, IfxQspi_ChannelId channelId, uint32 data)
670 {
671  int cs = channelId % 8;
672  qspi->DATAENTRY[cs].U = data;
673 }
674 
675 
677 {
678  // Flush RXFIFO
679  qspi->GLOBALCON.B.RESETS = 4;
680 }
681 
682 
684 {
685  // Flush TXFIFO
686  qspi->GLOBALCON.B.RESETS = 2;
687 }
688 
689 
691 {
692  return (IfxQspi_Mode)qspi->GLOBALCON.B.MS;
693 }
694 
695 
697 {
698  return IfxScuCcu_getMaxFrequency();
699 }
700 
701 
703 {
704  return (IfxQspi_Phase)qspi->STATUS.B.PHASE;
705 }
706 
707 
709 {
710  return qspi->STATUS.B.RXFIFOLEVEL;
711 }
712 
713 
715 {
716  return IfxQspi_getModuleFrequency(qspi) / (qspi->GLOBALCON.B.TQ + 1);
717 }
718 
719 
721 {
722  return qspi->STATUS.B.TXFIFOLEVEL;
723 }
724 
725 
726 IFX_INLINE boolean IfxQspi_isModuleEnabled(Ifx_QSPI *qspi)
727 {
728  return (qspi->CLC.B.DISS == 0) ? TRUE : FALSE;
729 }
730 
731 
733 {
734  qspi->CLC.B.DISR = 1;
735 }
736 
737 
739 {
740  qspi->CLC.B.DISR = 0;
741 }
742 
743 
745 {
746  qspi->GLOBALCON1.B.RXFIFOINT = rxFifoInt;
747 }
748 
749 
751 {
752  qspi->CLC.B.EDIS = mode;
753 }
754 
755 
757 {
758  qspi->GLOBALCON1.B.TXFIFOINT = txFifoInt;
759 }
760 
761 
762 IFX_INLINE void IfxQspi_writeBasicConfiguration(Ifx_QSPI *qspi, uint32 baconVal)
763 {
764  qspi->BACONENTRY.U = baconVal;
765 }
766 
767 
769 {
770  Ifx_QSPI_BACON bacon;
771  bacon.U = baconVal;
772  bacon.B.LAST = 0;
773 
774  qspi->BACONENTRY.U = bacon.U;
775 }
776 
777 
779 {
780  Ifx_QSPI_BACON bacon;
781  bacon.U = baconVal;
782  bacon.B.LAST = 1;
783 
784  qspi->BACONENTRY.U = bacon.U;
785 }
786 
787 
789 {
790  int cs = channelId % 8;
791  qspi->ECON[cs].U = econVal;
792 }
793 
794 
795 IFX_INLINE void IfxQspi_writeMixedDataTransmitFifo(Ifx_QSPI *qspi, uint32 mixEntryVal)
796 {
797  qspi->MIXENTRY.U = mixEntryVal;
798 }
799 
800 
802 {
803  uint32 base = (uint32)&MODULE_QSPI0;
804  uint32 singleDistance = ((uint32)&MODULE_QSPI1) - base;
805  uint32 distance = ((uint32)qspi) - base;
806  uint32 index = distance / singleDistance;
807  return index;
808 }
809 
810 
811 IFX_INLINE volatile Ifx_SRC_SRCR *IfxQspi_getErrorSrc(Ifx_QSPI *qspi)
812 {
813  uint32 index = IfxQspi_getIndex(qspi);
814  return &MODULE_SRC.QSPI.QSPI[index].ERR;
815 }
816 
817 
818 IFX_INLINE volatile Ifx_SRC_SRCR *IfxQspi_getReceiveSrc(Ifx_QSPI *qspi)
819 {
820  uint32 index = IfxQspi_getIndex(qspi);
821  return &MODULE_SRC.QSPI.QSPI[index].RX;
822 }
823 
824 
825 IFX_INLINE volatile Ifx_SRC_SRCR *IfxQspi_getTransmitSrc(Ifx_QSPI *qspi)
826 {
827  uint32 index = IfxQspi_getIndex(qspi);
828  return &MODULE_SRC.QSPI.QSPI[index].TX;
829 }
830 
831 
833 {
834  IfxPort_setPinModeInput(mrstIn->pin.port, mrstIn->pin.pinIndex, mrstInMode);
835  mrstIn->module->PISEL.B.MRIS = mrstIn->select;
836 }
837 
838 
840 {
841  IfxPort_setPinModeOutput(mrstOut->pin.port, mrstOut->pin.pinIndex, mrstOutMode, mrstOut->select);
842  IfxPort_setPinPadDriver(mrstOut->pin.port, mrstOut->pin.pinIndex, padDriver);
843 }
844 
845 
847 {
848  IfxPort_setPinModeInput(mtsrIn->pin.port, mtsrIn->pin.pinIndex, mtsrInMode);
849  mtsrIn->module->PISEL.B.SRIS = mtsrIn->select;
850 }
851 
852 
854 {
855  IfxPort_setPinModeOutput(mtsrOut->pin.port, mtsrOut->pin.pinIndex, mtsrOutMode, mtsrOut->select);
856  IfxPort_setPinPadDriver(mtsrOut->pin.port, mtsrOut->pin.pinIndex, padDriver);
857 }
858 
859 
861 {
862  IfxPort_setPinModeInput(sclkIn->pin.port, sclkIn->pin.pinIndex, sclkInMode);
863  sclkIn->module->PISEL.B.SCIS = sclkIn->select;
864 }
865 
866 
868 {
869  IfxPort_setPinModeOutput(sclkOut->pin.port, sclkOut->pin.pinIndex, sclkOutMode, sclkOut->select);
870  IfxPort_setPinPadDriver(sclkOut->pin.port, sclkOut->pin.pinIndex, padDriver);
871 }
872 
873 
875 {
876  IfxPort_setPinModeInput(slsi->pin.port, slsi->pin.pinIndex, slsiMode);
877  /* PISEL */
878  slsi->module->PISEL.B.SLSIS = slsi->select + 1;
879 }
880 
881 
883 {
884  IfxPort_setPinModeOutput(slso->pin.port, slso->pin.pinIndex, slsoMode, outIndex);
885  IfxPort_setPinPadDriver(slso->pin.port, slso->pin.pinIndex, padDriver);
886 }
887 
888 
889 #endif /* IFXQSPI_H */