iLLD_TC27xC
1.0
IfxPsi5s.h
Go to the documentation of this file.
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/**
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* \file IfxPsi5s.h
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* \brief PSI5S basic functionality
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* \ingroup IfxLld_Psi5s
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*
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* \version iLLD_0_1_0_10
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* \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
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*
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*
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* IMPORTANT NOTICE
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*
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*
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* Infineon Technologies AG (Infineon) is supplying this file for use
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* exclusively with Infineon's microcontroller products. This file can be freely
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* distributed within development tools that are supporting such microcontroller
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* products.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
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* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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*
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* \defgroup IfxLld_Psi5s PSI5S
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* \ingroup IfxLld
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* \defgroup IfxLld_Psi5s_Std Standard Driver
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* \ingroup IfxLld_Psi5s
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* \defgroup IfxLld_Psi5s_Std_Enumerations Enumerations
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* \ingroup IfxLld_Psi5s_Std
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* \defgroup IfxLld_Psi5s_Std_Channel Channel Operative Functions
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* \ingroup IfxLld_Psi5s_Std
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* \defgroup IfxLld_Psi5s_Std_IO IO Pin Configuration Functions
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* \ingroup IfxLld_Psi5s_Std
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*/
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#ifndef IFXPSI5S_H
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#define IFXPSI5S_H 1
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/******************************************************************************/
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/*----------------------------------Includes----------------------------------*/
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/******************************************************************************/
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#include "
_Impl/IfxPsi5s_cfg.h
"
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#include "
_PinMap/IfxPsi5s_PinMap.h
"
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/******************************************************************************/
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/*--------------------------------Enumerations--------------------------------*/
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/******************************************************************************/
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/** \addtogroup IfxLld_Psi5s_Std_Enumerations
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* \{ */
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/** \brief MODULE_PSI5S.IOCR.ALTI:Alternate input
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*/
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typedef
enum
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{
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IfxPsi5s_AlternateInput_0
= 0,
/**< \brief Alternate Input 0 */
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IfxPsi5s_AlternateInput_1
,
/**< \brief Alternate Input 1 */
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IfxPsi5s_AlternateInput_2
,
/**< \brief Alternate Input 2 */
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IfxPsi5s_AlternateInput_3
,
/**< \brief Alternate Input 3 */
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}
IfxPsi5s_AlternateInput
;
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/** \brief MODULE_PSI5S.BG.BR_VALUE:Baudrate prescalar select
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*/
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typedef
enum
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{
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IfxPsi5s_AscBaudratePrescalar_divideBy2
= 0,
/**< \brief Divide by 2 is selected for baudrate timer prescalar */
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IfxPsi5s_AscBaudratePrescalar_divideBy3
= 1
/**< \brief Divide by 3 is selected for baudrate timer prescalar */
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}
IfxPsi5s_AscBaudratePrescalar
;
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/** \brief MODULE_PSI5S.CON.M:ASC mode of operation
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*/
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typedef
enum
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{
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IfxPsi5s_AscMode_sync
= 0,
/**< \brief Synchronous mode */
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IfxPsi5s_AscMode_async_8bitData
= 1,
/**< \brief Asynchronous mode with 8 bit data */
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IfxPsi5s_AscMode_async_7bitDataWithParity
= 3,
/**< \brief Asynchronous mode with 7 bit data with parity */
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IfxPsi5s_AscMode_async_9bitData
= 4,
/**< \brief Asynchronous mode with 9 bit data */
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IfxPsi5s_AscMode_async_8bitDataWithWakeup
= 5,
/**< \brief Asynchronous mode with 8 bit data with wakeup */
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IfxPsi5s_AscMode_async_8bitDataWithParity
= 7
/**< \brief Asynchronous mode with 8 bit data with parity */
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}
IfxPsi5s_AscMode
;
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/** \brief MODULE_PSI5S.CON.STP: Number of stop bits
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*/
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typedef
enum
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{
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IfxPsi5s_AscStopBits_1
= 0,
/**< \brief 1 stop bit */
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IfxPsi5s_AscStopBits_2
,
/**< \brief 2 stop bit */
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}
IfxPsi5s_AscStopBits
;
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/** \brief PSI5S Channel Id defined in MODULE_PSI5S.RDS.B.CID.
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*/
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typedef
enum
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{
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IfxPsi5s_ChannelId_0
= 0,
/**< \brief Ifx_PSI5S Channel 0 */
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IfxPsi5s_ChannelId_1
,
/**< \brief Ifx_PSI5S Channel 1 */
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IfxPsi5s_ChannelId_2
,
/**< \brief Ifx_PSI5S Channel 2 */
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IfxPsi5s_ChannelId_3
,
/**< \brief Ifx_PSI5S Channel 3 */
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IfxPsi5s_ChannelId_4
,
/**< \brief Ifx_PSI5S Channel 4 */
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IfxPsi5s_ChannelId_5
,
/**< \brief Ifx_PSI5S Channel 5 */
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IfxPsi5s_ChannelId_6
,
/**< \brief Ifx_PSI5S Channel 6 */
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IfxPsi5s_ChannelId_7
,
/**< \brief Ifx_PSI5S Channel 7 */
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IfxPsi5s_ChannelId_none
= -1
/**< \brief None of the Ifx_PSI5S Channels */
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}
IfxPsi5s_ChannelId
;
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/** \brief Clock Selection
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*/
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typedef
enum
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{
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IfxPsi5s_ClockType_fracDiv
= 0,
/**< \brief Fractional Divide clock */
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IfxPsi5s_ClockType_timeStamp
= 1,
/**< \brief Timestamp clock */
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IfxPsi5s_ClockType_ascFracDiv
= 2,
/**< \brief Asc Fractional divider clock */
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IfxPsi5s_ClockType_ascOutput
= 3
/**< \brief Asc output clock */
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}
IfxPsi5s_ClockType
;
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/** \brief MODULE_PSI5S.RCRAx.CRCy(x= 0,1,..7:y=0,1,..,5),MODULE_PSI5S.RCRBx.CRCy(x= 0,1,..7:y=0,1,..,5)CRC or parity
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*/
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typedef
enum
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{
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IfxPsi5s_CrcOrParity_parity
= 0,
/**< \brief parity selection */
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IfxPsi5s_CrcOrParity_crc
= 1
/**< \brief CRC selection */
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}
IfxPsi5s_CrcOrParity
;
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/** \brief MODULE_PSI5S.FDR.DM;MODULE_PSI5S.FDRT.B.DM:Divider mode
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*/
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typedef
enum
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{
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IfxPsi5s_DividerMode_spb
= 0,
/**< \brief divider mode is off */
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IfxPsi5s_DividerMode_normal
= 1,
/**< \brief divider mode is normal */
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IfxPsi5s_DividerMode_fractional
= 2,
/**< \brief divider mode is fractional */
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IfxPsi5s_DividerMode_off
= 3
/**< \brief divider mode is off */
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}
IfxPsi5s_DividerMode
;
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/** \brief MODULE_PSI5S.SCRx.EPS(x=0,1,...,7):Enhanced protocol types
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*/
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typedef
enum
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{
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IfxPsi5s_EnhancedProtocol_toothGapMethod
= 0,
/**< \brief toothGapMethod Enhanced protocol type */
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IfxPsi5s_EnhancedProtocol_pulseWidth_frameFormat_1to3
= 1,
/**< \brief pulseWidth_frameFormat_1to3 Enhanced protocol type */
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IfxPsi5s_EnhancedProtocol_pulseWidth_frameFormat_4
= 3
/**< \brief pulseWidth_frameFormat_4 Enhanced protocol type */
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}
IfxPsi5s_EnhancedProtocol
;
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/** \brief MODULE_PSI5S.RCRAx.FIDS(x=0,1,....,7):.Frame ID updation
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*/
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typedef
enum
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{
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IfxPsi5s_FrameId_frameHeader
= 0,
/**< \brief Frame ID is updated from packet frame header (Sync mode) */
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IfxPsi5s_FrameId_rollingNumber
= 1
/**< \brief Frame ID is a rolling number 0 .. 5 copied from FCNT */
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}
IfxPsi5s_FrameId
;
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/** \brief MODULE_PSI5S.GCR.IDT:Idle time bit count
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*/
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typedef
enum
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{
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IfxPsi5s_IdleTime_1
= 0,
/**< \brief 1 bit Idle time */
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IfxPsi5s_IdleTime_2
,
/**< \brief 2 bit Idle time */
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IfxPsi5s_IdleTime_3
,
/**< \brief 3 bit Idle time */
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IfxPsi5s_IdleTime_4
,
/**< \brief 4 bit Idle time */
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IfxPsi5s_IdleTime_5
,
/**< \brief 5 bit Idle time */
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IfxPsi5s_IdleTime_6
,
/**< \brief 6 bit Idle time */
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IfxPsi5s_IdleTime_7
,
/**< \brief 7 bit Idle time */
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IfxPsi5s_IdleTime_8
,
/**< \brief 8 bit Idle time */
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IfxPsi5s_IdleTime_9
,
/**< \brief 9 bit Idle time */
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IfxPsi5s_IdleTime_10
,
/**< \brief 10 bit Idle time */
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IfxPsi5s_IdleTime_11
,
/**< \brief 11 bit Idle time */
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IfxPsi5s_IdleTime_12
,
/**< \brief 12 bit Idle time */
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IfxPsi5s_IdleTime_13
,
/**< \brief 13 bit Idle time */
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IfxPsi5s_IdleTime_14
,
/**< \brief 14 bit Idle time */
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IfxPsi5s_IdleTime_15
,
/**< \brief 15 bit Idle time */
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IfxPsi5s_IdleTime_16
,
/**< \brief 16 bit Idle time */
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}
IfxPsi5s_IdleTime
;
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/** \brief Messaging bits presence
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*/
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typedef
enum
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{
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IfxPsi5s_MessagingBits_absent
= 0,
/**< \brief No messaging bits */
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IfxPsi5s_MessagingBits_present
= 1
/**< \brief 2 messaging bits */
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}
IfxPsi5s_MessagingBits
;
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/** \brief MODULE_PSI5S.NFC.NFx:Expected Psi5s frames
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*/
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typedef
enum
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{
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IfxPsi5s_NumberExpectedFrames_1
= 1,
/**< \brief 1 psi5s frame expected */
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IfxPsi5s_NumberExpectedFrames_2
,
/**< \brief 2 psi5s frame expected */
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IfxPsi5s_NumberExpectedFrames_3
,
/**< \brief 3 psi5s frame expected */
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IfxPsi5s_NumberExpectedFrames_4
,
/**< \brief 4 psi5s frame expected */
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IfxPsi5s_NumberExpectedFrames_5
,
/**< \brief 5 psi5s frame expected */
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IfxPsi5s_NumberExpectedFrames_6
,
/**< \brief 6 psi5s frame expected */
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}
IfxPsi5s_NumberExpectedFrames
;
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/** \brief MODULE_PSI5S.TSCNTA.B.TBS;MODULE_PSI5S.TSCNTB.B.TBS:Time base
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*/
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typedef
enum
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{
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IfxPsi5s_TimeBase_internal
= 0,
/**< \brief Internal time stamp clock */
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IfxPsi5s_TimeBase_external
= 1
/**< \brief External GTM inputs */
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}
IfxPsi5s_TimeBase
;
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/** \brief MODULE_PSI5S.TSCNTx(x= A,B):Timestamp register
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*/
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typedef
enum
203
{
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IfxPsi5s_TimestampRegister_a
= 0,
/**< \brief Timestamp register A */
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IfxPsi5s_TimestampRegister_b
= 1
/**< \brief Timestamp register B */
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}
IfxPsi5s_TimestampRegister
;
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/** \brief MODULE_PSI5S.RCRAx.TSTS:Timestamp trigger
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*/
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typedef
enum
211
{
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IfxPsi5s_TimestampTrigger_syncPulse
= 0,
/**< \brief Timestamp trigger on sync pulse */
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IfxPsi5s_TimestampTrigger_frame
= 1
/**< \brief Timestamp trigger on any frame */
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}
IfxPsi5s_TimestampTrigger
;
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/** \brief MODULE_PSI5S.TSCNTA.B.ETB;MODULE_PSI5S.TSCNTB.B.ETB:Trigger Id
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*/
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typedef
enum
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{
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IfxPsi5s_Trigger_0
= 0,
/**< \brief Trigger 0 */
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IfxPsi5s_Trigger_1
,
/**< \brief Trigger 1 */
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IfxPsi5s_Trigger_2
,
/**< \brief Trigger 2 */
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IfxPsi5s_Trigger_3
,
/**< \brief Trigger 3 */
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IfxPsi5s_Trigger_4
,
/**< \brief Trigger 4 */
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IfxPsi5s_Trigger_5
,
/**< \brief Trigger 5 */
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IfxPsi5s_Trigger_6
,
/**< \brief Trigger 6 */
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IfxPsi5s_Trigger_7
,
/**< \brief Trigger 7 */
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}
IfxPsi5s_Trigger
;
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/** \brief Trigger type defined in
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*/
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typedef
enum
233
{
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IfxPsi5s_TriggerType_periodic
= 0,
/**< \brief Periodic trigger */
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IfxPsi5s_TriggerType_external
= 1
/**< \brief External trigger */
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}
IfxPsi5s_TriggerType
;
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/** \brief MODULE_PSI5S.RCRAx.UFCY(x=0,1,...7;y=0,1...5):UART frame count
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*/
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typedef
enum
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{
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IfxPsi5s_UartFrameCount_3
= 0,
/**< \brief 3 UART frames */
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IfxPsi5s_UartFrameCount_4
,
/**< \brief 4 UART frames */
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IfxPsi5s_UartFrameCount_5
,
/**< \brief 5 UART frames */
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IfxPsi5s_UartFrameCount_6
,
/**< \brief 6 UART frames */
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}
IfxPsi5s_UartFrameCount
;
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/** \brief MODULE_PSI5S.RCRAx.WDMS:Watchdog timer mode
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*/
250
typedef
enum
251
{
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IfxPsi5s_WatchdogTimerMode_frame
= 0,
/**< \brief Watch Dog Timer is restarted on reception of each recoverable frame (async mode) */
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IfxPsi5s_WatchdogTimerMode_syncPulse
= 1
/**< \brief Watch Dog Timer is restarted on Sync Pulse and stopped at reception of the last frame configured in NFC.NFx.(sync mode) */
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}
IfxPsi5s_WatchdogTimerMode
;
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/** \} */
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/** \addtogroup IfxLld_Psi5s_Std_Channel
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* \{ */
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/******************************************************************************/
262
/*-------------------------Global Function Prototypes-------------------------*/
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/******************************************************************************/
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/** \brief Enable ASC receiver
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* \param psi5s pointer to the PSI5S register space
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* \return None
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*/
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IFX_EXTERN
void
IfxPsi5s_enableAscReceiver
(Ifx_PSI5S *psi5s);
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/** \brief Enable/disable any combination of channel trigger counters selected by mask parameter
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* \param psi5s pointer to the PSI5S register space
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* \param channels specifies the channel trigger counters which should be enabled/disabled
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* \param mask specifies the channel trigger counters which should be modified
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* \return None
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*/
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IFX_EXTERN
void
IfxPsi5s_enableDisableChannelTriggerCounters
(Ifx_PSI5S *psi5s,
uint32
channels,
uint32
mask);
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/** \brief Enable/disable any combination of channels selected by mask parameter
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* \param psi5s pointer to the PSI5S register space
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* \param channels specifies the channels which should be enabled/disabled
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* \param mask specifies the channels which should be modified
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* \return None
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*/
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IFX_EXTERN
void
IfxPsi5s_enableDisableChannels
(Ifx_PSI5S *psi5s,
uint32
channels,
uint32
mask);
286
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/** \brief Start ASC transactions
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* \param psi5s pointer to the PSI5S register space
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* \return None
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*/
291
IFX_EXTERN
void
IfxPsi5s_startAscTransactions
(Ifx_PSI5S *psi5s);
292
293
/** \} */
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/** \addtogroup IfxLld_Psi5s_Std_IO
296
* \{ */
297
298
/******************************************************************************/
299
/*-------------------------Inline Function Prototypes-------------------------*/
300
/******************************************************************************/
301
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/** \brief Selects the alternate input for Rx signal
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* \param psi5s pointer to PSI5S registers
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* \param alti alternate input selection of Rx signal
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* \return None
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*/
307
IFX_INLINE
void
IfxPsi5s_setRxInput
(Ifx_PSI5S *psi5s,
IfxPsi5s_AlternateInput
alti);
308
309
/** \brief Initializes a RX input
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* \param rx the RX Pin which should be configured
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* \param inputMode the pin input mode which should be configured
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* \return None
313
*/
314
IFX_INLINE
void
IfxPsi5s_initRxPin
(
const
IfxPsi5s_Rx_In
*rx,
IfxPort_InputMode
inputMode);
315
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/** \brief Initializes a SCLK output
317
* \param sclk the SCLK Pin which should be configured
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* \param outputMode the pin output mode which should be configured
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* \param padDriver the pad driver mode which should be configured
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* \return None
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*/
322
IFX_INLINE
void
IfxPsi5s_initSclkPin
(
const
IfxPsi5s_Sclk_Out
*sclk,
IfxPort_OutputMode
outputMode,
IfxPort_PadDriver
padDriver);
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/** \brief Initializes a TX output
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* \param tx the TX Pin which should be configured
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* \param outputMode the pin output mode which should be configured
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* \param padDriver the pad driver mode which should be configured
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* \return None
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*/
330
IFX_INLINE
void
IfxPsi5s_initTxPin
(
const
IfxPsi5s_Tx_Out
*tx,
IfxPort_OutputMode
outputMode,
IfxPort_PadDriver
padDriver);
331
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/** \} */
333
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/******************************************************************************/
335
/*---------------------Inline Function Implementations------------------------*/
336
/******************************************************************************/
337
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IFX_INLINE
void
IfxPsi5s_setRxInput
(Ifx_PSI5S *psi5s,
IfxPsi5s_AlternateInput
alti)
339
{
340
psi5s->IOCR.B.ALTI = alti;
341
}
342
343
344
IFX_INLINE
void
IfxPsi5s_initRxPin
(
const
IfxPsi5s_Rx_In
*rx,
IfxPort_InputMode
inputMode)
345
{
346
IfxPort_setPinModeInput
(rx->
pin
.
port
, rx->
pin
.
pinIndex
, inputMode);
347
IfxPsi5s_setRxInput
(rx->
module
, (
IfxPsi5s_AlternateInput
)rx->
select
);
348
}
349
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351
IFX_INLINE
void
IfxPsi5s_initSclkPin
(
const
IfxPsi5s_Sclk_Out
*sclk,
IfxPort_OutputMode
outputMode,
IfxPort_PadDriver
padDriver)
352
{
353
IfxPort_setPinModeOutput
(sclk->
pin
.
port
, sclk->
pin
.
pinIndex
, outputMode, sclk->
select
);
354
IfxPort_setPinPadDriver
(sclk->
pin
.
port
, sclk->
pin
.
pinIndex
, padDriver);
355
}
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358
IFX_INLINE
void
IfxPsi5s_initTxPin
(
const
IfxPsi5s_Tx_Out
*tx,
IfxPort_OutputMode
outputMode,
IfxPort_PadDriver
padDriver)
359
{
360
IfxPort_setPinModeOutput
(tx->
pin
.
port
, tx->
pin
.
pinIndex
, outputMode, tx->
select
);
361
IfxPort_setPinPadDriver
(tx->
pin
.
port
, tx->
pin
.
pinIndex
, padDriver);
362
}
363
364
365
#endif
/* IFXPSI5S_H */
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IfxPsi5s.h
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