iLLD_TC27xC  1.0
IfxScu_cfg.h File Reference

SCU on-chip implementation data. More...

#include "Ifx_Cfg.h"
#include "IfxScu_bf.h"
#include "IfxFlash_bf.h"

Go to the source code of this file.

Macros

#define IFX_CFG_SCU_XTAL_FREQUENCY   20000000
 Default External oscillator frequency. More...
 
#define IFX_CFG_SCU_PLL_FREQUENCY   200000000
 Default PLL frequency. More...
 
#define IFXSCU_VCO_BASE_FREQUENCY   (100000000.0)
 
#define IFXSCU_EVR_OSC_FREQUENCY   (100000000.0)
 
#define IFXSCU_PLL_FREERUNNING_FREQUENCY   (100000000.0)
 
#define IFXSCU_CFG_PLL_STEPS_16MHZ_80MHZ
 Macros to configure Pll steps, Macros to configure the Pll steps for different profiles of Crystal frequency and target frequencies. This configuration is important for the current jump controll during clock throttling. IfxScuCcu_PllStepsConfig. More...
 
#define IFXSCU_CFG_PLL_STEPS_16MHZ_133MHZ
 Macro for Pll step for profile with 16MHz Crystal and 133MHz target. More...
 
#define IFXSCU_CFG_PLL_STEPS_16MHZ_160MHZ
 Macro for Pll step for profile with 16MHz Crystal and 160MHz target. More...
 
#define IFXSCU_CFG_PLL_STEPS_16MHZ_200MHZ
 Macro for Pll step for profile with 16MHz Crystal and 200MHz target. More...
 
#define IFXSCU_CFG_PLL_STEPS_16MHZ_240MHZ
 Macro for Pll step for profile with 16MHz Crystal and 240MHz target. More...
 
#define IFXSCU_CFG_PLL_STEPS_20MHZ_80MHZ
 Macro for Pll step for profile with 20MHz Crystal and 80MHz target. More...
 
#define IFXSCU_CFG_PLL_STEPS_20MHZ_133MHZ
 Macro for Pll step for profile with 20MHz Crystal and 133MHz target. More...
 
#define IFXSCU_CFG_PLL_STEPS_20MHZ_160MHZ
 Macro for Pll step for profile with 20MHz Crystal and 160MHz target. More...
 
#define IFXSCU_CFG_PLL_STEPS_20MHZ_200MHZ
 Macro for Pll step for profile with 20MHz Crystal and 200MHz target. More...
 
#define IFXSCU_CFG_PLL_STEPS_20MHZ_240MHZ
 Macro for Pll step for profile with 20MHz Crystal and 240MHz target. More...
 
#define IFXSCU_CFG_PLL_STEPS_20MHZ_300MHZ
 Macro for Pll step for profile with 20MHz Crystal and 300MHz target. More...
 
#define IFXSCU_CFG_PLL_STEPS_40MHZ_80MHZ
 Macro for Pll step for profile with 40MHz Crystal and 80MHz target. More...
 
#define IFXSCU_CFG_PLL_STEPS_40MHZ_133MHZ
 Macro for Pll step for profile with 40MHz Crystal and 133MHz target. More...
 
#define IFXSCU_CFG_PLL_STEPS_40MHZ_160MHZ
 Macro for Pll step for profile with 40MHz Crystal and 160MHz target. More...
 
#define IFXSCU_CFG_PLL_STEPS_40MHZ_200MHZ
 Macro for Pll step for profile with 40MHz Crystal and 200MHz target. More...
 
#define IFXSCU_CFG_PLL_STEPS_40MHZ_240MHZ
 Macro for Pll step for profile with 40MHz Crystal and 240MHz target. More...
 
#define IFXSCU_CFG_PLL_STEPS_40MHZ_300MHZ
 Macro for Pll step for profile with 40MHz Crystal and 300MHz target. More...
 
#define IFXSCU_CFG_PLL_STEPS_8MHZ_80MHZ
 Macro for Pll step for profile with 8MHz Crystal and 80MHz target. More...
 
#define IFXSCU_CFG_PLL_STEPS_8MHZ_160MHZ
 Macro for Pll step for profile with 8MHz Crystal and 160MHz target. More...
 
#define IFXSCU_CFG_PLL_STEPS_8MHZ_200MHZ
 Macro for Pll step for profile with 8MHz Crystal and 200MHz target. More...
 
#define IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_80MHZ
 Macros to configure Initial Pll step. Macros to configure the Pll initial step, where the configuration of PDIV, NDIV and K2DIV are done for the internal Oscillator frequency. IfxScuCcu_InitialStepConfig. More...
 
#define IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_133MHZ
 Macro for Initial Pll step, for profile with 16MHz Crystal and 133MHz target. More...
 
#define IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_160MHZ
 Macro for Initial Pll step, for profile with 16MHz Crystal and 160MHz target. More...
 
#define IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_200MHZ
 Macro for Initial Pll step, for profile with 16MHz Crystal and 200MHz target. More...
 
#define IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_240MHZ
 Macro for Initial Pll step, for profile with 16MHz Crystal and 240MHz target. More...
 
#define IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_80MHZ
 Macro for Initial Pll step, for profile with 20MHz Crystal and 80MHz target. More...
 
#define IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_133MHZ
 Macro for Initial Pll step, for profile with 20MHz Crystal and 133MHz target. More...
 
#define IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_160MHZ
 Macro for Initial Pll step, for profile with 20MHz Crystal and 160MHz target. More...
 
#define IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_200MHZ
 Macro for Initial Pll step, for profile with 20MHz Crystal and 200MHz target. More...
 
#define IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_240MHZ
 Macro for Initial Pll step, for profile with 20MHz Crystal and 240MHz target. More...
 
#define IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_300MHZ
 Macro for Initial Pll step, for profile with 20MHz Crystal and 300MHz target. More...
 
#define IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_80MHZ
 Macro for Initial Pll step, for profile with 40MHz Crystal and 80MHz target. More...
 
#define IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_133MHZ
 Macro for Initial Pll step, for profile with 40MHz Crystal and 133MHz target. More...
 
#define IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_160MHZ
 Macro for Initial Pll step, for profile with 40MHz Crystal and 160MHz target. More...
 
#define IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_200MHZ
 Macro for Initial Pll step, for profile with 40MHz Crystal and 200MHz target. More...
 
#define IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_240MHZ
 Macro for Initial Pll step, for profile with 40MHz Crystal and 240MHz target. More...
 
#define IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_300MHZ
 Macro for Initial Pll step, for profile with 40MHz Crystal and 300MHz target. More...
 
#define IFXSCU_CFG_PLL_INITIAL_STEP_8MHZ_80MHZ
 Macro for Initial Pll step, for profile with 8MHz Crystal and 80MHz target. More...
 
#define IFXSCU_CFG_PLL_INITIAL_STEP_8MHZ_160MHZ
 Macro for Initial Pll step, for profile with 8MHz Crystal and 160MHz target. More...
 
#define IFXSCU_CFG_PLL_INITIAL_STEP_8MHZ_200MHZ
 Macro for Initial Pll step, for profile with 8MHz Crystal and 200MHz target. More...
 
#define IFXSCU_CFG_MAXDIV_80MHZ   (1)
 Macros to configure CCUCON registers. Macros to configure the Pll initial step, where the configuration of PDIV, NDIV and K2DIV are done for the internal Oscillator frequency. IfxScuCcu_InitialStepConfig. More...
 
#define IFXSCU_CFG_MAXDIV_133MHZ   (1)
 Macro to configure MAXDIV at 133MHz target frequency. More...
 
#define IFXSCU_CFG_MAXDIV_160MHZ   (1)
 Macro to configure MAXDIV at 160MHz target frequency. More...
 
#define IFXSCU_CFG_MAXDIV_200MHZ   (1)
 Macro to configure MAXDIV at 200MHz target frequency. More...
 
#define IFXSCU_CFG_MAXDIV_240MHZ   (1)
 Macro to configure MAXDIV at 240MHz target frequency. More...
 
#define IFXSCU_CFG_MAXDIV_300MHZ   (1)
 Macro to configure MAXDIV at 300MHz target frequency. More...
 
#define IFXSCU_CFG_SRIDIV_80MHZ   (IFXSCU_CFG_MAXDIV_80MHZ) /*Same as MAXDIV */
 Macro to configure SRIDIV at 80MHz target frequency. More...
 
#define IFXSCU_CFG_SRIDIV_133MHZ   (IFXSCU_CFG_MAXDIV_133MHZ) /*Same as MAXDIV */
 Macro to configure SRIDIV at 133MHz target frequency. More...
 
#define IFXSCU_CFG_SRIDIV_160MHZ   (IFXSCU_CFG_MAXDIV_160MHZ) /*Same as MAXDIV */
 Macro to configure SRIDIV at 160MHz target frequency. More...
 
#define IFXSCU_CFG_SRIDIV_200MHZ   (IFXSCU_CFG_MAXDIV_200MHZ) /*Same as MAXDIV */
 Macro to configure SRIDIV at 200MHz target frequency. More...
 
#define IFXSCU_CFG_SRIDIV_240MHZ   (IFXSCU_CFG_MAXDIV_240MHZ) /*Same as MAXDIV */
 Macro to configure SRIDIV at 240MHz target frequency. More...
 
#define IFXSCU_CFG_SRIDIV_300MHZ   (IFXSCU_CFG_MAXDIV_300MHZ) /*Same as MAXDIV */
 Macro to configure SRIDIV at 300MHz target frequency. More...
 
#define IFXSCU_CFG_BAUD1DIV_80MHZ   (IFXSCU_CFG_MAXDIV_80MHZ) /*Max: 100MHz */
 Macro to configure BAUD1DIV at 80MHz target frequency. More...
 
#define IFXSCU_CFG_BAUD1DIV_133MHZ   (IFXSCU_CFG_MAXDIV_133MHZ * 2) /*Max: 100MHz */
 Macro to configure BAUD1DIV at 133MHz target frequency. More...
 
#define IFXSCU_CFG_BAUD1DIV_160MHZ   (IFXSCU_CFG_MAXDIV_160MHZ * 2) /*Max: 100MHz */
 Macro to configure BAUD1DIV at 160MHz target frequency. More...
 
#define IFXSCU_CFG_BAUD1DIV_200MHZ   (IFXSCU_CFG_MAXDIV_200MHZ * 2) /*Max: 100MHz */
 Macro to configure BAUD1DIV at 200MHz target frequency. More...
 
#define IFXSCU_CFG_BAUD1DIV_240MHZ   (IFXSCU_CFG_MAXDIV_240MHZ * 3) /*Max: 100MHz */
 Macro to configure BAUD1DIV at 240MHz target frequency. More...
 
#define IFXSCU_CFG_BAUD1DIV_300MHZ   (IFXSCU_CFG_MAXDIV_300MHZ * 3) /*Max: 100MHz */
 Macro to configure BAUD1DIV at 300MHz target frequency. More...
 
#define IFXSCU_CFG_BAUD2DIV_80MHZ   (IFXSCU_CFG_MAXDIV_80MHZ) /*Same as MAXDIV */
 Macro to configure BAUD2DIV at 80MHz target frequency. More...
 
#define IFXSCU_CFG_BAUD2DIV_133MHZ   (IFXSCU_CFG_MAXDIV_133MHZ) /*Same as MAXDIV */
 Macro to configure BAUD2DIV at 133MHz target frequency. More...
 
#define IFXSCU_CFG_BAUD2DIV_160MHZ   (IFXSCU_CFG_MAXDIV_160MHZ) /*Same as MAXDIV */
 Macro to configure BAUD2DIV at 160MHz target frequency. More...
 
#define IFXSCU_CFG_BAUD2DIV_200MHZ   (IFXSCU_CFG_MAXDIV_200MHZ) /*Same as MAXDIV */
 Macro to configure BAUD2DIV at 200MHz target frequency. More...
 
#define IFXSCU_CFG_BAUD2DIV_240MHZ   (IFXSCU_CFG_MAXDIV_240MHZ) /*Same as MAXDIV */
 Macro to configure BAUD2DIV at 240MHz target frequency. More...
 
#define IFXSCU_CFG_BAUD2DIV_300MHZ   (IFXSCU_CFG_MAXDIV_300MHZ) /*Same as MAXDIV */
 Macro to configure BAUD2DIV at 300MHz target frequency. More...
 
#define IFXSCU_CFG_SPBDIV_80MHZ   (IFXSCU_CFG_MAXDIV_80MHZ) /*Max: 100MHz */
 Macro to configure SPBDIV at 80MHz target frequency. More...
 
#define IFXSCU_CFG_SPBDIV_133MHZ   (IFXSCU_CFG_MAXDIV_133MHZ * 2) /*Max: 100MHz */
 Macro to configure SPBDIV at 133MHz target frequency. More...
 
#define IFXSCU_CFG_SPBDIV_160MHZ   (IFXSCU_CFG_MAXDIV_160MHZ * 2) /*Max: 100MHz */
 Macro to configure SPBDIV at 160MHz target frequency. More...
 
#define IFXSCU_CFG_SPBDIV_200MHZ   (IFXSCU_CFG_MAXDIV_200MHZ * 2) /*Max: 100MHz */
 Macro to configure SPBDIV at 200MHz target frequency. More...
 
#define IFXSCU_CFG_SPBDIV_240MHZ   (IFXSCU_CFG_MAXDIV_240MHZ * 3) /*Max: 100MHz */
 Macro to configure SPBDIV at 240MHz target frequency. More...
 
#define IFXSCU_CFG_SPBDIV_300MHZ   (IFXSCU_CFG_MAXDIV_300MHZ * 3) /*Max: 100MHz */
 Macro to configure SPBDIV at 300MHz target frequency. More...
 
#define IFXSCU_CFG_FSI2DIV_80MHZ   (IFXSCU_CFG_MAXDIV_80MHZ) /*Same as MAXDIV */
 Macro to configure FSI2DIV at 80MHz target frequency. More...
 
#define IFXSCU_CFG_FSI2DIV_133MHZ   (IFXSCU_CFG_MAXDIV_133MHZ) /*Same as MAXDIV */
 Macro to configure FSI2DIV at 133MHz target frequency. More...
 
#define IFXSCU_CFG_FSI2DIV_160MHZ   (IFXSCU_CFG_MAXDIV_160MHZ) /*Same as MAXDIV */
 Macro to configure FSI2DIV at 160MHz target frequency. More...
 
#define IFXSCU_CFG_FSI2DIV_200MHZ   (IFXSCU_CFG_MAXDIV_200MHZ) /*Same as MAXDIV */
 Macro to configure FSI2DIV at 200MHz target frequency. More...
 
#define IFXSCU_CFG_FSI2DIV_240MHZ   (IFXSCU_CFG_MAXDIV_240MHZ) /*Same as MAXDIV */
 Macro to configure FSI2DIV at 240MHz target frequency. More...
 
#define IFXSCU_CFG_FSI2DIV_300MHZ   (IFXSCU_CFG_MAXDIV_300MHZ) /*Same as MAXDIV */
 Macro to configure FSI2DIV at 300MHz target frequency. More...
 
#define IFXSCU_CFG_FSIDIV_80MHZ   (IFXSCU_CFG_MAXDIV_80MHZ) /*Max: 100MHz */
 Macro to configure FSIDIV at 80MHz target frequency. More...
 
#define IFXSCU_CFG_FSIDIV_133MHZ   (IFXSCU_CFG_MAXDIV_133MHZ * 2) /*Max: 100MHz */
 Macro to configure FSIDIV at 133MHz target frequency. More...
 
#define IFXSCU_CFG_FSIDIV_160MHZ   (IFXSCU_CFG_MAXDIV_160MHZ * 2) /*Max: 100MHz */
 Macro to configure FSIDIV at 160MHz target frequency. More...
 
#define IFXSCU_CFG_FSIDIV_200MHZ   (IFXSCU_CFG_MAXDIV_200MHZ * 2) /*Max: 100MHz */
 Macro to configure FSIDIV at 200MHz target frequency. More...
 
#define IFXSCU_CFG_FSIDIV_240MHZ   (IFXSCU_CFG_MAXDIV_240MHZ * 2) /*Max: 100MHz */
 Macro to configure FSIDIV at 240MHz target frequency. More...
 
#define IFXSCU_CFG_FSIDIV_300MHZ   (IFXSCU_CFG_MAXDIV_300MHZ * 2) /*Max: 100MHz */
 Macro to configure FSIDIV at 300MHz target frequency. More...
 
#define IFXSCU_CFG_CANDIV_80MHZ   (IFXSCU_CFG_MAXDIV_80MHZ) /*Max: 100MHz */
 Macro to configure CANDIV at 80MHz target frequency. More...
 
#define IFXSCU_CFG_CANDIV_133MHZ   (IFXSCU_CFG_MAXDIV_133MHZ * 2) /*Max: 100MHz */
 Macro to configure CANDIV at 133MHz target frequency. More...
 
#define IFXSCU_CFG_CANDIV_160MHZ   (IFXSCU_CFG_MAXDIV_160MHZ * 2) /*Max: 100MHz */
 Macro to configure CANDIV at 160MHz target frequency. More...
 
#define IFXSCU_CFG_CANDIV_200MHZ   (IFXSCU_CFG_MAXDIV_200MHZ * 2) /*Max: 100MHz */
 Macro to configure CANDIV at 200MHz target frequency. More...
 
#define IFXSCU_CFG_CANDIV_240MHZ   (IFXSCU_CFG_MAXDIV_240MHZ * 3) /*Max: 100MHz */
 Macro to configure CANDIV at 240MHz target frequency. More...
 
#define IFXSCU_CFG_CANDIV_300MHZ   (IFXSCU_CFG_MAXDIV_300MHZ * 3) /*Max: 100MHz */
 Macro to configure CANDIV at 200MHz target frequency. More...
 
#define IFXSCU_CFG_ERAYDIV_80MHZ   (IFXSCU_CFG_MAXDIV_80MHZ) /*Max: 80MHz */
 Macro to configure ERAYDIV at 80MHz target frequency. More...
 
#define IFXSCU_CFG_ERAYDIV_133MHZ   (IFXSCU_CFG_MAXDIV_133MHZ * 2) /*Max: 80MHz */
 Macro to configure ERAYDIV at 133MHz target frequency. More...
 
#define IFXSCU_CFG_ERAYDIV_160MHZ   (IFXSCU_CFG_MAXDIV_160MHZ * 2) /*Max: 80MHz */
 Macro to configure ERAYDIV at 160MHz target frequency. More...
 
#define IFXSCU_CFG_ERAYDIV_200MHZ   (IFXSCU_CFG_MAXDIV_200MHZ * 3) /*Max: 80MHz */
 Macro to configure ERAYDIV at 200MHz target frequency. More...
 
#define IFXSCU_CFG_ERAYDIV_240MHZ   (IFXSCU_CFG_MAXDIV_240MHZ * 3) /*Max: 80MHz */
 Macro to configure ERAYDIV at 200MHz target frequency. More...
 
#define IFXSCU_CFG_ERAYDIV_300MHZ   (IFXSCU_CFG_MAXDIV_300MHZ * 4) /*Max: 80MHz */
 Macro to configure ERAYDIV at 300MHz target frequency. More...
 
#define IFXSCU_CFG_STMDIV_80MHZ   (IFXSCU_CFG_MAXDIV_80MHZ) /*Max: 100MHz */
 Macro to configure STMDIV at 80MHz target frequency. More...
 
#define IFXSCU_CFG_STMDIV_133MHZ   (IFXSCU_CFG_MAXDIV_133MHZ * 2) /*Max: 100MHz */
 Macro to configure STMDIV at 133MHz target frequency. More...
 
#define IFXSCU_CFG_STMDIV_160MHZ   (IFXSCU_CFG_MAXDIV_160MHZ * 2) /*Max: 100MHz */
 Macro to configure STMDIV at 160MHz target frequency. More...
 
#define IFXSCU_CFG_STMDIV_200MHZ   (IFXSCU_CFG_MAXDIV_200MHZ * 2) /*Max: 100MHz */
 Macro to configure STMDIV at 200MHz target frequency. More...
 
#define IFXSCU_CFG_STMDIV_240MHZ   (IFXSCU_CFG_MAXDIV_240MHZ * 3) /*Max: 100MHz */
 Macro to configure STMDIV at 240MHz target frequency. More...
 
#define IFXSCU_CFG_STMDIV_300MHZ   (IFXSCU_CFG_MAXDIV_300MHZ * 3) /*Max: 100MHz */
 Macro to configure STMDIV at 300MHz target frequency. More...
 
#define IFXSCU_CFG_GTMDIV_80MHZ   (IFXSCU_CFG_MAXDIV_80MHZ) /*Max: 100MHz */
 Macro to configure GTMDIV at 80MHz target frequency. More...
 
#define IFXSCU_CFG_GTMDIV_133MHZ   (IFXSCU_CFG_MAXDIV_133MHZ * 2) /*Max: 100MHz */
 Macro to configure GTMDIV at 133MHz target frequency. More...
 
#define IFXSCU_CFG_GTMDIV_160MHZ   (IFXSCU_CFG_MAXDIV_160MHZ * 2) /*Max: 100MHz */
 Macro to configure GTMDIV at 160MHz target frequency. More...
 
#define IFXSCU_CFG_GTMDIV_200MHZ   (IFXSCU_CFG_MAXDIV_200MHZ * 2) /*Max: 100MHz */
 Macro to configure GTMDIV at 200MHz target frequency. More...
 
#define IFXSCU_CFG_GTMDIV_240MHZ   (IFXSCU_CFG_MAXDIV_240MHZ * 3) /*Max: 100MHz */
 Macro to configure GTMDIV at 240MHz target frequency. More...
 
#define IFXSCU_CFG_GTMDIV_300MHZ   (IFXSCU_CFG_MAXDIV_300MHZ * 3) /*Max: 100MHz */
 Macro to configure GTMDIV at 300MHz target frequency. More...
 
#define IFXSCU_CFG_ETHDIV_80MHZ   (IFXSCU_CFG_MAXDIV_80MHZ * 2)
 Macro to configure ETHDIV at 80MHz target frequency. More...
 
#define IFXSCU_CFG_ETHDIV_133MHZ   (IFXSCU_CFG_MAXDIV_133MHZ * 3)
 Macro to configure ETHDIV at 133MHz target frequency. More...
 
#define IFXSCU_CFG_ETHDIV_160MHZ   (IFXSCU_CFG_MAXDIV_160MHZ * 4)
 Macro to configure ETHDIV at 160MHz target frequency. More...
 
#define IFXSCU_CFG_ETHDIV_200MHZ   (IFXSCU_CFG_MAXDIV_200MHZ * 4)
 Macro to configure ETHDIV at 200MHz target frequency. More...
 
#define IFXSCU_CFG_ETHDIV_240MHZ   (IFXSCU_CFG_MAXDIV_240MHZ * 5)
 Macro to configure ETHDIV at 240MHz target frequency. More...
 
#define IFXSCU_CFG_ETHDIV_300MHZ   (IFXSCU_CFG_MAXDIV_300MHZ * 6)
 Macro to configure ETHDIV at 300MHz target frequency. More...
 
#define IFXSCU_CFG_ASCLINFDIV_80MHZ   (IFXSCU_CFG_MAXDIV_80MHZ) /*Same as MAXDIV */
 Macro to configure ASCLINFDIV at 80MHz target frequency. More...
 
#define IFXSCU_CFG_ASCLINFDIV_133MHZ   (IFXSCU_CFG_MAXDIV_133MHZ) /*Same as MAXDIV */
 Macro to configure ASCLINFDIV at 133MHz target frequency. More...
 
#define IFXSCU_CFG_ASCLINFDIV_160MHZ   (IFXSCU_CFG_MAXDIV_160MHZ) /*Same as MAXDIV */
 Macro to configure ASCLINFDIV at 160MHz target frequency. More...
 
#define IFXSCU_CFG_ASCLINFDIV_200MHZ   (IFXSCU_CFG_MAXDIV_200MHZ) /*Same as MAXDIV */
 Macro to configure ASCLINFDIV at 200MHz target frequency. More...
 
#define IFXSCU_CFG_ASCLINFDIV_240MHZ   (IFXSCU_CFG_MAXDIV_240MHZ) /*Same as MAXDIV */
 Macro to configure ASCLINFDIV at 240MHz target frequency. More...
 
#define IFXSCU_CFG_ASCLINFDIV_300MHZ   (IFXSCU_CFG_MAXDIV_300MHZ) /*Same as MAXDIV */
 Macro to configure ASCLINFDIV at 300MHz target frequency. More...
 
#define IFXSCU_CFG_ASCLINSDIV_80MHZ   (IFXSCU_CFG_MAXDIV_80MHZ) /*Max: 100MHz */
 Macro to configure ASCLINSDIV at 80MHz target frequency. More...
 
#define IFXSCU_CFG_ASCLINSDIV_133MHZ   (IFXSCU_CFG_MAXDIV_133MHZ * 2) /*Max: 100MHz */
 Macro to configure ASCLINSDIV at 133MHz target frequency. More...
 
#define IFXSCU_CFG_ASCLINSDIV_160MHZ   (IFXSCU_CFG_MAXDIV_160MHZ * 2) /*Max: 100MHz */
 Macro to configure ASCLINSDIV at 160MHz target frequency. More...
 
#define IFXSCU_CFG_ASCLINSDIV_200MHZ   (IFXSCU_CFG_MAXDIV_200MHZ * 2) /*Max: 100MHz */
 Macro to configure ASCLINSDIV at 200MHz target frequency. More...
 
#define IFXSCU_CFG_ASCLINSDIV_240MHZ   (IFXSCU_CFG_MAXDIV_240MHZ * 3) /*Max: 100MHz */
 Macro to configure ASCLINSDIV at 240MHz target frequency. More...
 
#define IFXSCU_CFG_ASCLINSDIV_300MHZ   (IFXSCU_CFG_MAXDIV_300MHZ * 3) /*Max: 100MHz */
 Macro to configure ASCLINSDIV at 300MHz target frequency. More...
 
#define IFXSCU_CFG_BBBDIV_80MHZ   (IFXSCU_CFG_SRIDIV_80MHZ * 2)
 Macro to configure BBBDIV at 80MHz target frequency. More...
 
#define IFXSCU_CFG_BBBDIV_133MHZ   (IFXSCU_CFG_SRIDIV_133MHZ * 2)
 Macro to configure BBBDIV at 133MHz target frequency. More...
 
#define IFXSCU_CFG_BBBDIV_160MHZ   (IFXSCU_CFG_SRIDIV_160MHZ * 2)
 Macro to configure BBBDIV at 160MHz target frequency. More...
 
#define IFXSCU_CFG_BBBDIV_200MHZ   (IFXSCU_CFG_SRIDIV_200MHZ * 2)
 Macro to configure BBBDIV at 200MHz target frequency. More...
 
#define IFXSCU_CFG_BBBDIV_240MHZ   (IFXSCU_CFG_SRIDIV_240MHZ * 2)
 Macro to configure BBBDIV at 240MHz target frequency. More...
 
#define IFXSCU_CFG_BBBDIV_300MHZ   (IFXSCU_CFG_SRIDIV_300MHZ * 2)
 Macro to configure BBBDIV at 300MHz target frequency. More...
 
#define IFXSCU_CFG_CPU0DIV_80MHZ   (0) /*Same as SRIDIV */
 Macro to configure CPU0DIV at 80MHz target frequency. More...
 
#define IFXSCU_CFG_CPU0DIV_133MHZ   (0) /*Same as SRIDIV */
 Macro to configure CPU0DIV at 133MHz target frequency. More...
 
#define IFXSCU_CFG_CPU0DIV_160MHZ   (0) /*Same as SRIDIV */
 Macro to configure CPU0DIV at 160MHz target frequency. More...
 
#define IFXSCU_CFG_CPU0DIV_200MHZ   (0) /*Same as SRIDIV */
 Macro to configure CPU0DIV at 200MHz target frequency. More...
 
#define IFXSCU_CFG_CPU0DIV_240MHZ   (0) /*Same as SRIDIV */
 Macro to configure CPU0DIV at 240MHz target frequency. More...
 
#define IFXSCU_CFG_CPU0DIV_300MHZ   (0) /*Same as SRIDIV */
 Macro to configure CPU0DIV at 300MHz target frequency. More...
 
#define IFXSCU_CFG_CPU1DIV_80MHZ   (0) /*Same as SRIDIV */
 Macro to configure CPU1DIV at 80MHz target frequency. More...
 
#define IFXSCU_CFG_CPU1DIV_133MHZ   (0) /*Same as SRIDIV */
 Macro to configure CPU1DIV at 133MHz target frequency. More...
 
#define IFXSCU_CFG_CPU1DIV_160MHZ   (0) /*Same as SRIDIV */
 Macro to configure CPU1DIV at 160MHz target frequency. More...
 
#define IFXSCU_CFG_CPU1DIV_200MHZ   (0) /*Same as SRIDIV */
 Macro to configure CPU1DIV at 200MHz target frequency. More...
 
#define IFXSCU_CFG_CPU1DIV_240MHZ   (0) /*Same as SRIDIV */
 Macro to configure CPU1DIV at 240MHz target frequency. More...
 
#define IFXSCU_CFG_CPU1DIV_300MHZ   (0) /*Same as SRIDIV */
 Macro to configure CPU1DIV at 300MHz target frequency. More...
 
#define IFXSCU_CFG_CPU2DIV_80MHZ   (0) /*Same as SRIDIV */
 Macro to configure CPU2DIV at 80MHz target frequency. More...
 
#define IFXSCU_CFG_CPU2DIV_133MHZ   (0) /*Same as SRIDIV */
 Macro to configure CPU2DIV at 133MHz target frequency. More...
 
#define IFXSCU_CFG_CPU2DIV_160MHZ   (0) /*Same as SRIDIV */
 Macro to configure CPU2DIV at 160MHz target frequency. More...
 
#define IFXSCU_CFG_CPU2DIV_200MHZ   (0) /*Same as SRIDIV */
 Macro to configure CPU2DIV at 200MHz target frequency. More...
 
#define IFXSCU_CFG_CPU2DIV_240MHZ   (0) /*Same as SRIDIV */
 Macro to configure CPU2DIV at 240MHz target frequency. More...
 
#define IFXSCU_CFG_CPU2DIV_300MHZ   (0) /*Same as SRIDIV */
 Macro to configure CPU2DIV at 300MHz target frequency. More...
 
#define IFXSCU_CFG_FLASH_FCON_WSPFLASH_80MHZ   (3-1)
 Macros to configure FLASH.FCON register for flash waitstate configuration. IfxScuCcu_InitialStepConfig. More...
 
#define IFXSCU_CFG_FLASH_FCON_WSPFLASH_133MHZ   (4-1)
 Macro to configure FCON.WSPFLASH at 133MHz target frequency. More...
 
#define IFXSCU_CFG_FLASH_FCON_WSPFLASH_160MHZ   (5-1)
 Macro to configure FCON.WSPFLASH at 160MHz target frequency. More...
 
#define IFXSCU_CFG_FLASH_FCON_WSPFLASH_200MHZ   (6-1)
 Macro to configure FCON.WSPFLASH at 200MHz target frequency. More...
 
#define IFXSCU_CFG_FLASH_FCON_WSPFLASH_240MHZ   (8-1)
 Macro to configure FCON.WSPFLASH at 240MHz target frequency. More...
 
#define IFXSCU_CFG_FLASH_FCON_WSPFLASH_300MHZ   (9-1)
 Macro to configure FCON.WSPFLASH at 300MHz target frequency. More...
 
#define IFXSCU_CFG_FLASH_FCON_WSECPF_80MHZ   (1-1)
 Macro to configure FCON.WSECP_ at 80MHz target frequency. More...
 
#define IFXSCU_CFG_FLASH_FCON_WSECPF_133MHZ   (2-1)
 Macro to configure FCON.WSECPF at 133MHz target frequency. More...
 
#define IFXSCU_CFG_FLASH_FCON_WSECPF_160MHZ   (2-1)
 Macro to configure FCON.WSECPF at 160MHz target frequency. More...
 
#define IFXSCU_CFG_FLASH_FCON_WSECPF_200MHZ   (2-1)
 Macro to configure FCON.WSECPF at 200MHz target frequency. More...
 
#define IFXSCU_CFG_FLASH_FCON_WSECPF_240MHZ   (3-1)
 Macro to configure FCON.WSECPF_ at 240MHz target frequency. More...
 
#define IFXSCU_CFG_FLASH_FCON_WSECPF_300MHZ   (3-1)
 Macro to configure FCON.WSECPF at 300MHz target frequency. More...
 
#define IFXSCU_CFG_FLASH_FCON_WSDFLASH_80MHZ   (16-1)
 Macro to configure FCON.WSDFLASH at 80MHz target frequency. More...
 
#define IFXSCU_CFG_FLASH_FCON_WSDFLASH_133MHZ   (14-1)
 Macro to configure FCON.WSDFLASH_ at 133MHz target frequency, where fSRI= 133/2= 66.5MHZ. More...
 
#define IFXSCU_CFG_FLASH_FCON_WSDFLASH_160MHZ   (16-1)
 Macro to configure FCON.WSDFLASH at 160MHz target frequency, where fSRI= 160/2= 80MHZ. More...
 
#define IFXSCU_CFG_FLASH_FCON_WSDFLASH_200MHZ   (20-1)
 Macro to configure FCON.WSDFLASH at 200MHz target frequency, where fSRI= 200/2= 100MHZ. More...
 
#define IFXSCU_CFG_FLASH_FCON_WSDFLASH_240MHZ   (16-1)
 Macro to configure FCON.WSDFLASH at 240MHz target frequency, where fSRI= 240/3= 80MHZ. More...
 
#define IFXSCU_CFG_FLASH_FCON_WSDFLASH_300MHZ   (20-1)
 Macro to configure FCON.WSDFLASH at 300MHz target frequency, where fSRI= 300/3= 100MHZ. More...
 
#define IFXSCU_CFG_FLASH_FCON_WSECDF_80MHZ   (2-1)
 Macro to configure FCON.WSECDF at 80MHz target frequency. More...
 
#define IFXSCU_CFG_FLASH_FCON_WSECDF_133MHZ   (2-1)
 Macro to configure FCON.WSECDF at 133MHz target frequency, where fSRI= 133/2= 66.5MHZ. More...
 
#define IFXSCU_CFG_FLASH_FCON_WSECDF_160MHZ   (2-1)
 Macro to configure FCON.WSECDF at 160MHz target frequency, where fSRI= 160/2= 80MHZ. More...
 
#define IFXSCU_CFG_FLASH_FCON_WSECDF_200MHZ   (2-1)
 Macro to configure FCON.WSECDF at 200MHz target frequency, where fSRI= 200/2= 100MHZ. More...
 
#define IFXSCU_CFG_FLASH_FCON_WSECDF_240MHZ   (2-1)
 Macro to configure FCON.WSECDF at 240MHz target frequency, where fSRI= 240/3= 80MHZ. More...
 
#define IFXSCU_CFG_FLASH_FCON_WSECDF_300MHZ   (2-1)
 Macro to configure FCON.WSECDF at 300MHz target frequency, where fSRI= 300/3= 100MHZ. More...
 
#define IFXSCU_CFG_FLASH_WAITSTATE_MSK
 Macros to configure FLASH.FCON registers. More...
 
#define IFXSCU_CFG_FLASH_WAITSTATE_VAL_BASIC_(pllFreq)
 
#define IFXSCU_CFG_FLASH_WAITSTATE_VAL_BASIC(pllFreq)   IFXSCU_CFG_FLASH_WAITSTATE_VAL_BASIC_(pllFreq)
 
#define IFXSCU_CFG_FLASH_WAITSTATE_VAL   IFXSCU_CFG_FLASH_WAITSTATE_VAL_BASIC(IFXSCU_CFG_PLL_FREQ)
 
#define IFXSCU_CFG_CCUCON0_MASK
 Macros to configure CCUCON0 Clock distribution. More...
 
#define IFXSCU_CFG_CCUCON0_BASIC_(pllFreq)
 
#define IFXSCU_CFG_CCUCON0_BASIC(pllFreq)   IFXSCU_CFG_CCUCON0_BASIC_(pllFreq)
 
#define IFXSCU_CFG_CCUCON0   IFXSCU_CFG_CCUCON0_BASIC(IFXSCU_CFG_PLL_FREQ)
 
#define IFXSCU_CFG_CCUCON1_MASK
 Macros to configure CCUCON1 Clock distribution. More...
 
#define IFXSCU_CFG_CCUCON1_BASIC_(pllFreq)
 
#define IFXSCU_CFG_CCUCON1_BASIC(pllFreq)   IFXSCU_CFG_CCUCON1_BASIC_(pllFreq)
 
#define IFXSCU_CFG_CCUCON1   IFXSCU_CFG_CCUCON1_BASIC(IFXSCU_CFG_PLL_FREQ)
 
#define IFXSCU_CFG_CCUCON2_MASK
 Macros to configure CCUCON2 Clock distribution. More...
 
#define IFXSCU_CFG_CCUCON2_BASIC_(pllFreq)
 
#define IFXSCU_CFG_CCUCON2_BASIC(pllFreq)   IFXSCU_CFG_CCUCON2_BASIC_(pllFreq)
 
#define IFXSCU_CFG_CCUCON2   IFXSCU_CFG_CCUCON2_BASIC(IFXSCU_CFG_PLL_FREQ)
 
#define IFXSCU_CFG_CCUCON5_MASK
 Macros to configure CCUCON5 Clock distribution. More...
 
#define IFXSCU_CFG_CCUCON5_BASIC_(pllFreq)
 
#define IFXSCU_CFG_CCUCON5_BASIC(pllFreq)   IFXSCU_CFG_CCUCON5_BASIC_(pllFreq)
 
#define IFXSCU_CFG_CCUCON5   IFXSCU_CFG_CCUCON5_BASIC(IFXSCU_CFG_PLL_FREQ)
 
#define IFXSCU_CFG_CCUCON6_MASK
 Macros to configure CCUCON6 Clock distribution. More...
 
#define IFXSCU_CFG_CCUCON6_BASIC_(pllFreq)
 
#define IFXSCU_CFG_CCUCON6_BASIC(pllFreq)   IFXSCU_CFG_CCUCON6_BASIC_(pllFreq)
 
#define IFXSCU_CFG_CCUCON6   IFXSCU_CFG_CCUCON6_BASIC(IFXSCU_CFG_PLL_FREQ)
 
#define IFXSCU_CFG_CCUCON7_MASK
 Macros to configure CCUCON7 Clock distribution. More...
 
#define IFXSCU_CFG_CCUCON7_BASIC_(pllFreq)
 
#define IFXSCU_CFG_CCUCON7_BASIC(pllFreq)   IFXSCU_CFG_CCUCON7_BASIC_(pllFreq)
 
#define IFXSCU_CFG_CCUCON7   IFXSCU_CFG_CCUCON7_BASIC(IFXSCU_CFG_PLL_FREQ)
 
#define IFXSCU_CFG_CCUCON8_MASK
 Macros to configure CCUCON8 Clock distribution. More...
 
#define IFXSCU_CFG_CCUCON8_BASIC_(pllFreq)
 
#define IFXSCU_CFG_CCUCON8_BASIC(pllFreq)   IFXSCU_CFG_CCUCON8_BASIC_(pllFreq)
 
#define IFXSCU_CFG_CCUCON8   IFXSCU_CFG_CCUCON8_BASIC(IFXSCU_CFG_PLL_FREQ)
 
#define IFXSCU_CFG_CLK_DISTRIBUTION
 
#define IFXSCU_CFG_PLL_STEPS_BASIC_(xtalFreq, pllFreq)   IFXSCU_CFG_PLL_STEPS_##xtalFreq##_##pllFreq
 
#define IFXSCU_CFG_PLL_STEPS_BASIC(xtalFreq, pllFreq)   IFXSCU_CFG_PLL_STEPS_BASIC_(xtalFreq, pllFreq)
 
#define IFXSCU_CFG_PLL_STEPS   IFXSCU_CFG_PLL_STEPS_BASIC(IFXSCU_CFG_XTAL_FREQ, IFXSCU_CFG_PLL_FREQ)
 
#define IFXSCU_CFG_PLL_INITIAL_STEP_BASIC_(xtalFreq, pllFreq)   IFXSCU_CFG_PLL_INITIAL_STEP_##xtalFreq##_##pllFreq
 
#define IFXSCU_CFG_PLL_INITIAL_STEP_BASIC(xtalFreq, pllFreq)   IFXSCU_CFG_PLL_INITIAL_STEP_BASIC_(xtalFreq, pllFreq)
 
#define IFXSCU_CFG_PLL_INITIAL_STEP   IFXSCU_CFG_PLL_INITIAL_STEP_BASIC(IFXSCU_CFG_XTAL_FREQ, IFXSCU_CFG_PLL_FREQ)
 
#define IFXSCU_CFG_FLASH_WAITSTATE
 
#define IFXSCU_CFG_XTAL_FREQ   20MHZ
 
#define IFXSCU_CFG_PLL_FREQ   200MHZ
 

Enumerations

enum  IfxScu_CCUCON0_CLKSEL {
  IfxScu_CCUCON0_CLKSEL_fBack = 0,
  IfxScu_CCUCON0_CLKSEL_fPll = 1
}
 
enum  IfxScu_CCUCON1_INSEL {
  IfxScu_CCUCON1_INSEL_fOsc1 = 0,
  IfxScu_CCUCON1_INSEL_fOsc0 = 1
}
 
enum  IfxScu_WDTCON1_IR {
  IfxScu_WDTCON1_IR_divBy16384 = 0,
  IfxScu_WDTCON1_IR_divBy256 = 1,
  IfxScu_WDTCON1_IR_divBy64 = 2
}
 
enum  IfxScu_PMCSR_REQSLP {
  IfxScu_PMCSR_REQSLP_Run = 0U,
  IfxScu_PMCSR_REQSLP_Idle = 1U,
  IfxScu_PMCSR_REQSLP_Sleep = 2U,
  IfxScu_PMCSR_REQSLP_Stby = 3U
}
 

Detailed Description

SCU on-chip implementation data.

Version
iLLD_0_1_0_10
                            IMPORTANT NOTICE

Infineon Technologies AG (Infineon) is supplying this file for use exclusively with Infineon's microcontroller products. This file can be freely distributed within development tools that are supporting such microcontroller products.

THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

Definition in file IfxScu_cfg.h.

Macro Definition Documentation

#define IFX_CFG_SCU_PLL_FREQUENCY   200000000

Default PLL frequency.

Definition at line 43 of file IfxScu_cfg.h.

#define IFX_CFG_SCU_XTAL_FREQUENCY   20000000

Default External oscillator frequency.

Definition at line 37 of file IfxScu_cfg.h.

Referenced by IfxScuCcu_getOsc0Frequency(), and IfxScuCcu_getOscFrequency().

#define IFXSCU_CFG_ASCLINFDIV_133MHZ   (IFXSCU_CFG_MAXDIV_133MHZ) /*Same as MAXDIV */

Macro to configure ASCLINFDIV at 133MHz target frequency.

Definition at line 921 of file IfxScu_cfg.h.

#define IFXSCU_CFG_ASCLINFDIV_160MHZ   (IFXSCU_CFG_MAXDIV_160MHZ) /*Same as MAXDIV */

Macro to configure ASCLINFDIV at 160MHz target frequency.

Definition at line 926 of file IfxScu_cfg.h.

#define IFXSCU_CFG_ASCLINFDIV_200MHZ   (IFXSCU_CFG_MAXDIV_200MHZ) /*Same as MAXDIV */

Macro to configure ASCLINFDIV at 200MHz target frequency.

Definition at line 931 of file IfxScu_cfg.h.

#define IFXSCU_CFG_ASCLINFDIV_240MHZ   (IFXSCU_CFG_MAXDIV_240MHZ) /*Same as MAXDIV */

Macro to configure ASCLINFDIV at 240MHz target frequency.

Definition at line 936 of file IfxScu_cfg.h.

#define IFXSCU_CFG_ASCLINFDIV_300MHZ   (IFXSCU_CFG_MAXDIV_300MHZ) /*Same as MAXDIV */

Macro to configure ASCLINFDIV at 300MHz target frequency.

Definition at line 941 of file IfxScu_cfg.h.

#define IFXSCU_CFG_ASCLINFDIV_80MHZ   (IFXSCU_CFG_MAXDIV_80MHZ) /*Same as MAXDIV */

Macro to configure ASCLINFDIV at 80MHz target frequency.

Definition at line 916 of file IfxScu_cfg.h.

#define IFXSCU_CFG_ASCLINSDIV_133MHZ   (IFXSCU_CFG_MAXDIV_133MHZ * 2) /*Max: 100MHz */

Macro to configure ASCLINSDIV at 133MHz target frequency.

Definition at line 951 of file IfxScu_cfg.h.

#define IFXSCU_CFG_ASCLINSDIV_160MHZ   (IFXSCU_CFG_MAXDIV_160MHZ * 2) /*Max: 100MHz */

Macro to configure ASCLINSDIV at 160MHz target frequency.

Definition at line 956 of file IfxScu_cfg.h.

#define IFXSCU_CFG_ASCLINSDIV_200MHZ   (IFXSCU_CFG_MAXDIV_200MHZ * 2) /*Max: 100MHz */

Macro to configure ASCLINSDIV at 200MHz target frequency.

Definition at line 961 of file IfxScu_cfg.h.

#define IFXSCU_CFG_ASCLINSDIV_240MHZ   (IFXSCU_CFG_MAXDIV_240MHZ * 3) /*Max: 100MHz */

Macro to configure ASCLINSDIV at 240MHz target frequency.

Definition at line 966 of file IfxScu_cfg.h.

#define IFXSCU_CFG_ASCLINSDIV_300MHZ   (IFXSCU_CFG_MAXDIV_300MHZ * 3) /*Max: 100MHz */

Macro to configure ASCLINSDIV at 300MHz target frequency.

Definition at line 971 of file IfxScu_cfg.h.

#define IFXSCU_CFG_ASCLINSDIV_80MHZ   (IFXSCU_CFG_MAXDIV_80MHZ) /*Max: 100MHz */

Macro to configure ASCLINSDIV at 80MHz target frequency.

Definition at line 946 of file IfxScu_cfg.h.

#define IFXSCU_CFG_BAUD1DIV_133MHZ   (IFXSCU_CFG_MAXDIV_133MHZ * 2) /*Max: 100MHz */

Macro to configure BAUD1DIV at 133MHz target frequency.

Definition at line 621 of file IfxScu_cfg.h.

#define IFXSCU_CFG_BAUD1DIV_160MHZ   (IFXSCU_CFG_MAXDIV_160MHZ * 2) /*Max: 100MHz */

Macro to configure BAUD1DIV at 160MHz target frequency.

Definition at line 626 of file IfxScu_cfg.h.

#define IFXSCU_CFG_BAUD1DIV_200MHZ   (IFXSCU_CFG_MAXDIV_200MHZ * 2) /*Max: 100MHz */

Macro to configure BAUD1DIV at 200MHz target frequency.

Definition at line 631 of file IfxScu_cfg.h.

#define IFXSCU_CFG_BAUD1DIV_240MHZ   (IFXSCU_CFG_MAXDIV_240MHZ * 3) /*Max: 100MHz */

Macro to configure BAUD1DIV at 240MHz target frequency.

Definition at line 636 of file IfxScu_cfg.h.

#define IFXSCU_CFG_BAUD1DIV_300MHZ   (IFXSCU_CFG_MAXDIV_300MHZ * 3) /*Max: 100MHz */

Macro to configure BAUD1DIV at 300MHz target frequency.

Definition at line 641 of file IfxScu_cfg.h.

#define IFXSCU_CFG_BAUD1DIV_80MHZ   (IFXSCU_CFG_MAXDIV_80MHZ) /*Max: 100MHz */

Macro to configure BAUD1DIV at 80MHz target frequency.

Definition at line 616 of file IfxScu_cfg.h.

#define IFXSCU_CFG_BAUD2DIV_133MHZ   (IFXSCU_CFG_MAXDIV_133MHZ) /*Same as MAXDIV */

Macro to configure BAUD2DIV at 133MHz target frequency.

Definition at line 651 of file IfxScu_cfg.h.

#define IFXSCU_CFG_BAUD2DIV_160MHZ   (IFXSCU_CFG_MAXDIV_160MHZ) /*Same as MAXDIV */

Macro to configure BAUD2DIV at 160MHz target frequency.

Definition at line 656 of file IfxScu_cfg.h.

#define IFXSCU_CFG_BAUD2DIV_200MHZ   (IFXSCU_CFG_MAXDIV_200MHZ) /*Same as MAXDIV */

Macro to configure BAUD2DIV at 200MHz target frequency.

Definition at line 661 of file IfxScu_cfg.h.

#define IFXSCU_CFG_BAUD2DIV_240MHZ   (IFXSCU_CFG_MAXDIV_240MHZ) /*Same as MAXDIV */

Macro to configure BAUD2DIV at 240MHz target frequency.

Definition at line 666 of file IfxScu_cfg.h.

#define IFXSCU_CFG_BAUD2DIV_300MHZ   (IFXSCU_CFG_MAXDIV_300MHZ) /*Same as MAXDIV */

Macro to configure BAUD2DIV at 300MHz target frequency.

Definition at line 671 of file IfxScu_cfg.h.

#define IFXSCU_CFG_BAUD2DIV_80MHZ   (IFXSCU_CFG_MAXDIV_80MHZ) /*Same as MAXDIV */

Macro to configure BAUD2DIV at 80MHz target frequency.

Definition at line 646 of file IfxScu_cfg.h.

#define IFXSCU_CFG_BBBDIV_133MHZ   (IFXSCU_CFG_SRIDIV_133MHZ * 2)

Macro to configure BBBDIV at 133MHz target frequency.

Definition at line 981 of file IfxScu_cfg.h.

#define IFXSCU_CFG_BBBDIV_160MHZ   (IFXSCU_CFG_SRIDIV_160MHZ * 2)

Macro to configure BBBDIV at 160MHz target frequency.

Definition at line 986 of file IfxScu_cfg.h.

#define IFXSCU_CFG_BBBDIV_200MHZ   (IFXSCU_CFG_SRIDIV_200MHZ * 2)

Macro to configure BBBDIV at 200MHz target frequency.

Definition at line 991 of file IfxScu_cfg.h.

#define IFXSCU_CFG_BBBDIV_240MHZ   (IFXSCU_CFG_SRIDIV_240MHZ * 2)

Macro to configure BBBDIV at 240MHz target frequency.

Definition at line 996 of file IfxScu_cfg.h.

#define IFXSCU_CFG_BBBDIV_300MHZ   (IFXSCU_CFG_SRIDIV_300MHZ * 2)

Macro to configure BBBDIV at 300MHz target frequency.

Definition at line 1001 of file IfxScu_cfg.h.

#define IFXSCU_CFG_BBBDIV_80MHZ   (IFXSCU_CFG_SRIDIV_80MHZ * 2)

Macro to configure BBBDIV at 80MHz target frequency.

Definition at line 976 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CANDIV_133MHZ   (IFXSCU_CFG_MAXDIV_133MHZ * 2) /*Max: 100MHz */

Macro to configure CANDIV at 133MHz target frequency.

Definition at line 771 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CANDIV_160MHZ   (IFXSCU_CFG_MAXDIV_160MHZ * 2) /*Max: 100MHz */

Macro to configure CANDIV at 160MHz target frequency.

Definition at line 776 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CANDIV_200MHZ   (IFXSCU_CFG_MAXDIV_200MHZ * 2) /*Max: 100MHz */

Macro to configure CANDIV at 200MHz target frequency.

Definition at line 781 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CANDIV_240MHZ   (IFXSCU_CFG_MAXDIV_240MHZ * 3) /*Max: 100MHz */

Macro to configure CANDIV at 240MHz target frequency.

Definition at line 786 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CANDIV_300MHZ   (IFXSCU_CFG_MAXDIV_300MHZ * 3) /*Max: 100MHz */

Macro to configure CANDIV at 200MHz target frequency.

Definition at line 791 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CANDIV_80MHZ   (IFXSCU_CFG_MAXDIV_80MHZ) /*Max: 100MHz */

Macro to configure CANDIV at 80MHz target frequency.

Definition at line 766 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CCUCON0   IFXSCU_CFG_CCUCON0_BASIC(IFXSCU_CFG_PLL_FREQ)

Definition at line 1264 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CCUCON0_BASIC (   pllFreq)    IFXSCU_CFG_CCUCON0_BASIC_(pllFreq)

Definition at line 1262 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CCUCON0_BASIC_ (   pllFreq)
Value:
(uint32)( \
(IFXSCU_CFG_BAUD1DIV_##pllFreq << IFX_SCU_CCUCON0_BAUD1DIV_OFF) | \
(IFXSCU_CFG_BAUD2DIV_##pllFreq << IFX_SCU_CCUCON0_BAUD2DIV_OFF) | \
(IFXSCU_CFG_SRIDIV_##pllFreq << IFX_SCU_CCUCON0_SRIDIV_OFF) | \
(IFXSCU_CFG_SPBDIV_##pllFreq << IFX_SCU_CCUCON0_SPBDIV_OFF) | \
(IFXSCU_CFG_FSI2DIV_##pllFreq << IFX_SCU_CCUCON0_FSI2DIV_OFF) | \
(IFXSCU_CFG_FSIDIV_##pllFreq << IFX_SCU_CCUCON0_FSIDIV_OFF))

Definition at line 1253 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CCUCON0_MASK
Value:
( \
(IFX_SCU_CCUCON0_BAUD1DIV_MSK << IFX_SCU_CCUCON0_BAUD1DIV_OFF) | \
(IFX_SCU_CCUCON0_BAUD2DIV_MSK << IFX_SCU_CCUCON0_BAUD2DIV_OFF) | \
(IFX_SCU_CCUCON0_SRIDIV_MSK << IFX_SCU_CCUCON0_SRIDIV_OFF) | \
(IFX_SCU_CCUCON0_SPBDIV_MSK << IFX_SCU_CCUCON0_SPBDIV_OFF) | \
(IFX_SCU_CCUCON0_FSI2DIV_MSK << IFX_SCU_CCUCON0_FSI2DIV_OFF) | \
(IFX_SCU_CCUCON0_FSIDIV_MSK << IFX_SCU_CCUCON0_FSIDIV_OFF))

Macros to configure CCUCON0 Clock distribution.

Definition at line 1244 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CCUCON1   IFXSCU_CFG_CCUCON1_BASIC(IFXSCU_CFG_PLL_FREQ)

Definition at line 1289 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CCUCON1_BASIC (   pllFreq)    IFXSCU_CFG_CCUCON1_BASIC_(pllFreq)

Definition at line 1287 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CCUCON1_BASIC_ (   pllFreq)
Value:
(uint32)( \
(IFXSCU_CFG_CANDIV_##pllFreq << IFX_SCU_CCUCON1_CANDIV_OFF) | \
(IFXSCU_CFG_ERAYDIV_##pllFreq << IFX_SCU_CCUCON1_ERAYDIV_OFF) | \
(IFXSCU_CFG_STMDIV_##pllFreq << IFX_SCU_CCUCON1_STMDIV_OFF) | \
(IFXSCU_CFG_GTMDIV_##pllFreq << IFX_SCU_CCUCON1_GTMDIV_OFF) | \
(IFXSCU_CFG_ETHDIV_##pllFreq << IFX_SCU_CCUCON1_ETHDIV_OFF) | \
(IFXSCU_CFG_ASCLINFDIV_##pllFreq << IFX_SCU_CCUCON1_ASCLINFDIV_OFF) | \
(IFXSCU_CFG_ASCLINSDIV_##pllFreq << IFX_SCU_CCUCON1_ASCLINSDIV_OFF))

Definition at line 1277 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CCUCON1_MASK
Value:
( \
(IFX_SCU_CCUCON1_CANDIV_MSK << IFX_SCU_CCUCON1_CANDIV_OFF) | \
(IFX_SCU_CCUCON1_ERAYDIV_MSK << IFX_SCU_CCUCON1_ERAYDIV_OFF) | \
(IFX_SCU_CCUCON1_STMDIV_MSK << IFX_SCU_CCUCON1_STMDIV_OFF) | \
(IFX_SCU_CCUCON1_GTMDIV_MSK << IFX_SCU_CCUCON1_GTMDIV_OFF) | \
(IFX_SCU_CCUCON1_ETHDIV_MSK << IFX_SCU_CCUCON1_ETHDIV_OFF) | \
(IFX_SCU_CCUCON1_ASCLINFDIV_MSK << IFX_SCU_CCUCON1_ASCLINFDIV_OFF) | \
(IFX_SCU_CCUCON1_ASCLINSDIV_MSK << IFX_SCU_CCUCON1_ASCLINSDIV_OFF))

Macros to configure CCUCON1 Clock distribution.

Definition at line 1267 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CCUCON2   IFXSCU_CFG_CCUCON2_BASIC(IFXSCU_CFG_PLL_FREQ)

Definition at line 1302 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CCUCON2_BASIC (   pllFreq)    IFXSCU_CFG_CCUCON2_BASIC_(pllFreq)

Definition at line 1300 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CCUCON2_BASIC_ (   pllFreq)
Value:
(uint32)( \
(IFXSCU_CFG_BBBDIV_##pllFreq << IFX_SCU_CCUCON2_BBBDIV_OFF))

Definition at line 1296 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CCUCON2_MASK
Value:
( \
(IFX_SCU_CCUCON2_BBBDIV_MSK << IFX_SCU_CCUCON2_BBBDIV_OFF))

Macros to configure CCUCON2 Clock distribution.

Definition at line 1292 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CCUCON5   IFXSCU_CFG_CCUCON5_BASIC(IFXSCU_CFG_PLL_FREQ)

Definition at line 1315 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CCUCON5_BASIC (   pllFreq)    IFXSCU_CFG_CCUCON5_BASIC_(pllFreq)

Definition at line 1313 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CCUCON5_BASIC_ (   pllFreq)
Value:
(uint32)( \
(IFXSCU_CFG_MAXDIV_##pllFreq << IFX_SCU_CCUCON5_MAXDIV_OFF))

Definition at line 1309 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CCUCON5_MASK
Value:
( \
(IFX_SCU_CCUCON5_MAXDIV_MSK << IFX_SCU_CCUCON5_MAXDIV_OFF))

Macros to configure CCUCON5 Clock distribution.

Definition at line 1305 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CCUCON6   IFXSCU_CFG_CCUCON6_BASIC(IFXSCU_CFG_PLL_FREQ)

Definition at line 1328 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CCUCON6_BASIC (   pllFreq)    IFXSCU_CFG_CCUCON6_BASIC_(pllFreq)

Definition at line 1326 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CCUCON6_BASIC_ (   pllFreq)
Value:
(uint32)( \
(IFXSCU_CFG_CPU0DIV_##pllFreq << IFX_SCU_CCUCON6_CPU0DIV_OFF))

Definition at line 1322 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CCUCON6_MASK
Value:
( \
(IFX_SCU_CCUCON6_CPU0DIV_MSK << IFX_SCU_CCUCON6_CPU0DIV_OFF))

Macros to configure CCUCON6 Clock distribution.

Definition at line 1318 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CCUCON7   IFXSCU_CFG_CCUCON7_BASIC(IFXSCU_CFG_PLL_FREQ)

Definition at line 1341 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CCUCON7_BASIC (   pllFreq)    IFXSCU_CFG_CCUCON7_BASIC_(pllFreq)

Definition at line 1339 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CCUCON7_BASIC_ (   pllFreq)
Value:
(uint32)( \
(IFXSCU_CFG_CPU1DIV_##pllFreq << IFX_SCU_CCUCON7_CPU1DIV_OFF))

Definition at line 1335 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CCUCON7_MASK
Value:
( \
(IFX_SCU_CCUCON7_CPU1DIV_MSK << IFX_SCU_CCUCON7_CPU1DIV_OFF))

Macros to configure CCUCON7 Clock distribution.

Definition at line 1331 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CCUCON8   IFXSCU_CFG_CCUCON8_BASIC(IFXSCU_CFG_PLL_FREQ)

Definition at line 1354 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CCUCON8_BASIC (   pllFreq)    IFXSCU_CFG_CCUCON8_BASIC_(pllFreq)

Definition at line 1352 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CCUCON8_BASIC_ (   pllFreq)
Value:
(uint32)( \
(IFXSCU_CFG_CPU2DIV_##pllFreq << IFX_SCU_CCUCON8_CPU2DIV_OFF))

Definition at line 1348 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CCUCON8_MASK
Value:
( \
(IFX_SCU_CCUCON8_CPU2DIV_MSK << IFX_SCU_CCUCON8_CPU2DIV_OFF))

Macros to configure CCUCON8 Clock distribution.

Definition at line 1344 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CLK_DISTRIBUTION
Value:
{ \
/* { uint32 value, uint32 mask }*/ \
{IFXSCU_CFG_CCUCON0, IFXSCU_CFG_CCUCON0_MASK}, /*IfxScuCcu_CcuconRegConfig ccucon0;*/ \
{IFXSCU_CFG_CCUCON1, IFXSCU_CFG_CCUCON1_MASK}, /*IfxScuCcu_CcuconRegConfig ccucon1;*/ \
{IFXSCU_CFG_CCUCON2, IFXSCU_CFG_CCUCON2_MASK}, /*IfxScuCcu_CcuconRegConfig ccucon2;*/ \
{IFXSCU_CFG_CCUCON5, IFXSCU_CFG_CCUCON5_MASK}, /*IfxScuCcu_CcuconRegConfig ccucon5;*/ \
{IFXSCU_CFG_CCUCON6, IFXSCU_CFG_CCUCON6_MASK}, /*IfxScuCcu_CcuconRegConfig ccucon6;*/ \
{IFXSCU_CFG_CCUCON7, IFXSCU_CFG_CCUCON7_MASK}, /*IfxScuCcu_CcuconRegConfig ccucon7;*/ \
{IFXSCU_CFG_CCUCON8, IFXSCU_CFG_CCUCON8_MASK} /*IfxScuCcu_CcuconRegConfig ccucon8;*/ \
}

Definition at line 1356 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CPU0DIV_133MHZ   (0) /*Same as SRIDIV */

Macro to configure CPU0DIV at 133MHz target frequency.

Definition at line 1011 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CPU0DIV_160MHZ   (0) /*Same as SRIDIV */

Macro to configure CPU0DIV at 160MHz target frequency.

Definition at line 1016 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CPU0DIV_200MHZ   (0) /*Same as SRIDIV */

Macro to configure CPU0DIV at 200MHz target frequency.

Definition at line 1021 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CPU0DIV_240MHZ   (0) /*Same as SRIDIV */

Macro to configure CPU0DIV at 240MHz target frequency.

Definition at line 1026 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CPU0DIV_300MHZ   (0) /*Same as SRIDIV */

Macro to configure CPU0DIV at 300MHz target frequency.

Definition at line 1031 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CPU0DIV_80MHZ   (0) /*Same as SRIDIV */

Macro to configure CPU0DIV at 80MHz target frequency.

Definition at line 1006 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CPU1DIV_133MHZ   (0) /*Same as SRIDIV */

Macro to configure CPU1DIV at 133MHz target frequency.

Definition at line 1041 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CPU1DIV_160MHZ   (0) /*Same as SRIDIV */

Macro to configure CPU1DIV at 160MHz target frequency.

Definition at line 1046 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CPU1DIV_200MHZ   (0) /*Same as SRIDIV */

Macro to configure CPU1DIV at 200MHz target frequency.

Definition at line 1051 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CPU1DIV_240MHZ   (0) /*Same as SRIDIV */

Macro to configure CPU1DIV at 240MHz target frequency.

Definition at line 1056 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CPU1DIV_300MHZ   (0) /*Same as SRIDIV */

Macro to configure CPU1DIV at 300MHz target frequency.

Definition at line 1061 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CPU1DIV_80MHZ   (0) /*Same as SRIDIV */

Macro to configure CPU1DIV at 80MHz target frequency.

Definition at line 1036 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CPU2DIV_133MHZ   (0) /*Same as SRIDIV */

Macro to configure CPU2DIV at 133MHz target frequency.

Definition at line 1071 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CPU2DIV_160MHZ   (0) /*Same as SRIDIV */

Macro to configure CPU2DIV at 160MHz target frequency.

Definition at line 1076 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CPU2DIV_200MHZ   (0) /*Same as SRIDIV */

Macro to configure CPU2DIV at 200MHz target frequency.

Definition at line 1081 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CPU2DIV_240MHZ   (0) /*Same as SRIDIV */

Macro to configure CPU2DIV at 240MHz target frequency.

Definition at line 1086 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CPU2DIV_300MHZ   (0) /*Same as SRIDIV */

Macro to configure CPU2DIV at 300MHz target frequency.

Definition at line 1091 of file IfxScu_cfg.h.

#define IFXSCU_CFG_CPU2DIV_80MHZ   (0) /*Same as SRIDIV */

Macro to configure CPU2DIV at 80MHz target frequency.

Definition at line 1066 of file IfxScu_cfg.h.

#define IFXSCU_CFG_ERAYDIV_133MHZ   (IFXSCU_CFG_MAXDIV_133MHZ * 2) /*Max: 80MHz */

Macro to configure ERAYDIV at 133MHz target frequency.

Definition at line 801 of file IfxScu_cfg.h.

#define IFXSCU_CFG_ERAYDIV_160MHZ   (IFXSCU_CFG_MAXDIV_160MHZ * 2) /*Max: 80MHz */

Macro to configure ERAYDIV at 160MHz target frequency.

Definition at line 806 of file IfxScu_cfg.h.

#define IFXSCU_CFG_ERAYDIV_200MHZ   (IFXSCU_CFG_MAXDIV_200MHZ * 3) /*Max: 80MHz */

Macro to configure ERAYDIV at 200MHz target frequency.

Definition at line 811 of file IfxScu_cfg.h.

#define IFXSCU_CFG_ERAYDIV_240MHZ   (IFXSCU_CFG_MAXDIV_240MHZ * 3) /*Max: 80MHz */

Macro to configure ERAYDIV at 200MHz target frequency.

Definition at line 816 of file IfxScu_cfg.h.

#define IFXSCU_CFG_ERAYDIV_300MHZ   (IFXSCU_CFG_MAXDIV_300MHZ * 4) /*Max: 80MHz */

Macro to configure ERAYDIV at 300MHz target frequency.

Definition at line 821 of file IfxScu_cfg.h.

#define IFXSCU_CFG_ERAYDIV_80MHZ   (IFXSCU_CFG_MAXDIV_80MHZ) /*Max: 80MHz */

Macro to configure ERAYDIV at 80MHz target frequency.

Definition at line 796 of file IfxScu_cfg.h.

#define IFXSCU_CFG_ETHDIV_133MHZ   (IFXSCU_CFG_MAXDIV_133MHZ * 3)

Macro to configure ETHDIV at 133MHz target frequency.

Definition at line 891 of file IfxScu_cfg.h.

#define IFXSCU_CFG_ETHDIV_160MHZ   (IFXSCU_CFG_MAXDIV_160MHZ * 4)

Macro to configure ETHDIV at 160MHz target frequency.

Definition at line 896 of file IfxScu_cfg.h.

#define IFXSCU_CFG_ETHDIV_200MHZ   (IFXSCU_CFG_MAXDIV_200MHZ * 4)

Macro to configure ETHDIV at 200MHz target frequency.

Definition at line 901 of file IfxScu_cfg.h.

#define IFXSCU_CFG_ETHDIV_240MHZ   (IFXSCU_CFG_MAXDIV_240MHZ * 5)

Macro to configure ETHDIV at 240MHz target frequency.

Definition at line 906 of file IfxScu_cfg.h.

#define IFXSCU_CFG_ETHDIV_300MHZ   (IFXSCU_CFG_MAXDIV_300MHZ * 6)

Macro to configure ETHDIV at 300MHz target frequency.

Definition at line 911 of file IfxScu_cfg.h.

#define IFXSCU_CFG_ETHDIV_80MHZ   (IFXSCU_CFG_MAXDIV_80MHZ * 2)

Macro to configure ETHDIV at 80MHz target frequency.

Definition at line 886 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_FCON_WSDFLASH_133MHZ   (14-1)

Macro to configure FCON.WSDFLASH_ at 133MHz target frequency, where fSRI= 133/2= 66.5MHZ.

Definition at line 1169 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_FCON_WSDFLASH_160MHZ   (16-1)

Macro to configure FCON.WSDFLASH at 160MHz target frequency, where fSRI= 160/2= 80MHZ.

Definition at line 1174 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_FCON_WSDFLASH_200MHZ   (20-1)

Macro to configure FCON.WSDFLASH at 200MHz target frequency, where fSRI= 200/2= 100MHZ.

Definition at line 1179 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_FCON_WSDFLASH_240MHZ   (16-1)

Macro to configure FCON.WSDFLASH at 240MHz target frequency, where fSRI= 240/3= 80MHZ.

Definition at line 1184 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_FCON_WSDFLASH_300MHZ   (20-1)

Macro to configure FCON.WSDFLASH at 300MHz target frequency, where fSRI= 300/3= 100MHZ.

Definition at line 1189 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_FCON_WSDFLASH_80MHZ   (16-1)

Macro to configure FCON.WSDFLASH at 80MHz target frequency.

Definition at line 1164 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_FCON_WSECDF_133MHZ   (2-1)

Macro to configure FCON.WSECDF at 133MHz target frequency, where fSRI= 133/2= 66.5MHZ.

Definition at line 1200 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_FCON_WSECDF_160MHZ   (2-1)

Macro to configure FCON.WSECDF at 160MHz target frequency, where fSRI= 160/2= 80MHZ.

Definition at line 1205 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_FCON_WSECDF_200MHZ   (2-1)

Macro to configure FCON.WSECDF at 200MHz target frequency, where fSRI= 200/2= 100MHZ.

Definition at line 1210 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_FCON_WSECDF_240MHZ   (2-1)

Macro to configure FCON.WSECDF at 240MHz target frequency, where fSRI= 240/3= 80MHZ.

Definition at line 1215 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_FCON_WSECDF_300MHZ   (2-1)

Macro to configure FCON.WSECDF at 300MHz target frequency, where fSRI= 300/3= 100MHZ.

Definition at line 1220 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_FCON_WSECDF_80MHZ   (2-1)

Macro to configure FCON.WSECDF at 80MHz target frequency.

Definition at line 1195 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_FCON_WSECPF_133MHZ   (2-1)

Macro to configure FCON.WSECPF at 133MHz target frequency.

Definition at line 1138 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_FCON_WSECPF_160MHZ   (2-1)

Macro to configure FCON.WSECPF at 160MHz target frequency.

Definition at line 1143 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_FCON_WSECPF_200MHZ   (2-1)

Macro to configure FCON.WSECPF at 200MHz target frequency.

Definition at line 1148 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_FCON_WSECPF_240MHZ   (3-1)

Macro to configure FCON.WSECPF_ at 240MHz target frequency.

Definition at line 1153 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_FCON_WSECPF_300MHZ   (3-1)

Macro to configure FCON.WSECPF at 300MHz target frequency.

Definition at line 1158 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_FCON_WSECPF_80MHZ   (1-1)

Macro to configure FCON.WSECP_ at 80MHz target frequency.

Definition at line 1133 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_FCON_WSPFLASH_133MHZ   (4-1)

Macro to configure FCON.WSPFLASH at 133MHz target frequency.

Definition at line 1107 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_FCON_WSPFLASH_160MHZ   (5-1)

Macro to configure FCON.WSPFLASH at 160MHz target frequency.

Definition at line 1112 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_FCON_WSPFLASH_200MHZ   (6-1)

Macro to configure FCON.WSPFLASH at 200MHz target frequency.

Definition at line 1117 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_FCON_WSPFLASH_240MHZ   (8-1)

Macro to configure FCON.WSPFLASH at 240MHz target frequency.

Definition at line 1122 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_FCON_WSPFLASH_300MHZ   (9-1)

Macro to configure FCON.WSPFLASH at 300MHz target frequency.

Definition at line 1127 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_FCON_WSPFLASH_80MHZ   (3-1)

Macros to configure FLASH.FCON register for flash waitstate configuration. IfxScuCcu_InitialStepConfig.

Macro to configure FCON.WSPFLASH at 80MHz target frequency

Definition at line 1102 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_WAITSTATE
Value:
/* { uint32 value, uint32 mask }*/ \

Definition at line 1379 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_WAITSTATE_MSK
Value:
( \
(IFX_FLASH_FCON_WSPFLASH_MSK << IFX_FLASH_FCON_WSPFLASH_OFF) | \
(IFX_FLASH_FCON_WSECPF_MSK << IFX_FLASH_FCON_WSECPF_OFF) | \
(IFX_FLASH_FCON_WSDFLASH_MSK << IFX_FLASH_FCON_WSDFLASH_OFF) | \
(IFX_FLASH_FCON_WSECDF_MSK << IFX_FLASH_FCON_WSECDF_OFF))

Macros to configure FLASH.FCON registers.

Definition at line 1224 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_WAITSTATE_VAL   IFXSCU_CFG_FLASH_WAITSTATE_VAL_BASIC(IFXSCU_CFG_PLL_FREQ)

Definition at line 1240 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_WAITSTATE_VAL_BASIC (   pllFreq)    IFXSCU_CFG_FLASH_WAITSTATE_VAL_BASIC_(pllFreq)

Definition at line 1238 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FLASH_WAITSTATE_VAL_BASIC_ (   pllFreq)
Value:
( \
(IFXSCU_CFG_FLASH_FCON_WSPFLASH_##pllFreq << IFX_FLASH_FCON_WSPFLASH_OFF)| \
(IFXSCU_CFG_FLASH_FCON_WSECPF_##pllFreq << IFX_FLASH_FCON_WSECPF_OFF) | \
(IFXSCU_CFG_FLASH_FCON_WSDFLASH_##pllFreq << IFX_FLASH_FCON_WSDFLASH_OFF)| \
(IFXSCU_CFG_FLASH_FCON_WSECDF_##pllFreq << IFX_FLASH_FCON_WSECDF_OFF))

Definition at line 1231 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FSI2DIV_133MHZ   (IFXSCU_CFG_MAXDIV_133MHZ) /*Same as MAXDIV */

Macro to configure FSI2DIV at 133MHz target frequency.

Definition at line 711 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FSI2DIV_160MHZ   (IFXSCU_CFG_MAXDIV_160MHZ) /*Same as MAXDIV */

Macro to configure FSI2DIV at 160MHz target frequency.

Definition at line 716 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FSI2DIV_200MHZ   (IFXSCU_CFG_MAXDIV_200MHZ) /*Same as MAXDIV */

Macro to configure FSI2DIV at 200MHz target frequency.

Definition at line 721 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FSI2DIV_240MHZ   (IFXSCU_CFG_MAXDIV_240MHZ) /*Same as MAXDIV */

Macro to configure FSI2DIV at 240MHz target frequency.

Definition at line 726 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FSI2DIV_300MHZ   (IFXSCU_CFG_MAXDIV_300MHZ) /*Same as MAXDIV */

Macro to configure FSI2DIV at 300MHz target frequency.

Definition at line 731 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FSI2DIV_80MHZ   (IFXSCU_CFG_MAXDIV_80MHZ) /*Same as MAXDIV */

Macro to configure FSI2DIV at 80MHz target frequency.

Definition at line 706 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FSIDIV_133MHZ   (IFXSCU_CFG_MAXDIV_133MHZ * 2) /*Max: 100MHz */

Macro to configure FSIDIV at 133MHz target frequency.

Definition at line 741 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FSIDIV_160MHZ   (IFXSCU_CFG_MAXDIV_160MHZ * 2) /*Max: 100MHz */

Macro to configure FSIDIV at 160MHz target frequency.

Definition at line 746 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FSIDIV_200MHZ   (IFXSCU_CFG_MAXDIV_200MHZ * 2) /*Max: 100MHz */

Macro to configure FSIDIV at 200MHz target frequency.

Definition at line 751 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FSIDIV_240MHZ   (IFXSCU_CFG_MAXDIV_240MHZ * 2) /*Max: 100MHz */

Macro to configure FSIDIV at 240MHz target frequency.

Definition at line 756 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FSIDIV_300MHZ   (IFXSCU_CFG_MAXDIV_300MHZ * 2) /*Max: 100MHz */

Macro to configure FSIDIV at 300MHz target frequency.

Definition at line 761 of file IfxScu_cfg.h.

#define IFXSCU_CFG_FSIDIV_80MHZ   (IFXSCU_CFG_MAXDIV_80MHZ) /*Max: 100MHz */

Macro to configure FSIDIV at 80MHz target frequency.

Definition at line 736 of file IfxScu_cfg.h.

#define IFXSCU_CFG_GTMDIV_133MHZ   (IFXSCU_CFG_MAXDIV_133MHZ * 2) /*Max: 100MHz */

Macro to configure GTMDIV at 133MHz target frequency.

Definition at line 861 of file IfxScu_cfg.h.

#define IFXSCU_CFG_GTMDIV_160MHZ   (IFXSCU_CFG_MAXDIV_160MHZ * 2) /*Max: 100MHz */

Macro to configure GTMDIV at 160MHz target frequency.

Definition at line 866 of file IfxScu_cfg.h.

#define IFXSCU_CFG_GTMDIV_200MHZ   (IFXSCU_CFG_MAXDIV_200MHZ * 2) /*Max: 100MHz */

Macro to configure GTMDIV at 200MHz target frequency.

Definition at line 871 of file IfxScu_cfg.h.

#define IFXSCU_CFG_GTMDIV_240MHZ   (IFXSCU_CFG_MAXDIV_240MHZ * 3) /*Max: 100MHz */

Macro to configure GTMDIV at 240MHz target frequency.

Definition at line 876 of file IfxScu_cfg.h.

#define IFXSCU_CFG_GTMDIV_300MHZ   (IFXSCU_CFG_MAXDIV_300MHZ * 3) /*Max: 100MHz */

Macro to configure GTMDIV at 300MHz target frequency.

Definition at line 881 of file IfxScu_cfg.h.

#define IFXSCU_CFG_GTMDIV_80MHZ   (IFXSCU_CFG_MAXDIV_80MHZ) /*Max: 100MHz */

Macro to configure GTMDIV at 80MHz target frequency.

Definition at line 856 of file IfxScu_cfg.h.

#define IFXSCU_CFG_MAXDIV_133MHZ   (1)

Macro to configure MAXDIV at 133MHz target frequency.

Definition at line 561 of file IfxScu_cfg.h.

#define IFXSCU_CFG_MAXDIV_160MHZ   (1)

Macro to configure MAXDIV at 160MHz target frequency.

Definition at line 566 of file IfxScu_cfg.h.

#define IFXSCU_CFG_MAXDIV_200MHZ   (1)

Macro to configure MAXDIV at 200MHz target frequency.

Definition at line 571 of file IfxScu_cfg.h.

#define IFXSCU_CFG_MAXDIV_240MHZ   (1)

Macro to configure MAXDIV at 240MHz target frequency.

Definition at line 576 of file IfxScu_cfg.h.

#define IFXSCU_CFG_MAXDIV_300MHZ   (1)

Macro to configure MAXDIV at 300MHz target frequency.

Definition at line 581 of file IfxScu_cfg.h.

#define IFXSCU_CFG_MAXDIV_80MHZ   (1)

Macros to configure CCUCON registers. Macros to configure the Pll initial step, where the configuration of PDIV, NDIV and K2DIV are done for the internal Oscillator frequency. IfxScuCcu_InitialStepConfig.

Macros to configure CCUCON registers Macro to configure MAXDIV at 80MHz target frequency

Definition at line 556 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_FREQ   200MHZ

Definition at line 1404 of file IfxScu_cfg.h.

Definition at line 1377 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_133MHZ
Value:
/*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/ \
{(1 - 1), (50 - 1), (8 - 1), 0.000200F}

Macro for Initial Pll step, for profile with 16MHz Crystal and 133MHz target.

Definition at line 407 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_160MHZ
Value:
/*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/ \
{(1 - 1), (40 - 1), (6 - 1), 0.000200F}

Macro for Initial Pll step, for profile with 16MHz Crystal and 160MHz target.

Definition at line 414 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_200MHZ
Value:
/*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/ \
{(1 - 1), (50 - 1), (8 - 1), 0.000200F}

Macro for Initial Pll step, for profile with 16MHz Crystal and 200MHz target.

Definition at line 421 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_240MHZ
Value:
/*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/ \
{(1 - 1), (45 - 1), (7 - 1), 0.000200F}

Macro for Initial Pll step, for profile with 16MHz Crystal and 240MHz target.

Definition at line 428 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_80MHZ
Value:
/*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/ \
{(1 - 1), (40 - 1), (7 - 1), 0.000200F}

Macros to configure Initial Pll step. Macros to configure the Pll initial step, where the configuration of PDIV, NDIV and K2DIV are done for the internal Oscillator frequency. IfxScuCcu_InitialStepConfig.

Macro for Initial Pll step, for profile with 16MHz Crystal and 80MHz target

Definition at line 400 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_133MHZ
Value:
/*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/ \
{(2 - 1), (80 - 1), (8 - 1), 0.000200F}

Macro for Initial Pll step, for profile with 20MHz Crystal and 133MHz target.

Definition at line 444 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_160MHZ
Value:
/*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/ \
{(2 - 1), (64 - 1), (6 - 1), 0.000200F}

Macro for Initial Pll step, for profile with 20MHz Crystal and 160MHz target.

Definition at line 451 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_200MHZ
Value:
/*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/ \
{(2 - 1), (60 - 1), (6 - 1), 0.000200F}

Macro for Initial Pll step, for profile with 20MHz Crystal and 200MHz target.

Definition at line 458 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_240MHZ
Value:
/*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/ \
{(2 - 1), (72 - 1), (7 - 1), 0.000200F}

Macro for Initial Pll step, for profile with 20MHz Crystal and 240MHz target.

Definition at line 465 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_300MHZ
Value:
/*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/ \
{(2 - 1), (60 - 1), (6 - 1), 0.000200F}

Macro for Initial Pll step, for profile with 20MHz Crystal and 300MHz target.

Definition at line 472 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_80MHZ
Value:
/*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/ \
{(2 - 1), (64 - 1), (7 - 1), 0.000200F}

Macro for Initial Pll step, for profile with 20MHz Crystal and 80MHz target.

Definition at line 437 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_133MHZ
Value:
/*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/ \
{(4 - 1), (80 - 1), (8 - 1), 0.000200F}

Macro for Initial Pll step, for profile with 40MHz Crystal and 133MHz target.

Definition at line 488 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_160MHZ
Value:
/*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/ \
{(4 - 1), (64 - 1), (6 - 1), 0.000200F}

Macro for Initial Pll step, for profile with 40MHz Crystal and 160MHz target.

Definition at line 495 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_200MHZ
Value:
/*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/ \
{(4 - 1), (60 - 1), (6 - 1), 0.000200F}

Macro for Initial Pll step, for profile with 40MHz Crystal and 200MHz target.

Definition at line 502 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_240MHZ
Value:
/*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/ \
{(4 - 1), (72 - 1), (7 - 1), 0.000200F}

Macro for Initial Pll step, for profile with 40MHz Crystal and 240MHz target.

Definition at line 509 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_300MHZ
Value:
/*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/ \
{(4 - 1), (60 - 1), (6 - 1), 0.000200F}

Macro for Initial Pll step, for profile with 40MHz Crystal and 300MHz target.

Definition at line 516 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_80MHZ
Value:
/*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/ \
{(4 - 1), (64 - 1), (7 - 1), 0.000200F}

Macro for Initial Pll step, for profile with 40MHz Crystal and 80MHz target.

Definition at line 481 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_INITIAL_STEP_8MHZ_160MHZ
Value:
/*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/ \
{(1 - 1), (60 - 1), (5 - 1), 0.000200F}

Macro for Initial Pll step, for profile with 8MHz Crystal and 160MHz target.

Definition at line 533 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_INITIAL_STEP_8MHZ_200MHZ
Value:
/*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/ \
{(1 - 1), (75 - 1), (6 - 1), 0.000200F}

Macro for Initial Pll step, for profile with 8MHz Crystal and 200MHz target.

Definition at line 540 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_INITIAL_STEP_8MHZ_80MHZ
Value:
/*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime } ??*/ \
{(1 - 1), (50 - 1), (5 - 1), 0.000200F}

Macro for Initial Pll step, for profile with 8MHz Crystal and 80MHz target.

Definition at line 526 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_INITIAL_STEP_BASIC (   xtalFreq,
  pllFreq 
)    IFXSCU_CFG_PLL_INITIAL_STEP_BASIC_(xtalFreq, pllFreq)

Definition at line 1376 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_INITIAL_STEP_BASIC_ (   xtalFreq,
  pllFreq 
)    IFXSCU_CFG_PLL_INITIAL_STEP_##xtalFreq##_##pllFreq

Definition at line 1375 of file IfxScu_cfg.h.

Definition at line 1372 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_STEPS_16MHZ_133MHZ
Value:
{ /*Step 0 Config: 114MHz*/ \
(7 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}, \
{ /*Step 1 Config: 133MHz*/ \
(6 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
},

Macro for Pll step for profile with 16MHz Crystal and 133MHz target.

Definition at line 74 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_STEPS_16MHZ_160MHZ
Value:
{ /*Step 1 Config: 128MHz*/ \
(5 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}, \
{ /*Step 2 Config: 160MHz*/ \
(4 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}

Macro for Pll step for profile with 16MHz Crystal and 160MHz target.

Definition at line 89 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_STEPS_16MHZ_200MHZ
Value:
{ /*Step 0 Config: 120MHz*/ \
(6 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}, \
{ /*Step 1 Config: 150MHz*/ \
(5 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}, \
{ /*Step 2 Config: 200MHz*/ \
(4 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}

Macro for Pll step for profile with 16MHz Crystal and 200MHz target.

Definition at line 104 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_STEPS_16MHZ_240MHZ
Value:
{ /*Step 0 Config: 144MHz*/ \
(5 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}, \
{ /*Step 1 Config: 180MHz*/ \
(4 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}, \
{ /*Step 2 Config: 240MHz*/ \
(3 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}

Macro for Pll step for profile with 16MHz Crystal and 240MHz target.

Definition at line 124 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_STEPS_16MHZ_80MHZ
Value:
{ /*Step 0 Config: 80MHz*/ \
(8 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
},

Macros to configure Pll steps, Macros to configure the Pll steps for different profiles of Crystal frequency and target frequencies. This configuration is important for the current jump controll during clock throttling. IfxScuCcu_PllStepsConfig.

Macro for Pll step for profile with 16MHz Crystal and 80MHz target

Definition at line 64 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_STEPS_20MHZ_133MHZ
Value:
{ /*Step 0 Config: 114MHz*/ \
(7 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}, \
{ /*Step 1 Config: 133MHz*/ \
(6 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
},

Macro for Pll step for profile with 20MHz Crystal and 133MHz target.

Definition at line 155 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_STEPS_20MHZ_160MHZ
Value:
{ /*Step 1 Config: 128MHz*/ \
(5 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}, \
{ /*Step 2 Config: 160MHz*/ \
(4 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}

Macro for Pll step for profile with 20MHz Crystal and 160MHz target.

Definition at line 170 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_STEPS_20MHZ_200MHZ
Value:
{ /*Step 0 Config: 120MHz*/ \
(5 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}, \
{ /*Step 1 Config: 150MHz*/ \
(4 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}, \
{ /*Step 2 Config: 200MHz*/ \
(3 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}

Macro for Pll step for profile with 20MHz Crystal and 200MHz target.

Definition at line 185 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_STEPS_20MHZ_240MHZ
Value:
{ /*Step 0 Config: 144MHz*/ \
(5 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}, \
{ /*Step 1 Config: 180MHz*/ \
(4 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}, \
{ /*Step 2 Config: 240MHz*/ \
(3 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}

Macro for Pll step for profile with 20MHz Crystal and 240MHz target.

Definition at line 205 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_STEPS_20MHZ_300MHZ
Value:
{ /*Step 0 Config: 150MHz*/ \
(4 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}, \
{ /*Step 1 Config: 200MHz*/ \
(3 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}, \
{ /*Step 2 Config: 300MHz*/ \
(2 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}

Macro for Pll step for profile with 20MHz Crystal and 300MHz target.

Definition at line 225 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_STEPS_20MHZ_80MHZ
Value:
{ /*Step 0 Config: 80MHz*/ \
(8 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
},

Macro for Pll step for profile with 20MHz Crystal and 80MHz target.

Definition at line 145 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_STEPS_40MHZ_133MHZ
Value:
{ /*Step 0 Config: 114MHz*/ \
(7 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}, \
{ /*Step 1 Config: 133MHz*/ \
(6 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
},

Macro for Pll step for profile with 40MHz Crystal and 133MHz target.

Definition at line 256 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_STEPS_40MHZ_160MHZ
Value:
{ /*Step 1 Config: 128MHz*/ \
(5 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}, \
{ /*Step 2 Config: 160MHz*/ \
(4 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}

Macro for Pll step for profile with 40MHz Crystal and 160MHz target.

Definition at line 271 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_STEPS_40MHZ_200MHZ
Value:
{ /*Step 0 Config: 120MHz*/ \
(5 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}, \
{ /*Step 1 Config: 150MHz*/ \
(4 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}, \
{ /*Step 2 Config: 200MHz*/ \
(3 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}

Macro for Pll step for profile with 40MHz Crystal and 200MHz target.

Definition at line 286 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_STEPS_40MHZ_240MHZ
Value:
{ /*Step 0 Config: 144MHz*/ \
(5 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}, \
{ /*Step 1 Config: 180MHz*/ \
(4 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}, \
{ /*Step 2 Config: 240MHz*/ \
(3 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}

Macro for Pll step for profile with 40MHz Crystal and 240MHz target.

Definition at line 306 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_STEPS_40MHZ_300MHZ
Value:
{ /*Step 0 Config: 150MHz*/ \
(4 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}, \
{ /*Step 1 Config: 200MHz*/ \
(3 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}, \
{ /*Step 2 Config: 300MHz*/ \
(2 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}

Macro for Pll step for profile with 40MHz Crystal and 300MHz target.

Definition at line 326 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_STEPS_40MHZ_80MHZ
Value:
{ /*Step 0 Config: 80MHz*/ \
(8 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
},

Macro for Pll step for profile with 40MHz Crystal and 80MHz target.

Definition at line 246 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_STEPS_8MHZ_160MHZ
Value:
{ /*Step 0 Config: 100MHz*/ \
(4 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}, \
{ /*Step 1 Config: 160MHz*/ \
(3 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
},

Macro for Pll step for profile with 8MHz Crystal and 160MHz target.

Definition at line 357 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_STEPS_8MHZ_200MHZ
Value:
{ /*Step 0 Config: 120MHz*/ \
(5 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}, \
{ /*Step 0 Config: 150MHz*/ \
(4 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
}, \
{ /*Step 1 Config: 200MHz*/ \
(3 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
},

Macro for Pll step for profile with 8MHz Crystal and 200MHz target.

Definition at line 372 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_STEPS_8MHZ_80MHZ
Value:
{ /*Step 0 Config: 80MHz*/ \
(5 - 1), /*uint8 k2Step;*/ \
0.000100, /*float32 waitTime;*/ \
0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
},

Macro for Pll step for profile with 8MHz Crystal and 80MHz target.

Definition at line 347 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_STEPS_BASIC (   xtalFreq,
  pllFreq 
)    IFXSCU_CFG_PLL_STEPS_BASIC_(xtalFreq, pllFreq)

Definition at line 1371 of file IfxScu_cfg.h.

#define IFXSCU_CFG_PLL_STEPS_BASIC_ (   xtalFreq,
  pllFreq 
)    IFXSCU_CFG_PLL_STEPS_##xtalFreq##_##pllFreq

Definition at line 1370 of file IfxScu_cfg.h.

#define IFXSCU_CFG_SPBDIV_133MHZ   (IFXSCU_CFG_MAXDIV_133MHZ * 2) /*Max: 100MHz */

Macro to configure SPBDIV at 133MHz target frequency.

Definition at line 681 of file IfxScu_cfg.h.

#define IFXSCU_CFG_SPBDIV_160MHZ   (IFXSCU_CFG_MAXDIV_160MHZ * 2) /*Max: 100MHz */

Macro to configure SPBDIV at 160MHz target frequency.

Definition at line 686 of file IfxScu_cfg.h.

#define IFXSCU_CFG_SPBDIV_200MHZ   (IFXSCU_CFG_MAXDIV_200MHZ * 2) /*Max: 100MHz */

Macro to configure SPBDIV at 200MHz target frequency.

Definition at line 691 of file IfxScu_cfg.h.

#define IFXSCU_CFG_SPBDIV_240MHZ   (IFXSCU_CFG_MAXDIV_240MHZ * 3) /*Max: 100MHz */

Macro to configure SPBDIV at 240MHz target frequency.

Definition at line 696 of file IfxScu_cfg.h.

#define IFXSCU_CFG_SPBDIV_300MHZ   (IFXSCU_CFG_MAXDIV_300MHZ * 3) /*Max: 100MHz */

Macro to configure SPBDIV at 300MHz target frequency.

Definition at line 701 of file IfxScu_cfg.h.

#define IFXSCU_CFG_SPBDIV_80MHZ   (IFXSCU_CFG_MAXDIV_80MHZ) /*Max: 100MHz */

Macro to configure SPBDIV at 80MHz target frequency.

Definition at line 676 of file IfxScu_cfg.h.

#define IFXSCU_CFG_SRIDIV_133MHZ   (IFXSCU_CFG_MAXDIV_133MHZ) /*Same as MAXDIV */

Macro to configure SRIDIV at 133MHz target frequency.

Definition at line 591 of file IfxScu_cfg.h.

#define IFXSCU_CFG_SRIDIV_160MHZ   (IFXSCU_CFG_MAXDIV_160MHZ) /*Same as MAXDIV */

Macro to configure SRIDIV at 160MHz target frequency.

Definition at line 596 of file IfxScu_cfg.h.

#define IFXSCU_CFG_SRIDIV_200MHZ   (IFXSCU_CFG_MAXDIV_200MHZ) /*Same as MAXDIV */

Macro to configure SRIDIV at 200MHz target frequency.

Definition at line 601 of file IfxScu_cfg.h.

#define IFXSCU_CFG_SRIDIV_240MHZ   (IFXSCU_CFG_MAXDIV_240MHZ) /*Same as MAXDIV */

Macro to configure SRIDIV at 240MHz target frequency.

Definition at line 606 of file IfxScu_cfg.h.

#define IFXSCU_CFG_SRIDIV_300MHZ   (IFXSCU_CFG_MAXDIV_300MHZ) /*Same as MAXDIV */

Macro to configure SRIDIV at 300MHz target frequency.

Definition at line 611 of file IfxScu_cfg.h.

#define IFXSCU_CFG_SRIDIV_80MHZ   (IFXSCU_CFG_MAXDIV_80MHZ) /*Same as MAXDIV */

Macro to configure SRIDIV at 80MHz target frequency.

Definition at line 586 of file IfxScu_cfg.h.

#define IFXSCU_CFG_STMDIV_133MHZ   (IFXSCU_CFG_MAXDIV_133MHZ * 2) /*Max: 100MHz */

Macro to configure STMDIV at 133MHz target frequency.

Definition at line 831 of file IfxScu_cfg.h.

#define IFXSCU_CFG_STMDIV_160MHZ   (IFXSCU_CFG_MAXDIV_160MHZ * 2) /*Max: 100MHz */

Macro to configure STMDIV at 160MHz target frequency.

Definition at line 836 of file IfxScu_cfg.h.

#define IFXSCU_CFG_STMDIV_200MHZ   (IFXSCU_CFG_MAXDIV_200MHZ * 2) /*Max: 100MHz */

Macro to configure STMDIV at 200MHz target frequency.

Definition at line 841 of file IfxScu_cfg.h.

#define IFXSCU_CFG_STMDIV_240MHZ   (IFXSCU_CFG_MAXDIV_240MHZ * 3) /*Max: 100MHz */

Macro to configure STMDIV at 240MHz target frequency.

Definition at line 846 of file IfxScu_cfg.h.

#define IFXSCU_CFG_STMDIV_300MHZ   (IFXSCU_CFG_MAXDIV_300MHZ * 3) /*Max: 100MHz */

Macro to configure STMDIV at 300MHz target frequency.

Definition at line 851 of file IfxScu_cfg.h.

#define IFXSCU_CFG_STMDIV_80MHZ   (IFXSCU_CFG_MAXDIV_80MHZ) /*Max: 100MHz */

Macro to configure STMDIV at 80MHz target frequency.

Definition at line 826 of file IfxScu_cfg.h.

#define IFXSCU_CFG_XTAL_FREQ   20MHZ

Definition at line 1385 of file IfxScu_cfg.h.

#define IFXSCU_EVR_OSC_FREQUENCY   (100000000.0)

Definition at line 47 of file IfxScu_cfg.h.

Referenced by IfxScuCcu_getEvrFrequency(), and IfxScuCcu_getOscFrequency().

#define IFXSCU_PLL_FREERUNNING_FREQUENCY   (100000000.0)

Definition at line 51 of file IfxScu_cfg.h.

#define IFXSCU_VCO_BASE_FREQUENCY   (100000000.0)

Enumeration Type Documentation

Clock selection

Enumerator
IfxScu_CCUCON0_CLKSEL_fBack 
IfxScu_CCUCON0_CLKSEL_fPll 

Definition at line 1414 of file IfxScu_cfg.h.

Input selection for PLL and PLL ERAY

Enumerator
IfxScu_CCUCON1_INSEL_fOsc1 
IfxScu_CCUCON1_INSEL_fOsc0 

Definition at line 1421 of file IfxScu_cfg.h.

Enumerator
IfxScu_PMCSR_REQSLP_Run 
IfxScu_PMCSR_REQSLP_Idle 
IfxScu_PMCSR_REQSLP_Sleep 
IfxScu_PMCSR_REQSLP_Stby 

Definition at line 1435 of file IfxScu_cfg.h.

Input frequency request control

Enumerator
IfxScu_WDTCON1_IR_divBy16384 
IfxScu_WDTCON1_IR_divBy256 
IfxScu_WDTCON1_IR_divBy64 

Definition at line 1428 of file IfxScu_cfg.h.