iLLD_TC27xC
1.0
IfxCpu_Irq.h
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/**
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* \file IfxCpu_Irq.h
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* \brief This file contains the APIs for Interrupt related functions.
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*
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*
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* \version iLLD_0_1_0_10
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* \copyright Copyright (c) 2012 Infineon Technologies AG. All rights reserved.
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*
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*
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* IMPORTANT NOTICE
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*
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*
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* Infineon Technologies AG (Infineon) is supplying this file for use
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* exclusively with Infineon's microcontroller products. This file can be freely
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* distributed within development tools that are supporting such microcontroller
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* products.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
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* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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*
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* \defgroup IfxLld_Cpu_Irq Interrupt Functions
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* \ingroup IfxLld_Cpu
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*
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* \defgroup IfxLld_Cpu_Irq_Usage How to define Interrupts?
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* \ingroup IfxLld_Cpu_Irq
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*
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*/
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#ifndef IFXCPU_IRQ_H_
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#define IFXCPU_IRQ_H_
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/*******************************************************************************
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** Includes **
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*******************************************************************************/
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#include "Ifx_Cfg.h"
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#include "
Cpu/Std/Ifx_Types.h
"
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/*******************************************************************************
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** Type definitions **
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*******************************************************************************/
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/*******************************************************************************
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** Global Exported variables/constants **
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*******************************************************************************/
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/*******************************************************************************
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** Global Exported macros/inlines/function ptototypes **
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*******************************************************************************/
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#if defined(IFX_USE_SW_MANAGED_INT)
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/** \addtogroup IfxLld_Cpu_Irq_Usage
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* \{ */
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/** \brief API for Interrupt handler install for SW Managed interrupts.
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* This API installs the isr to SW interrupt vector.
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* This must be used only when IFX_USE_SW_MANAGED_INT is defined in Ifx_Cfg.h
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*
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* \param isrFuncPointer pointer to ISR function.
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* \param serviceReqPrioNumber ISR priority.
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*/
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IFX_EXTERN
void
IfxCpu_Irq_installInterruptHandler(
void
*isrFuncPointer,
uint32
serviceReqPrioNumber);
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IFX_INLINE
void
interruptHandlerInstall(
uint32
srpn,
uint32
addr)
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{
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IfxCpu_Irq_installInterruptHandler((
void
*)addr, srpn);
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}
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/** \} */
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#endif
/*defined(IFX_USE_SW_MANAGED_INT) */
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/*Documentation */
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/** \addtogroup IfxLld_Cpu_Irq_Usage
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* \{
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*
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* This page describes how to use interrupts with application framework.\n
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*
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* \section IfxLld_Cpu_Irq_Terminology Interrupts Terminology:
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* \subsection IfxLld_Cpu_Irq_HWManaged Hardware Managed Interrupt Mechanism.
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* Hardware managed interrupts have static interrupt vector which are defined for each priority separately.
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* These vectors have jump instruction to the interrupt handler.
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*
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* Advantages:\n
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* This mechanism has less interrupt latency time.
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*
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* \subsection IfxLld_Cpu_Irq_SWManaged Software Managed Interrupt Mechanism.
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* Software managed interrupts have single interrupt vector statically defined at vector position 255.
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* This address is assigned to BIV during startup.\n
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* For Tricore, this vector position is important, because whenever an interrupt occurs, with whichever priority,
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* the execution control jumps to this vector position. The code at this vector position will:\n
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* 1) fetch the priority of the targetted interrupt.\n
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* 2) fetch the interrupt handler defined for this priority (this is done by Interrupt handler installation. Refer
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* \ref IfxLld_Cpu_Irq_Step4\n
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* 3) Then call the handler as notmal function call.
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*
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* Advantages:\n
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* This kind of mechanism is useful when project wants to change the handler for an interrupt during runtime.
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*
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* Disadvantages:\n
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* This mechanism has more interrupt latency time.
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*
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* of the interrupt and in tand jumps to the function
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*
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* \section IfxLld_Cpu_Irq_Steps Steps to use Interrupt Mechanism.
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* Dependency: Ifx_Compilers, Ifx_Cpu, Ifx_Src, IfxCpu_Irq\n
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* Following are the steps to use interrupt mechanism.
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*
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* \section IfxLld_Cpu_Irq_Step1 Step1: Define Interrupt priorities.
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* Define priorities of all interrupts with names corresponding to their functionality. It is recommended to define
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* such priority definitions in single header file, because it is easy to detect if ISR priorities are conflicting.
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* In Tricore architecture, two Isrs can't have same priority at same point of time.
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* \note These defines shall be defined without brackets surrounding priority number. (eg. #define PRIO (10) is not allowed)
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*
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* In a user defined file eg. Ifx_IntPrioDef.h, placed in folder: 0_AppSw/Tricore/DemoApp:
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* \code
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* //file: Ifx_IntPrioDef.h.
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* #define IFX_INTPRIO_FUNCT1 1
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* #define IFX_INTPRIO_FUNCT2 2
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* #define IFX_INTPRIO_FUNCT3 5
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* #define IFX_INTPRIO_STM0 8
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* #define IFX_INTPRIO_ADC_FUNC1 10
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* //etc.
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* \endcode
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*
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* \note !! IMPORTANT !!\n As explained above, the definition with closing bracket around priority number as,
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* #define IFX_INTPRIO_FUNCT1 (1) will cause compilation error. Because linker sections which are constructed
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* using such information will also get these brackets included. Which look like ".intvec_tc0_(1)" instead of the
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* expected ".intvec_tc0_1"\n
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* Linker sections' definitions are predefined statically in .lsl file,
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* for all 255 interrupts, with the format ".intvec_tc<vector number>_<interrupt priority>".
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*
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* \section IfxLld_Cpu_Irq_Step2 Step2: Define Type of interrupt mechanism.
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* \subsection IfxLld_Cpu_Irq_HWManaged_Usage To use Hardware Managed Interrupt Mechanism.
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* Refer \ref IfxLld_Cpu_Irq_HWManaged
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* If project is designed for hardware managed interrupts, this feature is enabled at the file Ifx_Cfg.h, at path:
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* 0_Src/0_AppSw/Config/Common/, as shown below. IFX_USE_SW_MANAGED_INT definition must be undefined (i.e. the
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* statement "#define IFX_USE_SW_MANAGED_INT" shall be commented as below).
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*
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* \code
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* //file: Ifx_Cfg.h
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*
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* //#define IFX_USE_SW_MANAGED_INT
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*
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* \endcode
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*
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* \subsection IfxLld_Cpu_Irq_SWManaged_Usage To use Software Managed Interrupt Mechanism.
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* Refer \ref IfxLld_Cpu_Irq_SWManaged
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* If project is designed for software managed interrupts, this feature is enabled at the file Ifx_Cfg.h, at path:
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* 0_Src/0_AppSw/Config/Common/, as shown below.
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* IFX_USE_SW_MANAGED_INT definition must be defined.
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*
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* \code
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* //file: Ifx_Cfg.h
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*
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* #define IFX_USE_SW_MANAGED_INT
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*
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* \endcode
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*
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* Software managed interrupts must also install the "Interrupt Handlers" Refer \ref IfxLld_Cpu_Irq_Step4
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*
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* \section IfxLld_Cpu_Irq_Step3 Step3: How to define an Interrupt Service routine?
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* Interrupt service routines or interrupt handlers are defined in driver specific files or application specific
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* files.
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*
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* \code
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* //file usercode1.c
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* #include "Compilers.h" // to get the compiler abstracted macros for interrupt definition
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* #include "Ifx_IntPrioDef.h" // to get the priority numbers
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*
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* //define an ISR with name Isr_Stm0 with priority defined by IFX_INTPRIO_STM0
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* IFX_INTERRUPT (Isr_Stm0, 0, IFX_INTPRIO_STM0)
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* {
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* //Isr code here
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* }
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* \endcode
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*
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* \code
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* //file usercode2.c
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* #include "Compilers.h" // to get the compiler abstracted macros for interrupt definition
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* #include "Ifx_IntPrioDef.h" // to get the priority numbers
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*
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* //define an ISR with name Isr_Adc_fun1 with priority defined by IFX_INTPRIO_ADC_FUNC1
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* IFX_INTERRUPT (Isr_Adc_fun1, 0, IFX_INTPRIO_ADC_FUNC1)
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* {
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* //Isr code here
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* }
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* \endcode
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*
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* \section IfxLld_Cpu_Irq_Step4 Step4: How to install Interrupt Service routine/handler?
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* This step is not required for HW managed interrupts.\n
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* Interrupt service routines or interrupt handlers are installed in driver specific files or application specific
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* files
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*
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* \code
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* //file usermain.c
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* #include "IfxCpu_Irq.h"
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* #include "Ifx_IntPrioDef.h" // to get the priority numbers
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*
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* void userfunction_init(void)
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* {
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* //code for user function init
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* // :
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* // :
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* IfxCpu_Irq_installInterruptHandler (Isr_Stm0, IFX_INTPRIO_STM0);
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* IfxCpu_Irq_installInterruptHandler (Isr_Adc_fun1, IFX_INTPRIO_ADC_FUNC1);
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*
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* // :
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* }
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*
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* \endcode
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*
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* \section IfxLld_Cpu_Irq_Step5 Step5: Managing the Service Request Node.
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* For the interrupt to get activated, interrupt triggers are needed. These triggers are activated by peripheral modules
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* and corresponding service request node must be\n
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* 1) Configured with correct priority number\n
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* 2) The request node must be enabled\n
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* Refer to \ref IfxLld_Src_Usage
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*/
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/** \} */
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#endif
/* IFXCPU_IRQ_H_ */
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