- r -
- RBS1
: IfxEth_AltRxDescr1_Bits
, IfxEth_RxDescr1_Bits
- RBS2
: IfxEth_RxDescr1_Bits
, IfxEth_AltRxDescr1_Bits
- RCH
: IfxEth_AltRxDescr1_Bits
, IfxEth_RxDescr1_Bits
- RDES0
: IfxEth_RxDescr
- RDES1
: IfxEth_RxDescr
- RDES2
: IfxEth_RxDescr
- RDES3
: IfxEth_RxDescr
- rdm
: IfxPsi5_Psi5_Frame
- rdr
: IfxPsi5s_Psi5s_ReceiveData
- rds
: IfxPsi5_Psi5_SerialMessage
, IfxPsi5s_Psi5s_ReceiveStatus
- RE
: IfxEth_RxDescr0_Bits
, IfxEth_AltRxDescr0_Bits
- read
: IfxStdIf_DPipe_
- readData
: IfxPsi5_Psi5_FrameData
, IfxPsi5s_Psi5s_ReceivedData
- readDataCrc
: IfxDma_Dma_ChannelConfig
- readerWaitx
: Ifx_Fifo_Shared
- receive
: Spi_ErrorChecks
- receiveBufferErrorConsideredForRSI
: IfxPsi5s_Psi5s_GlobalControlConfig
- receiveBufferOverflowFlag
: IfxPsi5s_Psi5s_ReceivedBits
- receiveBufferOverflowInterrupt
: IfxSent_Sent_Enable
- receiveBufferOverflowInterruptNode
: IfxSent_Sent_InterruptNodeControl
- receiveChannel
: IfxEray_Eray_MessageRAMConfig
- receiveControl
: IfxPsi5_Psi5_ChannelConfig
, IfxPsi5s_Psi5s_ChannelConfig
, IfxSent_Sent_ChannelConfig
- receiveDataInterrupt
: IfxSent_Sent_Enable
, IfxMsc_Msc_InterruptConfig
- receiveDataInterruptNode
: IfxMsc_Msc_InterruptConfig
, IfxSent_Sent_InterruptNodeControl
- receiveDataRegisterTimestamp
: IfxPsi5_Psi5_ReceiveControl
- receivedBits
: IfxPsi5s_Psi5s_ReceiveStatus
- receivedData
: IfxPsi5s_Psi5s_ReceiveData
- receiveIdEnable
: IfxAsclin_Lin
, IfxAsclin_Lin_Config
- receiveMemoryOverflowError
: IfxPsi5_Psi5_FrameData
- receiveMode
: IfxPsi5s_Psi5s_AscConfig
- receiveRequested
: IfxEray_Eray_ReceiveControl
- receiverOddParityEnabled
: IfxPsi5s_Psi5s_AscConfig
- receiveSuccessInterrupt
: IfxSent_Sent_Enable
- receiveSuccessInterruptNode
: IfxSent_Sent_InterruptNodeControl
- receiveWakeupIdleTime
: IfxEray_Eray_Prtc2Control
- receiveWakeupLowTime
: IfxEray_Eray_Prtc2Control
- receiveWakeupTestDuration
: IfxEray_Eray_Prtc1Control
- rectifier
: IfxDsadc_Dsadc_ChannelConfig
- refClk
: IfxEth_PortPins
- reference
: IfxVadc_Adc_ChannelConfig
- referenceSignal
: IfxIom_Iom_FpcConfig
- referenceSignalInverted
: IfxIom_Iom_LamConfig
- rejectedFrameId
: IfxEray_Eray_MessageRAMConfig
- reload
: IfxScuWdt_Config
- remaining
: SpiIf_Job
- requestId
: IfxScu_Req_In
- requestMode
: IfxDma_Dma_ChannelConfig
- requestSlotBackgroundScanEnabled
: IfxVadc_Adc_ArbiterConfig
- requestSlotPrio
: IfxVadc_Adc_BackgroundScanConfig
, IfxVadc_Adc_QueueConfig
, IfxVadc_Adc_ScanConfig
- requestSlotQueueEnabled
: IfxVadc_Adc_ArbiterConfig
- requestSlotScanEnabled
: IfxVadc_Adc_ArbiterConfig
- requestSlotStartMode
: IfxVadc_Adc_BackgroundScanConfig
, IfxVadc_Adc_QueueConfig
, IfxVadc_Adc_ScanConfig
- requestSource
: IfxDma_Dma_ChannelConfig
- RER
: IfxEth_AltRxDescr1_Bits
, IfxEth_RxDescr1_Bits
- reserved
: Spi_ErrorChecks
, IfxIom_Iom_EcmGlobalEventSelectionBits
- reservedBit
: IfxEray_ReceivedHeader
- resetSendCount
: IfxStdIf_DPipe_
- resolution
: IfxVadc_Adc_ClassConfig
- resource
: Ifx_GlobalResources_Item
- responseTimeout
: IfxAsclin_Lin_DataControl
, IfxAsclin_Lin_ErrorFlags
- responseTimeoutMode
: IfxAsclin_Lin_DataControl
- resultPriority
: IfxVadc_Adc_ChannelConfig
- resultreg
: IfxVadc_Adc_Channel
- resultRegister
: IfxVadc_Adc_ChannelConfig
- resultServProvider
: IfxVadc_Adc_ChannelConfig
- resultSrcNr
: IfxVadc_Adc_ChannelConfig
- resume
: TPwm_Functions
- resv
: IfxEth_AltTxDescr0_Bits
, IfxEth_AltRxDescr1_Bits
, IfxEth_RxDescr1_Bits
, IfxEth_TxDescr0_Bits
- resv1
: IfxEth_AltRxDescr1_Bits
, IfxEth_AltTxDescr1_Bits
, IfxEth_AltTxDescr0_Bits
- resv2
: IfxEth_AltTxDescr1_Bits
, IfxEth_RxDescr1_Bits
- rightAlignedStorage
: IfxVadc_Adc_ChannelConfig
- risingEdgeAtPeriod
: IfxStdIf_Timer_TrigConfig
- rts
: IfxAsclin_Asc_Pins
- rtsMode
: IfxAsclin_Asc_Pins
- run
: IfxStdIf_Timer_
- RWT
: IfxEth_AltRxDescr0_Bits
, IfxEth_RxDescr0_Bits
- rx
: IfxAsclin_Lin_Pins
, IfxPsi5s_Psi5s_Pins
, IfxAsclin_Asc_Pins
, SpiIf_Ch_
, IfxAsclin_Asc
, IfxAsclin_Spi_Pins
- rxBuffer
: IfxAsclin_Asc_Config
- rxBufferSize
: IfxAsclin_Asc_Config
- rxCount
: IfxEth
, SpiIf_
- rxd0
: IfxEth_PortPins
- rxd1
: IfxEth_PortPins
- rxDescr
: IfxEth
- rxDiff
: IfxEth
- rxDmaChannel
: IfxQspi_SpiSlave_Dma
, IfxQspi_SpiMaster_Dma
- rxDmaChannelId
: IfxQspi_SpiMaster_DmaConfig
, IfxQspi_SpiSlave_DmaConfig
, IfxQspi_SpiMaster_Dma
, IfxQspi_SpiSlave_Dma
- rxFifoInterruptLevel
: IfxAsclin_Asc_FifoControl
, IfxAsclin_Spi_FifoControl
- rxFifoOverflow
: IfxAsclin_Lin_ErrorFlags
, IfxAsclin_Spi_ErrorFlags
, IfxAsclin_Asc_ErrorFlags
- rxFifoThreshold
: IfxQspi_SpiSlave_Config
, IfxQspi_SpiMaster_Config
- rxFifoUnderflow
: IfxAsclin_Asc_ErrorFlags
, IfxAsclin_Spi_ErrorFlags
- rxHandler
: SpiIf_Ch_
- rxHeaderEnd
: IfxAsclin_Lin_AcknowledgementFlags
- rxIn
: IfxEray_Eray_NodeA
, IfxEray_Eray_NodeB
- rxInMode
: IfxEray_Eray_NodeB
, IfxEray_Eray_NodeA
- rxInterrupt
: IfxMultican_Can_MsgObjConfig
- rxJob
: IfxAsclin_Spi
, IfxQspi_SpiSlave
- rxMode
: IfxPsi5s_Psi5s_Pins
, IfxAsclin_Lin_Pins
, IfxAsclin_Spi_Pins
, IfxAsclin_Asc_Pins
- rxPin
: IfxMultican_Can_NodeConfig
- rxPinMode
: IfxMultican_Can_NodeConfig
- rxPriority
: IfxAsclin_Spi_InterruptConfig
, SpiIf_Config
, IfxAsclin_Asc_InterruptConfig
- rxResponseEnd
: IfxAsclin_Lin_AcknowledgementFlags
- rxSwFifoOverflow
: IfxAsclin_Asc