iLLD_TC27xC  1.0
IfxAsclin.h
Go to the documentation of this file.
1 /**
2  * \file IfxAsclin.h
3  * \brief ASCLIN basic functionality
4  * \ingroup IfxLld_Asclin
5  *
6  * \version iLLD_0_1_0_10
7  * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
8  *
9  *
10  * IMPORTANT NOTICE
11  *
12  *
13  * Infineon Technologies AG (Infineon) is supplying this file for use
14  * exclusively with Infineon's microcontroller products. This file can be freely
15  * distributed within development tools that are supporting such microcontroller
16  * products.
17  *
18  * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
19  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
20  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
21  * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
22  * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
23  *
24  * \defgroup IfxLld_Asclin ASCLIN
25  * \ingroup IfxLld
26  * \defgroup IfxLld_Asclin_Std Standard Driver
27  * \ingroup IfxLld_Asclin
28  * \defgroup IfxLld_Asclin_Std_Enumerations Enumerations
29  * \ingroup IfxLld_Asclin_Std
30  * \defgroup IfxLld_Asclin_Std_Operative Operative Functions
31  * \ingroup IfxLld_Asclin_Std
32  * \defgroup IfxLld_Asclin_Std_Utility Utility Functions
33  * \ingroup IfxLld_Asclin_Std
34  * \defgroup IfxLld_Asclin_Std_Configuration Configuration Functions
35  * \ingroup IfxLld_Asclin_Std
36  * \defgroup IfxLld_Asclin_Std_External External Functions
37  * \ingroup IfxLld_Asclin_Std
38  * \defgroup IfxLld_Asclin_Std_IO IO Pin Configuration Functions
39  * \ingroup IfxLld_Asclin_Std
40  */
41 
42 #ifndef IFXASCLIN_H
43 #define IFXASCLIN_H 1
44 
45 /******************************************************************************/
46 /*----------------------------------Includes----------------------------------*/
47 /******************************************************************************/
48 
49 #include "_Impl/IfxAsclin_cfg.h"
50 
51 /******************************************************************************/
52 /*--------------------------------Enumerations--------------------------------*/
53 /******************************************************************************/
54 
55 /** \addtogroup IfxLld_Asclin_Std_Enumerations
56  * \{ */
57 /** \brief Defines if the classic or the enhanced checksum will be calculated by the checksum block.\n
58  * Definition in Ifx_ASCLIN.DATCON.B.CSM
59  */
60 typedef enum
61 {
62  IfxAsclin_Checksum_classic = 0, /**< \brief classic checksum */
63  IfxAsclin_Checksum_enhanced = 1 /**< \brief enhanced checksum */
65 
66 /** \brief Defines if the received checksum byte is written into the RXFifo or not.\n
67  * Definition in Ifx_ASCLIN.LIN.CON.B.CSI
68  */
69 typedef enum
70 {
71  IfxAsclin_ChecksumInjection_notWritten = 0, /**< \brief checksum byte is not written */
72  IfxAsclin_ChecksumInjection_written = 1 /**< \brief checksum byte is written */
74 
75 /** \brief CPOL defines the idle level of the clock signal in the SPI mode.\n
76  * Idle level is the level outside the data transmission time intervals.\n
77  * Definition in Ifx_ASCLIN.IOCR.B.CPOL
78  */
79 typedef enum
80 {
81  IfxAsclin_ClockPolarity_idleLow = 0, /**< \brief idle low */
82  IfxAsclin_ClockPolarity_idleHigh = 1 /**< \brief idle high */
84 
85 /** \brief Selection of clock source\n
86  * Definition in Ifx_ASCLIN.CSR.B.CLKSEL
87  */
88 typedef enum
89 {
90  IfxAsclin_ClockSource_noClock = 0, /**< \brief no clock will be supplied */
91  IfxAsclin_ClockSource_kernelClock = 1, /**< \brief f clc will be supplied */
92  IfxAsclin_ClockSource_oscillatorClock = 2, /**< \brief XTAL oscillator clock foso0 will be supplied */
93  IfxAsclin_ClockSource_flexRayClock = 4, /**< \brief f eray will be supplied */
94  IfxAsclin_ClockSource_ascFastClock = 8, /**< \brief f asclinf wiil be supplied */
95  IfxAsclin_ClockSource_ascSlowClock = 16, /**< \brief f asclins will be supplied */
97 
98 /** \brief CTS input pin selection\n
99  * Definition in Ifx_ASCLIN.IOCR.B.CTS
100  */
101 typedef enum
102 {
103  IfxAsclin_CtsInputSelect_0, /**< \brief CTS input pin 0 */
104  IfxAsclin_CtsInputSelect_1, /**< \brief CTS input pin 1 */
105  IfxAsclin_CtsInputSelect_2, /**< \brief CTS input pin 2 */
106  IfxAsclin_CtsInputSelect_3, /**< \brief CTS input pin 3 */
108 
109 /** \brief Number of bits per transfer\n
110  * Definition in Ifx_ASCLIN.FRAMECON.B.DATALEN
111  */
112 typedef enum
113 {
114  IfxAsclin_DataLength_1 = 0, /**< \brief number of bits per transfer 0 */
115  IfxAsclin_DataLength_2, /**< \brief number of bits per transfer 1 */
116  IfxAsclin_DataLength_3, /**< \brief number of bits per transfer 2 */
117  IfxAsclin_DataLength_4, /**< \brief number of bits per transfer 3 */
118  IfxAsclin_DataLength_5, /**< \brief number of bits per transfer 4 */
119  IfxAsclin_DataLength_6, /**< \brief number of bits per transfer 5 */
120  IfxAsclin_DataLength_7, /**< \brief number of bits per transfer 6 */
121  IfxAsclin_DataLength_8, /**< \brief number of bits per transfer 7 */
122  IfxAsclin_DataLength_9, /**< \brief number of bits per transfer 8 */
123  IfxAsclin_DataLength_10, /**< \brief number of bits per transfer 9 */
124  IfxAsclin_DataLength_11, /**< \brief number of bits per transfer 10 */
125  IfxAsclin_DataLength_12, /**< \brief number of bits per transfer 11 */
126  IfxAsclin_DataLength_13, /**< \brief number of bits per transfer 12 */
127  IfxAsclin_DataLength_14, /**< \brief number of bits per transfer 13 */
128  IfxAsclin_DataLength_15, /**< \brief number of bits per transfer 14 */
129  IfxAsclin_DataLength_16, /**< \brief number of bits per transfer 15 */
131 
132 /** \brief Defines the basic operating mode of the module. Changing the mode must be done by switching first to initialize mode, and then to the other mode.\n
133  * Definition in Ifx_ASCLIN.FRAMECON.B.MODE
134  */
135 typedef enum
136 {
137  IfxAsclin_FrameMode_initialise = 0, /**< \brief initialise mode */
138  IfxAsclin_FrameMode_asc = 1, /**< \brief asc mode */
139  IfxAsclin_FrameMode_spi = 2, /**< \brief spi mode */
140  IfxAsclin_FrameMode_lin = 3 /**< \brief lin mode */
142 
143 /** \brief Defines if LIN frame shall consist of a header and response or of a header only.\n
144  * Definition in Ifx_ASCLIN.DATCON.B.HO
145  */
146 typedef enum
147 {
148  IfxAsclin_HeaderResponseSelect_headerAndResponse = 0, /**< \brief header and response expected */
149  IfxAsclin_HeaderResponseSelect_headerOnly = 1 /**< \brief header only expected */
151 
152 /** \brief Defines the duration of the IDLE delay in bit times.\n
153  * SPI mode: this is the idle time between the frames.\n
154  * ASC and LIN mode: this is the pause inserted between transmission of bytes.\n
155  * Definition in Ifx_ASCLIN.FRAMECON.B.IDLE
156  */
157 typedef enum
158 {
159  IfxAsclin_IdleDelay_0, /**< \brief idle delay in 0 bit times */
160  IfxAsclin_IdleDelay_1, /**< \brief idle delay in 1 bit times */
161  IfxAsclin_IdleDelay_2, /**< \brief idle delay in 2 bit times */
162  IfxAsclin_IdleDelay_3, /**< \brief idle delay in 3 bit times */
163  IfxAsclin_IdleDelay_4, /**< \brief idle delay in 4 bit times */
164  IfxAsclin_IdleDelay_5, /**< \brief idle delay in 5 bit times */
165  IfxAsclin_IdleDelay_6, /**< \brief idle delay in 6 bit times */
166  IfxAsclin_IdleDelay_7, /**< \brief idle delay in 7 bit times */
168 
169 /** \brief Defines the leading delay in bit times in SPI mode. ASC mode: not applicable.\n
170  * LIN mode: delay between the end of the break and the start of the sync character.\n
171  * Definition in Ifx_ASCLIN.FRAMECON.B.LEAD
172  */
173 typedef enum
174 {
175  IfxAsclin_LeadDelay_0, /**< \brief lead delay in 0 bit times */
176  IfxAsclin_LeadDelay_1, /**< \brief lead delay in 1 bit times */
177  IfxAsclin_LeadDelay_2, /**< \brief lead delay in 2 bit times */
178  IfxAsclin_LeadDelay_3, /**< \brief lead delay in 3 bit times */
179  IfxAsclin_LeadDelay_4, /**< \brief lead delay in 4 bit times */
180  IfxAsclin_LeadDelay_5, /**< \brief lead delay in 5 bit times */
181  IfxAsclin_LeadDelay_6, /**< \brief lead delay in 6 bit times */
182  IfxAsclin_LeadDelay_7, /**< \brief lead delay in 7 bit times */
184 
185 /** \brief Configures if the module in LIN mode operates as master or slave\n
186  * Definition in Ifx_ASCLIN.LIN.CON.B.MS
187  */
188 typedef enum
189 {
190  IfxAsclin_LinMode_slave = 0, /**< \brief operates in slave mode */
191  IfxAsclin_LinMode_master = 1 /**< \brief operates in master mode */
193 
194 /** \brief Defines the timeout threshold of RESPOSE bit is for LIN response timeout or LIN frame timeout.\n
195  * Definition in Ifx_ASCLIN.DATCON.B.RM
196  */
197 typedef enum
198 {
199  IfxAsclin_LinResponseTimeoutMode_frameTimeout = 0, /**< \brief timeout threshold is for frame */
200  IfxAsclin_LinResponseTimeoutMode_responseTimeout = 1 /**< \brief timeout threshold is for reponse */
202 
203 /** \brief Defines the bit length in ticks in the range of 1 to 16. The lengths of 1 to 3 are not allowed\n
204  * Definition in Ifx_ASCLIN.BITCON.B.OVERSAMPLING
205  */
206 typedef enum
207 {
208  IfxAsclin_OversamplingFactor_4 = 3, /**< \brief oversampling factor 4 */
209  IfxAsclin_OversamplingFactor_5 = 4, /**< \brief oversampling factor 5 */
210  IfxAsclin_OversamplingFactor_6 = 5, /**< \brief oversampling factor 6 */
211  IfxAsclin_OversamplingFactor_7 = 6, /**< \brief oversampling factor 7 */
212  IfxAsclin_OversamplingFactor_8 = 7, /**< \brief oversampling factor 8 */
213  IfxAsclin_OversamplingFactor_9 = 8, /**< \brief oversampling factor 9 */
214  IfxAsclin_OversamplingFactor_10 = 9, /**< \brief oversampling factor 10 */
215  IfxAsclin_OversamplingFactor_11 = 10, /**< \brief oversampling factor 11 */
216  IfxAsclin_OversamplingFactor_12 = 11, /**< \brief oversampling factor 12 */
217  IfxAsclin_OversamplingFactor_13 = 12, /**< \brief oversampling factor 13 */
218  IfxAsclin_OversamplingFactor_14 = 13, /**< \brief oversampling factor 14 */
219  IfxAsclin_OversamplingFactor_15 = 14, /**< \brief oversampling factor 15 */
220  IfxAsclin_OversamplingFactor_16 = 15 /**< \brief oversampling factor 16 */
222 
223 /** \brief Type of parity bit attached to data bits\n
224  * Definition in Ifx_ASCLIN.FRAMECON.B.ODD
225  */
226 typedef enum
227 {
228  IfxAsclin_ParityType_even = 0, /**< \brief even parity */
229  IfxAsclin_ParityType_odd = 1 /**< \brief odd parity */
231 
232 /** \brief Receive buffer mode\n
233  * Definition in Ifx_ASCLIN.RXFIFOCON.B.BUF
234  */
235 typedef enum
236 {
237  IfxAsclin_ReceiveBufferMode_rxFifo = 0, /**< \brief RxFIFO mode */
238  IfxAsclin_ReceiveBufferMode_rxBuffer = 1 /**< \brief single stage Rx buffer */
240 
241 /** \brief Polarity of the RTS and CTS signals\n
242  * Definition in Ifx_ASCLIN.IOCR.B.RCPOL
243  */
244 typedef enum
245 {
246  IfxAsclin_RtsCtsPolarity_activeHigh = 0, /**< \brief ready/clear are active-high */
247  IfxAsclin_RtsCtsPolarity_activeLow = 1 /**< \brief ready/clear are active-low */
249 
250 /** \brief Defines the filling level that triggers a drain (RX) interrupt or DMA access\n
251  * Definition in Ifx_ASCLIN.RXFIFOCON.B.INTLEVEL
252  */
253 typedef enum
254 {
255  IfxAsclin_RxFifoInterruptLevel_1, /**< \brief RX FIFO level 1 */
256  IfxAsclin_RxFifoInterruptLevel_2, /**< \brief RX FIFO level 2 */
257  IfxAsclin_RxFifoInterruptLevel_3, /**< \brief RX FIFO level 3 */
258  IfxAsclin_RxFifoInterruptLevel_4, /**< \brief RX FIFO level 4 */
259  IfxAsclin_RxFifoInterruptLevel_5, /**< \brief RX FIFO level 5 */
260  IfxAsclin_RxFifoInterruptLevel_6, /**< \brief RX FIFO level 6 */
261  IfxAsclin_RxFifoInterruptLevel_7, /**< \brief RX FIFO level 7 */
262  IfxAsclin_RxFifoInterruptLevel_8, /**< \brief RX FIFO level 8 */
263  IfxAsclin_RxFifoInterruptLevel_9, /**< \brief RX FIFO level 9 */
264  IfxAsclin_RxFifoInterruptLevel_10, /**< \brief RX FIFO level 10 */
265  IfxAsclin_RxFifoInterruptLevel_11, /**< \brief RX FIFO level 11 */
266  IfxAsclin_RxFifoInterruptLevel_12, /**< \brief RX FIFO level 12 */
267  IfxAsclin_RxFifoInterruptLevel_13, /**< \brief RX FIFO level 13 */
268  IfxAsclin_RxFifoInterruptLevel_14, /**< \brief RX FIFO level 14 */
269  IfxAsclin_RxFifoInterruptLevel_15, /**< \brief RX FIFO level 15 */
270  IfxAsclin_RxFifoInterruptLevel_16, /**< \brief RX FIFO level 16 */
272 
273 /** \brief Defines the number of bytes read from the Rx FIFO with one FPI bus read\n
274  * Definition in Ifx_ASCLIN.RXFIFOCON.B.OUTW
275  */
276 typedef enum
277 {
278  IfxAsclin_RxFifoOutletWidth_0, /**< \brief number of bytes 0 */
279  IfxAsclin_RxFifoOutletWidth_1, /**< \brief number of bytes 1 */
280  IfxAsclin_RxFifoOutletWidth_2, /**< \brief number of bytes 2 */
281  IfxAsclin_RxFifoOutletWidth_3, /**< \brief number of bytes 3 */
283 
284 /** \brief Alternate input selection for Rx signal.\n
285  * Definition in Ifx_ASCLIN.IOCR.B.ALTI
286  */
287 typedef enum
288 {
289  IfxAsclin_RxInputSelect_0, /**< \brief alternate input selection 0 */
290  IfxAsclin_RxInputSelect_1, /**< \brief alternate input selection 1 */
291  IfxAsclin_RxInputSelect_2, /**< \brief alternate input selection 2 */
292  IfxAsclin_RxInputSelect_3, /**< \brief alternate input selection 3 */
293  IfxAsclin_RxInputSelect_4, /**< \brief alternate input selection 4 */
294  IfxAsclin_RxInputSelect_5, /**< \brief alternate input selection 5 */
295  IfxAsclin_RxInputSelect_6, /**< \brief alternate input selection 6 */
296  IfxAsclin_RxInputSelect_7, /**< \brief alternate input selection 7 */
298 
299 /** \brief Sample point position\n
300  * Definition in Ifx_ASCLIN.BITCON.B.SAMPLEPOINT
301  */
302 typedef enum
303 {
304  IfxAsclin_SamplePointPosition_1 = 1, /**< \brief sample point position at 1 */
305  IfxAsclin_SamplePointPosition_2 = 2, /**< \brief sample point position at 2 */
306  IfxAsclin_SamplePointPosition_3 = 3, /**< \brief sample point position at 3 */
307  IfxAsclin_SamplePointPosition_4 = 4, /**< \brief sample point position at 4 */
308  IfxAsclin_SamplePointPosition_5 = 5, /**< \brief sample point position at 5 */
309  IfxAsclin_SamplePointPosition_6 = 6, /**< \brief sample point position at 6 */
310  IfxAsclin_SamplePointPosition_7 = 7, /**< \brief sample point position at 7 */
311  IfxAsclin_SamplePointPosition_8 = 8, /**< \brief sample point position at 8 */
312  IfxAsclin_SamplePointPosition_9 = 9, /**< \brief sample point position at 9 */
313  IfxAsclin_SamplePointPosition_10 = 10, /**< \brief sample point position at 10 */
314  IfxAsclin_SamplePointPosition_11 = 11, /**< \brief sample point position at 11 */
315  IfxAsclin_SamplePointPosition_12 = 12, /**< \brief sample point position at 12 */
316  IfxAsclin_SamplePointPosition_13 = 13, /**< \brief sample point position at 13 */
317  IfxAsclin_SamplePointPosition_14 = 14, /**< \brief sample point position at 14 */
318  IfxAsclin_SamplePointPosition_15 = 15 /**< \brief sample point position at 15 */
320 
321 /** \brief Number of samples per bit, sample mode/medianfilter\n
322  * Definition in Ifx_ASCLIN.BITCON.B.SM
323  */
324 typedef enum
325 {
326  IfxAsclin_SamplesPerBit_one = 0, /**< \brief one sample per bit */
327  IfxAsclin_SamplesPerBit_three = 1 /**< \brief three samples per bit */
329 
330 /** \brief SPI mode: defines the shift direction of the shift register.\n
331  * ASC and LIN mode: should be set to 0.\n
332  * Definition in Ifx_ASCLIN.FRAMECON.B.MSB
333  */
334 typedef enum
335 {
336  IfxAsclin_ShiftDirection_lsbFirst = 0, /**< \brief LSB first */
337  IfxAsclin_ShiftDirection_msbFirst = 1 /**< \brief MSB first */
339 
340 /** \brief Defines the idle level of the SLSO signal, which is the level.\n
341  * Outside the data transmission, leading and trailing time intervals.\n
342  * Definition in Ifx_ASCLIN.IOCR.B.SPOL
343  */
344 typedef enum
345 {
346  IfxAsclin_SlavePolarity_idleLow = 0, /**< \brief idle low */
347  IfxAsclin_SlavePolarity_idlehigh = 1 /**< \brief idle high */
349 
350 /** \brief Enable/disable the sensitivity of the module to sleep signal\n
351  * Definition in Ifx_ASCLIN.CLC.B.EDIS
352  */
353 typedef enum
354 {
355  IfxAsclin_SleepMode_enable = 0, /**< \brief enables */
356  IfxAsclin_SleepMode_disable = 1 /**< \brief disables */
358 
359 /** \brief Error status
360  */
361 typedef enum
362 {
363  IfxAsclin_Status_configurationError = 0, /**< \brief Configuration error */
364  IfxAsclin_Status_noError = 1 /**< \brief No error */
366 
367 /** \brief ASC and LIN mode: number of stop bits (0 is not allowed), SPI mode: trailing delay.\n
368  * Definition in Ifx_ASCLIN.FRAMECON.B.STOP
369  */
370 typedef enum
371 {
372  IfxAsclin_StopBit_0, /**< \brief number of stop bits 0 */
373  IfxAsclin_StopBit_1, /**< \brief number of stop bits 1 */
374  IfxAsclin_StopBit_2, /**< \brief number of stop bits 2 */
375  IfxAsclin_StopBit_3, /**< \brief number of stop bits 3 */
376  IfxAsclin_StopBit_4, /**< \brief number of stop bits 4 */
377  IfxAsclin_StopBit_5, /**< \brief number of stop bits 5 */
378  IfxAsclin_StopBit_6, /**< \brief number of stop bits 6 */
379  IfxAsclin_StopBit_7, /**< \brief number of stop bits 7 */
381 
382 /** \brief Defines the number of bytes written to the Tx FIFO with one FPI bus write\n
383  * Definition in Ifx_ASCLIN.TXFIFOCON.B.INW
384  */
385 typedef enum
386 {
387  IfxAsclin_TxFifoInletWidth_0, /**< \brief number of bytes 0 */
388  IfxAsclin_TxFifoInletWidth_1, /**< \brief number of bytes 1 */
389  IfxAsclin_TxFifoInletWidth_2, /**< \brief number of bytes 2 */
390  IfxAsclin_TxFifoInletWidth_3, /**< \brief number of bytes 3 */
392 
393 /** \brief Defines the filling level that triggers a refill (TX) interrupt or DMA access\n
394  * Definition in Ifx_ASCLIN.TXFIFOCON.B.INTLEVEL
395  */
396 typedef enum
397 {
398  IfxAsclin_TxFifoInterruptLevel_0, /**< \brief TX FIFO level 0 */
399  IfxAsclin_TxFifoInterruptLevel_1, /**< \brief TX FIFO level 1 */
400  IfxAsclin_TxFifoInterruptLevel_2, /**< \brief TX FIFO level 2 */
401  IfxAsclin_TxFifoInterruptLevel_3, /**< \brief TX FIFO level 3 */
402  IfxAsclin_TxFifoInterruptLevel_4, /**< \brief TX FIFO level 4 */
403  IfxAsclin_TxFifoInterruptLevel_5, /**< \brief TX FIFO level 5 */
404  IfxAsclin_TxFifoInterruptLevel_6, /**< \brief TX FIFO level 6 */
405  IfxAsclin_TxFifoInterruptLevel_7, /**< \brief TX FIFO level 7 */
406  IfxAsclin_TxFifoInterruptLevel_8, /**< \brief TX FIFO level 8 */
407  IfxAsclin_TxFifoInterruptLevel_9, /**< \brief TX FIFO level 9 */
408  IfxAsclin_TxFifoInterruptLevel_10, /**< \brief TX FIFO level 10 */
409  IfxAsclin_TxFifoInterruptLevel_11, /**< \brief TX FIFO level 11 */
410  IfxAsclin_TxFifoInterruptLevel_12, /**< \brief TX FIFO level 12 */
411  IfxAsclin_TxFifoInterruptLevel_13, /**< \brief TX FIFO level 13 */
412  IfxAsclin_TxFifoInterruptLevel_14, /**< \brief TX FIFO level 14 */
413  IfxAsclin_TxFifoInterruptLevel_15, /**< \brief TX FIFO level 15 */
415 
416 /** \} */
417 
418 /** \addtogroup IfxLld_Asclin_Std_Operative
419  * \{ */
420 
421 /******************************************************************************/
422 /*-------------------------Inline Function Prototypes-------------------------*/
423 /******************************************************************************/
424 
425 /** \brief clears all the flags
426  * \param asclin pointer to ASCLIN registers
427  * \return None
428  */
429 IFX_INLINE void IfxAsclin_clearAllFlags(Ifx_ASCLIN *asclin);
430 
431 /** \brief Clears the break detected flag
432  * \param asclin pointer to ASCLIN registers
433  * \return None
434  */
435 IFX_INLINE void IfxAsclin_clearBreakDetectedFlag(Ifx_ASCLIN *asclin);
436 
437 /** \brief Clears the collision detection error flag
438  * \param asclin pointer to ASCLIN registers
439  * \return None
440  */
442 
443 /** \brief Clears the falling edge detected flag
444  * \param asclin pointer to ASCLIN registers
445  * \return None
446  */
447 IFX_INLINE void IfxAsclin_clearFallingEdgeDetectedFlag(Ifx_ASCLIN *asclin);
448 
449 /** \brief Clears the frame error flag
450  * \param asclin pointer to ASCLIN registers
451  * \return None
452  */
453 IFX_INLINE void IfxAsclin_clearFrameErrorFlag(Ifx_ASCLIN *asclin);
454 
455 /** \brief Clears the header timeout flag
456  * \param asclin pointer to ASCLIN registers
457  * \return None
458  */
459 IFX_INLINE void IfxAsclin_clearHeaderTimeoutFlag(Ifx_ASCLIN *asclin);
460 
461 /** \brief Clears the kernel reset status
462  * \param asclin pointer to ASCLIN registers
463  * \return None
464  */
465 IFX_INLINE void IfxAsclin_clearKernelResetStatus(Ifx_ASCLIN *asclin);
466 
467 /** \brief Clears the auto baudrate detection error flag
468  * \param asclin pointer to ASCLIN registers
469  * \return None
470  */
472 
473 /** \brief Clears the LIN checksum error flag
474  * \param asclin pointer to ASCLIN registers
475  * \return None
476  */
477 IFX_INLINE void IfxAsclin_clearLinChecksumErrorFlag(Ifx_ASCLIN *asclin);
478 
479 /** \brief Clears the LIN parity error flag
480  * \param asclin pointer to ASCLIN registers
481  * \return None
482  */
483 IFX_INLINE void IfxAsclin_clearLinParityErrorFlag(Ifx_ASCLIN *asclin);
484 
485 /** \brief Clears the parity error flag
486  * \param asclin pointer to ASCLIN registers
487  * \return None
488  */
489 IFX_INLINE void IfxAsclin_clearParityErrorFlag(Ifx_ASCLIN *asclin);
490 
491 /** \brief Clears the raising edge detected flag
492  * \param asclin pointer to ASCLIN registers
493  * \return None
494  */
495 IFX_INLINE void IfxAsclin_clearRaisingEdgeDetectedFlag(Ifx_ASCLIN *asclin);
496 
497 /** \brief Clears the response timeout flag
498  * \param asclin pointer to ASCLIN registers
499  * \return None
500  */
501 IFX_INLINE void IfxAsclin_clearResponseTimeoutFlag(Ifx_ASCLIN *asclin);
502 
503 /** \brief Clears the Rx FIFO level flag
504  * \param asclin pointer to ASCLIN registers
505  * \return None
506  */
507 IFX_INLINE void IfxAsclin_clearRxFifoFillLevelFlag(Ifx_ASCLIN *asclin);
508 
509 /** \brief Clears the Rx FIFO overflow flag
510  * \param asclin pointer to ASCLIN registers
511  * \return None
512  */
513 IFX_INLINE void IfxAsclin_clearRxFifoOverflowFlag(Ifx_ASCLIN *asclin);
514 
515 /** \brief Clears the Rx FIFO underflow flag
516  * \param asclin pointer to ASCLIN registers
517  * \return None
518  */
519 IFX_INLINE void IfxAsclin_clearRxFifoUnderflowFlag(Ifx_ASCLIN *asclin);
520 
521 /** \brief Clears the receive header end flag
522  * \param asclin pointer to ASCLIN registers
523  * \return None
524  */
525 IFX_INLINE void IfxAsclin_clearRxHeaderEndFlag(Ifx_ASCLIN *asclin);
526 
527 /** \brief Clears the receive response end flag
528  * \param asclin pointer to ASCLIN registers
529  * \return None
530  */
531 IFX_INLINE void IfxAsclin_clearRxResponseEndFlag(Ifx_ASCLIN *asclin);
532 
533 /** \brief Clears the transmission pending flag
534  * \param asclin pointer to ASCLIN registers
535  * \return None
536  */
538 
539 /** \brief Clears the Tx FIFO level flag
540  * \param asclin pointer to ASCLIN registers
541  * \return None
542  */
543 IFX_INLINE void IfxAsclin_clearTxFifoFillLevelFlag(Ifx_ASCLIN *asclin);
544 
545 /** \brief Clears the Tx FIFO overflow flag
546  * \param asclin pointer to ASCLIN registers
547  * \return None
548  */
549 IFX_INLINE void IfxAsclin_clearTxFifoOverflowFlag(Ifx_ASCLIN *asclin);
550 
551 /** \brief Clears the transmit header end flag
552  * \param asclin pointer to ASCLIN registers
553  * \return None
554  */
555 IFX_INLINE void IfxAsclin_clearTxHeaderEndFlag(Ifx_ASCLIN *asclin);
556 
557 /** \brief Clears the transmit response end flag
558  * \param asclin pointer to ASCLIN registers
559  * \return None
560  */
561 IFX_INLINE void IfxAsclin_clearTxResponseEndFlag(Ifx_ASCLIN *asclin);
562 
563 /** \brief Flushes (empties) the Rx FIFO
564  * \param asclin pointer to ASCLIN registers
565  * \return None
566  */
567 IFX_INLINE void IfxAsclin_flushRxFifo(Ifx_ASCLIN *asclin);
568 
569 /** \brief Flushes (empties) the Tx FIFO
570  * \param asclin pointer to ASCLIN registers
571  * \return None
572  */
573 IFX_INLINE void IfxAsclin_flushTxFifo(Ifx_ASCLIN *asclin);
574 
575 /** \brief Sets the baudrate detection's lower limit
576  * \param asclin pointer to ASCLIN registers
577  * \param limit value of the lower limit
578  * \return None
579  */
580 IFX_INLINE void IfxAsclin_setBrdLowerlimt(Ifx_ASCLIN *asclin, uint8 limit);
581 
582 /** \brief Sets the baudrate detection's upper limit
583  * \param asclin pointer to ASCLIN registers
584  * \param limit value of the upper limit
585  * \return None
586  */
587 IFX_INLINE void IfxAsclin_setBrdUpperlimt(Ifx_ASCLIN *asclin, uint8 limit);
588 
589 /** \brief Sets the checksum injection
590  * \param asclin pointer to ASCLIN registers
591  * \param csi checksum injection selection (not written / written)
592  * \return None
593  */
595 
596 /** \brief Sets the checksum mode
597  * \param asclin pointer to ASCLIN registers
598  * \param mode checksum mode selection (classic / enhanced)
599  * \return None
600  */
601 IFX_INLINE void IfxAsclin_setChecksumMode(Ifx_ASCLIN *asclin, IfxAsclin_Checksum mode);
602 
603 /** \brief Sets the data length (number of bits per transfer)
604  * \param asclin pointer to ASCLIN registers
605  * \param length data length selection
606  * \return None
607  */
608 IFX_INLINE void IfxAsclin_setDataLength(Ifx_ASCLIN *asclin, IfxAsclin_DataLength length);
609 
610 /** \brief Sets the denominator of the fractional divider
611  * \param asclin pointer to ASCLIN registers
612  * \param denominator value of the denominator
613  * \return None
614  */
615 IFX_INLINE void IfxAsclin_setDenominator(Ifx_ASCLIN *asclin, uint16 denominator);
616 
617 /** \brief Sets the disable module request
618  * \param asclin pointer to ASCLIN registers
619  * \return None
620  */
621 IFX_INLINE void IfxAsclin_setDisableModuleRequest(Ifx_ASCLIN *asclin);
622 
623 /** \brief Sets the enable module request
624  * \param asclin pointer to ASCLIN registers
625  * \return None
626  */
627 IFX_INLINE void IfxAsclin_setEnableModuleRequest(Ifx_ASCLIN *asclin);
628 
629 /** \brief Sets digital glitch filter depth
630  * \param asclin pointer to ASCLIN registers
631  * \param depth digital glitch filter depth selection (1 to 63)
632  * \return None
633  */
634 IFX_INLINE void IfxAsclin_setFilterDepth(Ifx_ASCLIN *asclin, uint8 depth);
635 
636 /** \brief Sets the header response selection
637  * \param asclin pointer to ASCLIN registers
638  * \param type type of selection (header and response or header only)
639  * \return None
640  */
642 
643 /** \brief Sets the idle delay
644  * \param asclin pointer to ASCLIN registers
645  * \param delay idle delay selection
646  * \return None
647  */
648 IFX_INLINE void IfxAsclin_setIdleDelay(Ifx_ASCLIN *asclin, IfxAsclin_IdleDelay delay);
649 
650 /** \brief Sets the kernal reset of the KRST1
651  * \param asclin pointer to ASCLIN registers
652  * \return None
653  */
654 IFX_INLINE void IfxAsclin_setKernelResetOne(Ifx_ASCLIN *asclin);
655 
656 /** \brief Sets the kernel reset of the KRST0
657  * \param asclin pointer to ASCLIN registers
658  * \return None
659  */
660 IFX_INLINE void IfxAsclin_setKernelResetZero(Ifx_ASCLIN *asclin);
661 
662 /** \brief Sets the lead delay
663  * \param asclin pointer to ASCLIN registers
664  * \param delay lead delay selection
665  * \return None
666  */
667 IFX_INLINE void IfxAsclin_setLeadDelay(Ifx_ASCLIN *asclin, IfxAsclin_LeadDelay delay);
668 
669 /** \brief Sets the LIN break length
670  * \param asclin pointer to ASCLIN registers
671  * \param length value of the break length
672  * \return None
673  */
674 IFX_INLINE void IfxAsclin_setLinBreakLength(Ifx_ASCLIN *asclin, uint8 length);
675 
676 /** \brief Sets the LIN header timeout
677  * \param asclin pointer to ASCLIN registers
678  * \param timeout value of the header timeout
679  * \return None
680  */
681 IFX_INLINE void IfxAsclin_setLinHeaderTimeout(Ifx_ASCLIN *asclin, uint8 timeout);
682 
683 /** \brief Sets the LIN mode of operation
684  * \param asclin pointer to ASCLIN registers
685  * \param mode mode selection (slave / master)
686  * \return None
687  */
688 IFX_INLINE void IfxAsclin_setLinMode(Ifx_ASCLIN *asclin, IfxAsclin_LinMode mode);
689 
690 /** \brief Sets the LIN response timeout mode
691  * \param asclin pointer to ASCLIN registers
692  * \param mode LIN response timeout mode selection
693  * \return None
694  */
696 
697 /** \brief Sets the LIN response timeout threshold
698  * \param asclin pointer to ASCLIN registers
699  * \param threshold value of the tomeout threshold (1 to 256 bit times)
700  * \return None
701  */
702 IFX_INLINE void IfxAsclin_setLinResponseTimeoutThreshold(Ifx_ASCLIN *asclin, uint16 threshold);
703 
704 /** \brief Sets the numerator of the fractional divider
705  * \param asclin pointer to ASCLIN registers
706  * \param numerator value of the numerator
707  * \return None
708  */
709 IFX_INLINE void IfxAsclin_setNumerator(Ifx_ASCLIN *asclin, uint16 numerator);
710 
711 /** \brief Sets the division ratio of the baudrate post divider
712  * \param asclin pointer to ASCLIN registers
713  * \param ovsFactor value of oversampling factor
714  * \return None
715  */
716 IFX_INLINE void IfxAsclin_setOversampling(Ifx_ASCLIN *asclin, IfxAsclin_OversamplingFactor ovsFactor);
717 
718 /** \brief Sets the parity type
719  * \param asclin pointer to ASCLIN registers
720  * \param type parity type selction (even / odd)
721  * \return None
722  */
723 IFX_INLINE void IfxAsclin_setParityType(Ifx_ASCLIN *asclin, IfxAsclin_ParityType type);
724 
725 /** \brief Sets the division ratio of the predivider (prescaler)
726  * \param asclin pointer to ASCLIN registers
727  * \param prescaler value of prescaler
728  * \return None
729  */
730 IFX_INLINE void IfxAsclin_setPrescaler(Ifx_ASCLIN *asclin, uint16 prescaler);
731 
732 /** \brief Sets the receive buffer mode
733  * \param asclin pointer to ASCLIN registers
734  * \param mode receive buffer mode selection (Rx FIFO or single stage Rx buffer)
735  * \return None
736  */
738 
739 /** \brief Sets the Tx FIFO interrupt level
740  * \param asclin pointer to ASCLIN registers
741  * \param level interrupt level selection
742  * \return None
743  */
745 
746 /** \brief Sets the receive FIFO outlet width
747  * \param asclin pointer to ASCLIN registers
748  * \param width number of bytes read to the Rx FIFO with one FPI bus read
749  * \return None
750  */
752 
753 /** \brief Sets the sample mode (number of samples per bit / median filter)
754  * \param asclin pointer to ASCLIN registers
755  * \param medianFilter value of the median filter
756  * \return None
757  */
758 IFX_INLINE void IfxAsclin_setSampleMode(Ifx_ASCLIN *asclin, IfxAsclin_SamplesPerBit medianFilter);
759 
760 /** \brief Sets the sampling point position
761  * \param asclin pointer to ASCLIN registers
762  * \param spPosition sample point position selection
763  * \return None
764  */
766 
767 /** \brief Sets the shift direction
768  * \param asclin pointer to ASCLIN registers
769  * \param dir shift direction selection (LSB / MSB first)
770  * \return None
771  */
773 
774 /** \brief Sets the sensitivity of the module to sleep signal
775  * \param asclin pointer to ASCLIN registers
776  * \param mode mode selection (enable / disable)
777  * \return None
778  */
779 IFX_INLINE void IfxAsclin_setSleepMode(Ifx_ASCLIN *asclin, IfxAsclin_SleepMode mode);
780 
781 /** \brief Sets the number of stop bits
782  * \param asclin pointer to ASCLIN registers
783  * \param stopBit number of stop bits selection
784  * \return None
785  */
786 IFX_INLINE void IfxAsclin_setStopBit(Ifx_ASCLIN *asclin, IfxAsclin_StopBit stopBit);
787 
788 /** \brief Sets the transmit header request flag
789  * \param asclin pointer to ASCLIN registers
790  * \return None
791  */
792 IFX_INLINE void IfxAsclin_setTransmitHeaderRequestFlag(Ifx_ASCLIN *asclin);
793 
794 /** \brief Sets the transmit response request flag
795  * \param asclin pointer to ASCLIN registers
796  * \return None
797  */
799 
800 /** \brief Sets the transmission wake request flag
801  * \param asclin pointer to ASCLIN registers
802  * \return None
803  */
804 IFX_INLINE void IfxAsclin_setTransmitWakeRequestFlag(Ifx_ASCLIN *asclin);
805 
806 /** \brief Sets the transmit FIFO inlet width
807  * \param asclin pointer to ASCLIN registers
808  * \param width number of bytes written to the Tx FIFO with one FPI bus write
809  * \return None
810  */
812 
813 /** \brief Sets the Tx FIFO interrupt level
814  * \param asclin pointer to ASCLIN registers
815  * \param level interrupt level selection
816  * \return None
817  */
819 
820 /** \} */
821 
822 /** \addtogroup IfxLld_Asclin_Std_Utility
823  * \{ */
824 
825 /******************************************************************************/
826 /*-------------------------Inline Function Prototypes-------------------------*/
827 /******************************************************************************/
828 
829 /** \brief Returns the break detected flag status
830  * \param asclin pointer to ASCLIN registers
831  * \return break detected flag status
832  */
833 IFX_INLINE boolean IfxAsclin_getBreakDetectedFlagStatus(Ifx_ASCLIN *asclin);
834 
835 /** \brief Returns the clock source
836  * \param asclin pointer to ASCLIN registers
837  * \return clock source
838  */
839 IFX_INLINE uint8 IfxAsclin_getClockSource(Ifx_ASCLIN *asclin);
840 
841 /** \brief Returns the clock status
842  * \param asclin pointer to ASCLIN registers
843  * \return clock status (off / on)
844  */
845 IFX_INLINE boolean IfxAsclin_getClockStatus(Ifx_ASCLIN *asclin);
846 
847 /** \brief Returns the collision detection error flag status
848  * \param asclin pointer to ASCLIN registers
849  * \return collision detection error flag status
850  */
852 
853 /** \brief Returns the falling edge detected flag status
854  * \param asclin pointer to ASCLIN registers
855  * \return falling edge detected flag status
856  */
857 IFX_INLINE boolean IfxAsclin_getFallingEdgeDetectedFlagStatus(Ifx_ASCLIN *asclin);
858 
859 /** \brief Returns the frame error flag status
860  * \param asclin pointer to ASCLIN registers
861  * \return frame error flag status
862  */
863 IFX_INLINE boolean IfxAsclin_getFrameErrorFlagStatus(Ifx_ASCLIN *asclin);
864 
865 /** \brief Returns the header timeout flag status
866  * \param asclin pointer to ASCLIN registers
867  * \return header timeout flag status
868  */
869 IFX_INLINE boolean IfxAsclin_getHeaderTimeoutFlagStatus(Ifx_ASCLIN *asclin);
870 
871 /** \brief Returns the kernel reset status
872  * \param asclin pointer to ASCLIN registers
873  * \return kernel reset status
874  */
875 IFX_INLINE boolean IfxAsclin_getKernelResetStatus(Ifx_ASCLIN *asclin);
876 
877 /** \brief Returns the LIN auto baudrate detection error flag status
878  * \param asclin pointer to ASCLIN registers
879  * \return LIN auto baudrate detection error flag status
880  */
882 
883 /** \brief Returns the LIN checksum error flag status
884  * \param asclin pointer to ASCLIN registers
885  * \return LIN checksum error flag status
886  */
887 IFX_INLINE boolean IfxAsclin_getLinChecksumErrorFlagStatus(Ifx_ASCLIN *asclin);
888 
889 /** \brief Returns the LIN parity error flag status
890  * \param asclin pointer to ASCLIN registers
891  * \return LIN parity error flag status
892  */
893 IFX_INLINE boolean IfxAsclin_getLinParityErrorFlagStatus(Ifx_ASCLIN *asclin);
894 
895 /** \brief Returns the module status
896  * \param asclin pointer to ASCLIN registers
897  * \return module status (enabled / disabled)
898  */
899 IFX_INLINE boolean IfxAsclin_getModuleStatus(Ifx_ASCLIN *asclin);
900 
901 /** \brief Returns the parity error flag status
902  * \param asclin pointer to ASCLIN registers
903  * \return parity error flag status
904  */
905 IFX_INLINE boolean IfxAsclin_getParityErrorFlagStatus(Ifx_ASCLIN *asclin);
906 
907 /** \brief Returns the division ratio of the predivider (prescaler)
908  * \param asclin pointer to ASCLIN registers
909  * \return value of prescaler
910  */
911 IFX_INLINE uint16 IfxAsclin_getPrescaler(Ifx_ASCLIN *asclin);
912 
913 /** \brief Returns the raising edge detected flag status
914  * \param asclin pointer to ASCLIN registers
915  * \return raising edge detected flag status
916  */
917 IFX_INLINE boolean IfxAsclin_getRaisingEdgeDetectedFlagStatus(Ifx_ASCLIN *asclin);
918 
919 /** \brief Returns the received signal status
920  * \param asclin pointer to ASCLIN registers
921  * \return received signal status (0 is low & 1 is high)
922  */
923 IFX_INLINE boolean IfxAsclin_getReceiveSignalStatus(Ifx_ASCLIN *asclin);
924 
925 /** \brief Returns the response timeout flag status
926  * \param asclin pointer to ASCLIN registers
927  * \return response timeout flag status
928  */
929 IFX_INLINE boolean IfxAsclin_getResponseTimeoutFlagStatus(Ifx_ASCLIN *asclin);
930 
931 /** \brief Returns the current filling level of Tx FIFO
932  * \param asclin pointer to ASCLIN registers
933  * \return current filling level of Rx FIFO
934  */
935 IFX_INLINE uint8 IfxAsclin_getRxFifoFillLevel(Ifx_ASCLIN *asclin);
936 
937 /** \brief Returns the Rx FIFO level flag status
938  * \param asclin pointer to ASCLIN registers
939  * \return Rx FIFO level flag status
940  */
941 IFX_INLINE boolean IfxAsclin_getRxFifoFillLevelFlagStatus(Ifx_ASCLIN *asclin);
942 
943 /** \brief Returns the receive FIFO inlet width
944  * \param asclin pointer to ASCLIN registers
945  * \return number of bytes read to the Rx FIFO with one FPI bus read
946  */
948 
949 /** \brief Returns the Rx FIFO overflow flag status
950  * \param asclin pointer to ASCLIN registers
951  * \return Rx FIFO overflow flag status
952  */
953 IFX_INLINE boolean IfxAsclin_getRxFifoOverflowFlagStatus(Ifx_ASCLIN *asclin);
954 
955 /** \brief Returns the Rx FIFO underflow flag status
956  * \param asclin pointer to ASCLIN registers
957  * \return Rx FIFO underflow flag status
958  */
959 IFX_INLINE boolean IfxAsclin_getRxFifoUnderflowFlagStatus(Ifx_ASCLIN *asclin);
960 
961 /** \brief Returns the receive header end flag status
962  * \param asclin pointer to ASCLIN registers
963  * \return receive header end flag status
964  */
965 IFX_INLINE boolean IfxAsclin_getRxHeaderEndFlagStatus(Ifx_ASCLIN *asclin);
966 
967 /** \brief Returns the receive response end flag status
968  * \param asclin pointer to ASCLIN registers
969  * \return receive response end flag status
970  */
971 IFX_INLINE boolean IfxAsclin_getRxResponseEndFlagStatus(Ifx_ASCLIN *asclin);
972 
973 /** \brief Returns the transmission pending flag status
974  * \param asclin pointer to ASCLIN registers
975  * \return transmission pending flag status
976  */
977 IFX_INLINE boolean IfxAsclin_getTransmissionCompletedFlagStatus(Ifx_ASCLIN *asclin);
978 
979 /** \brief Returns the transmit signal status
980  * \param asclin pointer to ASCLIN registers
981  * \return transmit signal status (0 is low & 1 is high)
982  */
983 IFX_INLINE boolean IfxAsclin_getTransmitSignalStatus(Ifx_ASCLIN *asclin);
984 
985 /** \brief Returns the current filling level of Tx FIFO
986  * \param asclin pointer to ASCLIN registers
987  * \return current filling level of Tx FIFO
988  */
989 IFX_INLINE uint8 IfxAsclin_getTxFifoFillLevel(Ifx_ASCLIN *asclin);
990 
991 /** \brief Returns the Tx FIFO level flag status
992  * \param asclin pointer to ASCLIN registers
993  * \return Tx FIFO level flag status
994  */
995 IFX_INLINE boolean IfxAsclin_getTxFifoFillLevelFlagStatus(Ifx_ASCLIN *asclin);
996 
997 /** \brief Returns the transmit FIFO inlet width
998  * \param asclin pointer to ASCLIN registers
999  * \return number of bytes written to the Tx FIFO with one FPI bus write
1000  */
1001 IFX_INLINE uint8 IfxAsclin_getTxFifoInletWidth(Ifx_ASCLIN *asclin);
1002 
1003 /** \brief Returns the Tx FIFO overflow flag status
1004  * \param asclin pointer to ASCLIN registers
1005  * \return Tx FIFO overflow flag status
1006  */
1007 IFX_INLINE boolean IfxAsclin_getTxFifoOverflowFlagStatus(Ifx_ASCLIN *asclin);
1008 
1009 /** \brief Returns the transmit header end flag status
1010  * \param asclin pointer to ASCLIN registers
1011  * \return transmit header end flag status
1012  */
1013 IFX_INLINE boolean IfxAsclin_getTxHeaderEndFlagStatus(Ifx_ASCLIN *asclin);
1014 
1015 /** \brief Returns the transmit response end flag status
1016  * \param asclin pointer to ASCLIN registers
1017  * \return transmit response end flag status
1018  */
1019 IFX_INLINE boolean IfxAsclin_getTxResponseEndFlagStatus(Ifx_ASCLIN *asclin);
1020 
1021 /******************************************************************************/
1022 /*-------------------------Global Function Prototypes-------------------------*/
1023 /******************************************************************************/
1024 
1025 /** \brief Returns the ASCLIN module FA frequency in Hz
1026  * \param asclin pointer to ASCLIN registers
1027  * \return Returns the ASCLIN module FA frequency in Hz
1028  */
1029 IFX_EXTERN float32 IfxAsclin_getFaFrequency(Ifx_ASCLIN *asclin);
1030 
1031 /** \brief Returns the OVS frequency
1032  * \param asclin pointer to ASCLIN registers
1033  * \return Returns the ASCLIN module OVS frequency in Hz
1034  */
1035 IFX_EXTERN float32 IfxAsclin_getOvsFrequency(Ifx_ASCLIN *asclin);
1036 
1037 /** \brief Returns the PD frequency
1038  * \param asclin pointer to ASCLIN registers
1039  * \return Returns the ASCLIN module PD frequency in Hz
1040  */
1041 IFX_EXTERN float32 IfxAsclin_getPdFrequency(Ifx_ASCLIN *asclin);
1042 
1043 /** \brief Returns the SHIFT frequency
1044  * \param asclin pointer to ASCLIN registers
1045  * \return Returns the ASCLIN module SHIFT frequency in Hz
1046  */
1047 IFX_EXTERN float32 IfxAsclin_getShiftFrequency(Ifx_ASCLIN *asclin);
1048 
1049 /** \} */
1050 
1051 /** \addtogroup IfxLld_Asclin_Std_Configuration
1052  * \{ */
1053 
1054 /******************************************************************************/
1055 /*-------------------------Inline Function Prototypes-------------------------*/
1056 /******************************************************************************/
1057 
1058 /** \brief disables all flags
1059  * \param asclin pointer to ASCLIN registers
1060  * \return None
1061  */
1062 IFX_INLINE void IfxAsclin_disableAllFlags(Ifx_ASCLIN *asclin);
1063 
1064 /** \brief Enables/disables the auto baudrate detection
1065  * \param asclin pointer to ASCLIN registers
1066  * \param enable choice (enable / disable)
1067  * \return None
1068  */
1069 IFX_INLINE void IfxAsclin_enableAutoBaudrateDetection(Ifx_ASCLIN *asclin, boolean enable);
1070 
1071 /** \brief Enables/disables break detected flag
1072  * \param asclin pointer to ASCLIN registers
1073  * \param enable choice (enable / disable)
1074  * \return None
1075  */
1076 IFX_INLINE void IfxAsclin_enableBreakDetectedFlag(Ifx_ASCLIN *asclin, boolean enable);
1077 
1078 /** \brief Enables/disables the collision detection
1079  * \param asclin pointer to ASCLIN registers
1080  * \param enable choice (enable/disable)
1081  * \return None
1082  */
1083 IFX_INLINE void IfxAsclin_enableCollisionDetection(Ifx_ASCLIN *asclin, boolean enable);
1084 
1085 /** \brief Enables/disables LIN collision detection error flag
1086  * \param asclin pointer to ASCLIN registers
1087  * \param enable choice (enable / disable)
1088  * \return None
1089  */
1090 IFX_INLINE void IfxAsclin_enableCollisionDetectionErrorFlag(Ifx_ASCLIN *asclin, boolean enable);
1091 
1092 /** \brief Enables/disables CTS
1093  * \param asclin pointer to ASCLIN registers
1094  * \param enable choice (enable/disable)
1095  * \return None
1096  */
1097 IFX_INLINE void IfxAsclin_enableCts(Ifx_ASCLIN *asclin, boolean enable);
1098 
1099 /** \brief Enables/disables falling edge detected flag
1100  * \param asclin pointer to ASCLIN registers
1101  * \param enable choice (enable / disable)
1102  * \return None
1103  */
1104 IFX_INLINE void IfxAsclin_enableFallingEdgeDetectedFlag(Ifx_ASCLIN *asclin, boolean enable);
1105 
1106 /** \brief Enables/disables frame error flag
1107  * \param asclin pointer to ASCLIN registers
1108  * \param enable choice (enable / disable)
1109  * \return None
1110  */
1111 IFX_INLINE void IfxAsclin_enableFrameErrorFlag(Ifx_ASCLIN *asclin, boolean enable);
1112 
1113 /** \brief Enables/disables the hardware checksum
1114  * \param asclin pointer to ASCLIN registers
1115  * \param enable choice (enable / disable)
1116  * \return None
1117  */
1118 IFX_INLINE void IfxAsclin_enableHardwareChecksum(Ifx_ASCLIN *asclin, boolean enable);
1119 
1120 /** \brief Enables/disables header timeout flag
1121  * \param asclin pointer to ASCLIN registers
1122  * \param enable choice (enable / disable)
1123  * \return None
1124  */
1125 IFX_INLINE void IfxAsclin_enableHeaderTimeoutFlag(Ifx_ASCLIN *asclin, boolean enable);
1126 
1127 /** \brief Enables/disables LIN auto baudrate detection error flag
1128  * \param asclin pointer to ASCLIN registers
1129  * \param enable choice (enable / disable)
1130  * \return None
1131  */
1132 IFX_INLINE void IfxAsclin_enableLinAutoBaudDetectionErrorFlag(Ifx_ASCLIN *asclin, boolean enable);
1133 
1134 /** \brief Enables/disables LIN checksum error flag
1135  * \param asclin pointer to ASCLIN registers
1136  * \param enable choice (enable / disable)
1137  * \return None
1138  */
1139 IFX_INLINE void IfxAsclin_enableLinChecksumErrorFlag(Ifx_ASCLIN *asclin, boolean enable);
1140 
1141 /** \brief Enables/disables LIN parity error flag
1142  * \param asclin pointer to ASCLIN registers
1143  * \param enable choice (enable / disable)
1144  * \return None
1145  */
1146 IFX_INLINE void IfxAsclin_enableLinParityErrorFlag(Ifx_ASCLIN *asclin, boolean enable);
1147 
1148 /** \brief Enables/disables the loop back mode
1149  * \param asclin pointer to ASCLIN registers
1150  * \param enable choice (enable/disable)
1151  * \return None
1152  */
1153 IFX_INLINE void IfxAsclin_enableLoopBackMode(Ifx_ASCLIN *asclin, boolean enable);
1154 
1155 /** \brief Enables/disables the parity bit attachment to tha data bits
1156  * \param asclin pointer to ASCLIN registers
1157  * \param enable choice (enable/disable)
1158  * \return None
1159  */
1160 IFX_INLINE void IfxAsclin_enableParity(Ifx_ASCLIN *asclin, boolean enable);
1161 
1162 /** \brief Enables/disables parity error flag
1163  * \param asclin pointer to ASCLIN registers
1164  * \param enable choice (enable / disable)
1165  * \return None
1166  */
1167 IFX_INLINE void IfxAsclin_enableParityErrorFlag(Ifx_ASCLIN *asclin, boolean enable);
1168 
1169 /** \brief Enables/disables raising edge detected flag
1170  * \param asclin pointer to ASCLIN registers
1171  * \param enable choice (enable / disable)
1172  * \return None
1173  */
1174 IFX_INLINE void IfxAsclin_enableRaisingEdgeDetectedFlag(Ifx_ASCLIN *asclin, boolean enable);
1175 
1176 /** \brief Enables/disables response timeout flag
1177  * \param asclin pointer to ASCLIN registers
1178  * \param enable choice (enable / disable)
1179  * \return None
1180  */
1181 IFX_INLINE void IfxAsclin_enableResponseTimeoutFlag(Ifx_ASCLIN *asclin, boolean enable);
1182 
1183 /** \brief Enables/disables Rx FIFO level flag
1184  * \param asclin pointer to ASCLIN registers
1185  * \param enable choice (enable / disable)
1186  * \return None
1187  */
1188 IFX_INLINE void IfxAsclin_enableRxFifoFillLevelFlag(Ifx_ASCLIN *asclin, boolean enable);
1189 
1190 /** \brief Enables/disables the receive FIFO outlet to allow filling of Rx FIFO through shift register
1191  * \param asclin pointer to ASCLIN registers
1192  * \param enable choice (enable/disable)
1193  * \return None
1194  */
1195 IFX_INLINE void IfxAsclin_enableRxFifoInlet(Ifx_ASCLIN *asclin, boolean enable);
1196 
1197 /** \brief Enables/disables Rx FIFO overflow flag
1198  * \param asclin pointer to ASCLIN registers
1199  * \param enable choice (enable / disable)
1200  * \return None
1201  */
1202 IFX_INLINE void IfxAsclin_enableRxFifoOverflowFlag(Ifx_ASCLIN *asclin, boolean enable);
1203 
1204 /** \brief Enables/disables Rx FIFO underflow flag
1205  * \param asclin pointer to ASCLIN registers
1206  * \param enable choice (enable / disable)
1207  * \return None
1208  */
1209 IFX_INLINE void IfxAsclin_enableRxFifoUnderflowFlag(Ifx_ASCLIN *asclin, boolean enable);
1210 
1211 /** \brief Enables/disables receive header end flag
1212  * \param asclin pointer to ASCLIN registers
1213  * \param enable choice (enable / disable)
1214  * \return None
1215  */
1216 IFX_INLINE void IfxAsclin_enableRxHeaderEndFlag(Ifx_ASCLIN *asclin, boolean enable);
1217 
1218 /** \brief Enables/disables receive response end flag
1219  * \param asclin pointer to ASCLIN registers
1220  * \param enable choice (enable / disable)
1221  * \return None
1222  */
1223 IFX_INLINE void IfxAsclin_enableRxResponseEndFlag(Ifx_ASCLIN *asclin, boolean enable);
1224 
1225 /** \brief Enables/disables transmission completed flag
1226  * \param asclin pointer to ASCLIN registers
1227  * \param enable choice (enable / disable)
1228  * \return None
1229  */
1230 IFX_INLINE void IfxAsclin_enableTransmissionCompletedFlag(Ifx_ASCLIN *asclin, boolean enable);
1231 
1232 /** \brief Enables/disables Tx FIFO level flag
1233  * \param asclin pointer to ASCLIN registers
1234  * \param enable choice (enable / disable)
1235  * \return None
1236  */
1237 IFX_INLINE void IfxAsclin_enableTxFifoFillLevelFlag(Ifx_ASCLIN *asclin, boolean enable);
1238 
1239 /** \brief Enables/disables the transmit FIFO outlet to allow transmission
1240  * \param asclin pointer to ASCLIN registers
1241  * \param enable choice (enable/disable)
1242  * \return None
1243  */
1244 IFX_INLINE void IfxAsclin_enableTxFifoOutlet(Ifx_ASCLIN *asclin, boolean enable);
1245 
1246 /** \brief Enables/disables Tx FIFO overflow flag
1247  * \param asclin pointer to ASCLIN registers
1248  * \param enable choice (enable / disable)
1249  * \return None
1250  */
1251 IFX_INLINE void IfxAsclin_enableTxFifoOverflowFlag(Ifx_ASCLIN *asclin, boolean enable);
1252 
1253 /** \brief Enables/disables transmit header end flag
1254  * \param asclin pointer to ASCLIN registers
1255  * \param enable choice (enable / disable)
1256  * \return None
1257  */
1258 IFX_INLINE void IfxAsclin_enableTxHeaderEndFlag(Ifx_ASCLIN *asclin, boolean enable);
1259 
1260 /** \brief Enables/disables transmit response end flag
1261  * \param asclin pointer to ASCLIN registers
1262  * \param enable choice (enable / disable)
1263  * \return None
1264  */
1265 IFX_INLINE void IfxAsclin_enableTxResponseEndFlag(Ifx_ASCLIN *asclin, boolean enable);
1266 
1267 /** \brief Selects the clock polarity
1268  * \param asclin pointer to ASCLIN registers
1269  * \param cpol CPOL selection
1270  * \return None
1271  */
1272 IFX_INLINE void IfxAsclin_setClockPolarity(Ifx_ASCLIN *asclin, IfxAsclin_ClockPolarity cpol);
1273 
1274 /** \brief Selects the CTS input pin
1275  * \param asclin pointer to ASCLIN registers
1276  * \param ctsi CTS input pin selection
1277  * \return None
1278  */
1279 IFX_INLINE void IfxAsclin_setCtsInput(Ifx_ASCLIN *asclin, IfxAsclin_CtsInputSelect ctsi);
1280 
1281 /** \brief Selects the module's mode of operation
1282  * \param asclin pointer to ASCLIN registers
1283  * \param mode mode selction
1284  * \return None
1285  */
1286 IFX_INLINE void IfxAsclin_setFrameMode(Ifx_ASCLIN *asclin, IfxAsclin_FrameMode mode);
1287 
1288 /** \brief Selects the RTS/CTS polarity
1289  * \param asclin pointer to ASCLIN registers
1290  * \param rcpol RCPOL selection
1291  * \return None
1292  */
1293 IFX_INLINE void IfxAsclin_setRtsCtsPolarity(Ifx_ASCLIN *asclin, IfxAsclin_RtsCtsPolarity rcpol);
1294 
1295 /** \brief Selects the alternate input for Rx signal
1296  * \param asclin pointer to ASCLIN registers
1297  * \param alti alternate input selection of Rx signal
1298  * \return None
1299  */
1300 IFX_INLINE void IfxAsclin_setRxInput(Ifx_ASCLIN *asclin, IfxAsclin_RxInputSelect alti);
1301 
1302 /** \brief Selects the slave polarity
1303  * \param asclin pointer to ASCLIN registers
1304  * \param spol SPOL selection
1305  * \return None
1306  */
1307 IFX_INLINE void IfxAsclin_setSlavePolarity(Ifx_ASCLIN *asclin, IfxAsclin_SlavePolarity spol);
1308 
1309 /******************************************************************************/
1310 /*-------------------------Global Function Prototypes-------------------------*/
1311 /******************************************************************************/
1312 
1313 /** \brief Set the bit timing
1314  *
1315  * \note this function required FA source and the PD frequency to be set to their final values
1316  * \param asclin pointer to ASCLIN registers
1317  * \param baudrate Required baudrate
1318  * \param oversampling The oversampling factor
1319  * \param samplepoint The sample point position
1320  * \param medianFilter Number of samples per bit (median filter)
1321  * \return TRUE if configuration was successfull
1322  */
1323 IFX_EXTERN boolean IfxAsclin_setBitTiming(Ifx_ASCLIN *asclin, float32 baudrate, IfxAsclin_OversamplingFactor oversampling, IfxAsclin_SamplePointPosition samplepoint, IfxAsclin_SamplesPerBit medianFilter);
1324 
1325 /** \} */
1326 
1327 /** \addtogroup IfxLld_Asclin_Std_External
1328  * \{ */
1329 
1330 /******************************************************************************/
1331 /*-------------------------Global Function Prototypes-------------------------*/
1332 /******************************************************************************/
1333 
1334 /** \brief Enables the ASC error interrupt Flags
1335  * \param asclin pointer to ASCLIN registers
1336  * \param parEnable parity error
1337  * \param rfoEnable Rx FIFO overflow error
1338  * \return None
1339  */
1340 IFX_EXTERN void IfxAsclin_enableAscErrorFlags(Ifx_ASCLIN *asclin, boolean parEnable, boolean rfoEnable);
1341 
1342 /** \brief Enables the module
1343  * \param asclin pointer to ASCLIN registers
1344  * \return None
1345  */
1346 IFX_EXTERN void IfxAsclin_enableModule(Ifx_ASCLIN *asclin);
1347 
1348 /** \brief Returns the module Index
1349  * \param asclin pointer to ASCLIN registers
1350  * \return module index
1351  */
1352 IFX_EXTERN sint32 IfxAsclin_getIndex(Ifx_ASCLIN *asclin);
1353 
1354 /** \brief Returns the SRC pointer for ERR
1355  * \param asclin pointer to ASCLIN registers
1356  */
1357 IFX_EXTERN volatile Ifx_SRC_SRCR *IfxAsclin_getSrcPointerEr(Ifx_ASCLIN *asclin);
1358 
1359 /** \brief Returns the SRC pointer for Rx
1360  * \param asclin pointer to ASCLIN registers
1361  */
1362 IFX_EXTERN volatile Ifx_SRC_SRCR *IfxAsclin_getSrcPointerRx(Ifx_ASCLIN *asclin);
1363 
1364 /** \brief Returns the SRC pointer for Tx
1365  * \param asclin pointer to ASCLIN registers
1366  */
1367 IFX_EXTERN volatile Ifx_SRC_SRCR *IfxAsclin_getSrcPointerTx(Ifx_ASCLIN *asclin);
1368 
1369 /** \brief Reads data up to 16 bits
1370  * \param asclin pointer to ASCLIN registers
1371  * \param data Array where the read data shall be stored
1372  * \param count number of items to read
1373  * \return number of items that could not be read
1374  */
1375 IFX_EXTERN uint32 IfxAsclin_read16(Ifx_ASCLIN *asclin, uint16 *data, uint32 count);
1376 
1377 /** \brief Reads data up to 32 bits
1378  * \param asclin pointer to ASCLIN registers
1379  * \param data Array where the read data shall be stored
1380  * \param count number of items to read
1381  * \return number of items that could not be read
1382  */
1383 IFX_EXTERN uint32 IfxAsclin_read32(Ifx_ASCLIN *asclin, uint32 *data, uint32 count);
1384 
1385 /** \brief Reads data up to 8 bits
1386  * \param asclin pointer to ASCLIN registers
1387  * \param data Array where the read data shall be stored
1388  * \param count number of items to read
1389  * \return number of items that could not be read
1390  */
1391 IFX_EXTERN uint32 IfxAsclin_read8(Ifx_ASCLIN *asclin, uint8 *data, uint32 count);
1392 
1393 /** \brief Sets the baudrate bit fields
1394  * \param asclin pointer to ASCLIN registers
1395  * \param prescaler division ratio of the predivider
1396  * \param numerator numerator of the fractional divider
1397  * \param denominator denominator of the fractional divider
1398  * \param oversampling division ratio of the baudrate postdivider
1399  * \return None
1400  */
1401 IFX_EXTERN void IfxAsclin_setBaudrateBitFields(Ifx_ASCLIN *asclin, uint16 prescaler, uint16 numerator, uint16 denominator, IfxAsclin_OversamplingFactor oversampling);
1402 
1403 /** \brief Sets the clock source
1404  * \param asclin pointer to ASCLIN registers
1405  * \param clockSource clock source selection
1406  * \return None
1407  */
1408 IFX_EXTERN void IfxAsclin_setClockSource(Ifx_ASCLIN *asclin, IfxAsclin_ClockSource clockSource);
1409 
1410 /** \brief Writes data up to 16 bits
1411  * \param asclin pointer to ASCLIN registers
1412  * \param data Array of data to be send
1413  * \param count number of items to be send
1414  * \return the number of items that could not be send
1415  */
1416 IFX_EXTERN uint32 IfxAsclin_write16(Ifx_ASCLIN *asclin, uint16 *data, uint32 count);
1417 
1418 /** \brief Writes data up to 32 bits
1419  * \param asclin pointer to ASCLIN registers
1420  * \param data Array of data to be send
1421  * \param count number of items to be send
1422  * \return the number of items that could not be send
1423  */
1424 IFX_EXTERN uint32 IfxAsclin_write32(Ifx_ASCLIN *asclin, uint32 *data, uint32 count);
1425 
1426 /** \brief Writes data up to 8 bits
1427  * \param asclin pointer to ASCLIN registers
1428  * \param data Array of data to be send
1429  * \param count number of items to be send
1430  * \return the number of items that could not be send
1431  */
1432 IFX_EXTERN uint32 IfxAsclin_write8(Ifx_ASCLIN *asclin, uint8 *data, uint32 count);
1433 
1434 /** \} */
1435 
1436 /** \addtogroup IfxLld_Asclin_Std_IO
1437  * \{ */
1438 
1439 /******************************************************************************/
1440 /*-------------------------Inline Function Prototypes-------------------------*/
1441 /******************************************************************************/
1442 
1443 /** \brief Initializes a CTS input
1444  *
1445  * Attention: the kernel clock has to be disabled whenever the input multiplexer is changed.
1446  *
1447  * This can be done with IfxAsclin_setClockSource(asclinSFR, IfxAsclin_ClockSource_noClock);
1448  *
1449  * After the function call, the current clock can be enabled again.
1450  * \param cts the CTS Pin which should be configured
1451  * \param inputMode the pin input mode which should be configured
1452  * \return None
1453  */
1455 
1456 /** \brief Initializes a RTS output
1457  * \param rts the RTS Pin which should be configured
1458  * \param outputMode the pin output mode which should be configured
1459  * \param padDriver the pad driver mode which should be configured
1460  * \return None
1461  */
1463 
1464 /** \brief Initializes a RX input
1465  *
1466  * Attention: the kernel clock has to be disabled whenever the input multiplexer is changed.
1467  *
1468  * This can be done with IfxAsclin_setClockSource(asclinSFR, IfxAsclin_ClockSource_noClock);
1469  *
1470  * After the function call, the current clock can be enabled again.
1471  * \param rx the RX Pin which should be configured
1472  * \param inputMode the pin input mode which should be configured
1473  * \return None
1474  */
1476 
1477 /** \brief Initializes a SCLK output
1478  * \param sclk the SCLK Pin which should be configured
1479  * \param outputMode the pin output mode which should be configured
1480  * \param padDriver the pad driver mode which should be configured
1481  * \return None
1482  */
1484 
1485 /** \brief Initializes a SLSO output
1486  * \param slso the SLSO Pin which should be configured
1487  * \param outputMode the pin output mode which should be configured
1488  * \param padDriver the pad driver mode which should be configured
1489  * \return None
1490  */
1492 
1493 /** \brief Initializes a TX output
1494  * \param tx the TX Pin which should be configured
1495  * \param outputMode the pin output mode which should be configured
1496  * \param padDriver the pad driver mode which should be configured
1497  * \return None
1498  */
1500 
1501 /** \} */
1502 
1503 /******************************************************************************/
1504 /*-------------------------Inline Function Prototypes-------------------------*/
1505 /******************************************************************************/
1506 
1507 /**
1508  * \param asclin pointer to ASCLIN registers
1509  * \return returns the value of RxDATA register
1510  */
1511 IFX_INLINE uint32 IfxAsclin_readRxData(Ifx_ASCLIN *asclin);
1512 
1513 /**
1514  * \param asclin pointer to ASCLIN registers
1515  * \param data data to be written
1516  * \return None
1517  */
1518 IFX_INLINE void IfxAsclin_writeTxData(Ifx_ASCLIN *asclin, uint32 data);
1519 
1520 /******************************************************************************/
1521 /*---------------------Inline Function Implementations------------------------*/
1522 /******************************************************************************/
1523 
1524 IFX_INLINE void IfxAsclin_clearAllFlags(Ifx_ASCLIN *asclin)
1525 {
1526  asclin->FLAGSCLEAR.U = 0xFFFFFFFF;
1527 }
1528 
1529 
1531 {
1532  asclin->FLAGSCLEAR.B.BDC = 1;
1533 }
1534 
1535 
1537 {
1538  asclin->FLAGSCLEAR.B.CEC = 1;
1539 }
1540 
1541 
1543 {
1544  asclin->FLAGSCLEAR.B.FEDC = 1;
1545 }
1546 
1547 
1549 {
1550  asclin->FLAGSCLEAR.B.FEC = 1;
1551 }
1552 
1553 
1555 {
1556  asclin->FLAGSCLEAR.B.HTC = 1;
1557 }
1558 
1559 
1561 {
1562  asclin->KRSTCLR.B.CLR = 1;
1563 }
1564 
1565 
1567 {
1568  asclin->FLAGSCLEAR.B.LAC = 1;
1569 }
1570 
1571 
1573 {
1574  asclin->FLAGSCLEAR.B.LCC = 1;
1575 }
1576 
1577 
1579 {
1580  asclin->FLAGSCLEAR.B.LPC = 1;
1581 }
1582 
1583 
1585 {
1586  asclin->FLAGSCLEAR.B.PEC = 1;
1587 }
1588 
1589 
1591 {
1592  asclin->FLAGSCLEAR.B.REDC = 1;
1593 }
1594 
1595 
1597 {
1598  asclin->FLAGSCLEAR.B.RTC = 1;
1599 }
1600 
1601 
1603 {
1604  asclin->FLAGSCLEAR.B.RFLC = 1;
1605 }
1606 
1607 
1609 {
1610  asclin->FLAGSCLEAR.B.RFOC = 1;
1611 }
1612 
1613 
1615 {
1616  asclin->FLAGSCLEAR.B.RFUC = 1;
1617 }
1618 
1619 
1621 {
1622  asclin->FLAGSCLEAR.B.RHC = 1;
1623 }
1624 
1625 
1627 {
1628  asclin->FLAGSCLEAR.B.RRC = 1;
1629 }
1630 
1631 
1633 {
1634  asclin->FLAGSCLEAR.B.TCC = 1;
1635 }
1636 
1637 
1639 {
1640  asclin->FLAGSCLEAR.B.TFLC = 1;
1641 }
1642 
1643 
1645 {
1646  asclin->FLAGSCLEAR.B.TFOC = 1;
1647 }
1648 
1649 
1651 {
1652  asclin->FLAGSCLEAR.B.THC = 1;
1653 }
1654 
1655 
1657 {
1658  asclin->FLAGSCLEAR.B.TRC = 1;
1659 }
1660 
1661 
1662 IFX_INLINE void IfxAsclin_flushRxFifo(Ifx_ASCLIN *asclin)
1663 {
1664  asclin->RXFIFOCON.B.FLUSH = 1;
1665 }
1666 
1667 
1668 IFX_INLINE void IfxAsclin_flushTxFifo(Ifx_ASCLIN *asclin)
1669 {
1670  asclin->TXFIFOCON.B.FLUSH = 1;
1671 }
1672 
1673 
1674 IFX_INLINE void IfxAsclin_setBrdLowerlimt(Ifx_ASCLIN *asclin, uint8 limit)
1675 {
1676  asclin->BRD.B.LOWERLIMIT = limit;
1677 }
1678 
1679 
1680 IFX_INLINE void IfxAsclin_setBrdUpperlimt(Ifx_ASCLIN *asclin, uint8 limit)
1681 {
1682  asclin->BRD.B.UPPERLIMIT = limit;
1683 }
1684 
1685 
1687 {
1688  asclin->LIN.CON.B.CSI = csi;
1689 }
1690 
1691 
1693 {
1694  asclin->DATCON.B.CSM = mode;
1695 }
1696 
1697 
1699 {
1700  asclin->DATCON.B.DATLEN = length;
1701 }
1702 
1703 
1704 IFX_INLINE void IfxAsclin_setDenominator(Ifx_ASCLIN *asclin, uint16 denominator)
1705 {
1706  asclin->BRG.B.DENOMINATOR = denominator;
1707 }
1708 
1709 
1711 {
1712  asclin->CLC.B.DISR = 1;
1713 }
1714 
1715 
1717 {
1718  asclin->CLC.B.DISR = 0;
1719 }
1720 
1721 
1722 IFX_INLINE void IfxAsclin_setFilterDepth(Ifx_ASCLIN *asclin, uint8 depth)
1723 {
1724  asclin->IOCR.B.DEPTH = __minu(depth, 63);
1725 }
1726 
1727 
1729 {
1730  asclin->DATCON.B.HO = type;
1731 }
1732 
1733 
1735 {
1736  asclin->FRAMECON.B.IDLE = delay;
1737 }
1738 
1739 
1740 IFX_INLINE void IfxAsclin_setKernelResetOne(Ifx_ASCLIN *asclin)
1741 {
1742  asclin->KRST1.B.RST = 1;
1743 }
1744 
1745 
1747 {
1748  asclin->KRST0.B.RST = 1;
1749 }
1750 
1751 
1753 {
1754  asclin->FRAMECON.B.LEAD = delay;
1755 }
1756 
1757 
1758 IFX_INLINE void IfxAsclin_setLinBreakLength(Ifx_ASCLIN *asclin, uint8 length)
1759 {
1760  asclin->LIN.BTIMER.B.BREAK = length;
1761 }
1762 
1763 
1764 IFX_INLINE void IfxAsclin_setLinHeaderTimeout(Ifx_ASCLIN *asclin, uint8 timeout)
1765 {
1766  asclin->LIN.HTIMER.B.HEADER = timeout;
1767 }
1768 
1769 
1770 IFX_INLINE void IfxAsclin_setLinMode(Ifx_ASCLIN *asclin, IfxAsclin_LinMode mode)
1771 {
1772  asclin->LIN.CON.B.MS = mode;
1773 }
1774 
1775 
1777 {
1778  asclin->DATCON.B.RM = mode;
1779 }
1780 
1781 
1783 {
1784  asclin->DATCON.B.RESPONSE = __minu(threshold, 256);
1785 }
1786 
1787 
1788 IFX_INLINE void IfxAsclin_setNumerator(Ifx_ASCLIN *asclin, uint16 numerator)
1789 {
1790  asclin->BRG.B.NUMERATOR = numerator;
1791 }
1792 
1793 
1795 {
1796  asclin->BITCON.B.OVERSAMPLING = ovsFactor;
1797 }
1798 
1799 
1801 {
1802  asclin->FRAMECON.B.ODD = type;
1803 }
1804 
1805 
1806 IFX_INLINE void IfxAsclin_setPrescaler(Ifx_ASCLIN *asclin, uint16 prescaler)
1807 {
1808  asclin->BITCON.B.PRESCALER = prescaler - 1;
1809 }
1810 
1811 
1813 {
1814  asclin->RXFIFOCON.B.BUF = mode;
1815 }
1816 
1817 
1819 {
1820  asclin->RXFIFOCON.B.INTLEVEL = __minu(level, 15);
1821 }
1822 
1823 
1825 {
1826  asclin->RXFIFOCON.B.OUTW = width;
1827 }
1828 
1829 
1830 IFX_INLINE void IfxAsclin_setSampleMode(Ifx_ASCLIN *asclin, IfxAsclin_SamplesPerBit medianFilter)
1831 {
1832  asclin->BITCON.B.SM = medianFilter;
1833 }
1834 
1835 
1837 {
1838  asclin->BITCON.B.SAMPLEPOINT = __minu(spPosition, asclin->BITCON.B.OVERSAMPLING);
1839 }
1840 
1841 
1843 {
1844  asclin->FRAMECON.B.MSB = dir;
1845 }
1846 
1847 
1849 {
1850  asclin->CLC.B.EDIS = mode;
1851 }
1852 
1853 
1854 IFX_INLINE void IfxAsclin_setStopBit(Ifx_ASCLIN *asclin, IfxAsclin_StopBit stopBit)
1855 {
1856  asclin->FRAMECON.B.STOP = stopBit;
1857 }
1858 
1859 
1861 {
1862  asclin->FLAGSSET.B.THRQS = 1;
1863 }
1864 
1865 
1867 {
1868  asclin->FLAGSSET.B.TRRQS = 1;
1869 }
1870 
1871 
1873 {
1874  asclin->FLAGSSET.B.TWRQS = 1;
1875 }
1876 
1877 
1879 {
1880  asclin->TXFIFOCON.B.INW = width;
1881 }
1882 
1883 
1885 {
1886  asclin->TXFIFOCON.B.INTLEVEL = __minu(level, 15);
1887 }
1888 
1889 
1891 {
1892  return asclin->FLAGS.B.BD;
1893 }
1894 
1895 
1897 {
1898  return asclin->CSR.B.CLKSEL;
1899 }
1900 
1901 
1902 IFX_INLINE boolean IfxAsclin_getClockStatus(Ifx_ASCLIN *asclin)
1903 {
1904  return asclin->CSR.B.CON;
1905 }
1906 
1907 
1909 {
1910  return asclin->FLAGS.B.CE;
1911 }
1912 
1913 
1915 {
1916  return asclin->FLAGS.B.FED;
1917 }
1918 
1919 
1921 {
1922  return asclin->FLAGS.B.FE;
1923 }
1924 
1925 
1927 {
1928  return asclin->FLAGS.B.HT;
1929 }
1930 
1931 
1932 IFX_INLINE boolean IfxAsclin_getKernelResetStatus(Ifx_ASCLIN *asclin)
1933 {
1934  return asclin->KRST0.B.RSTSTAT;
1935 }
1936 
1937 
1939 {
1940  return asclin->FLAGS.B.LA;
1941 }
1942 
1943 
1945 {
1946  return asclin->FLAGS.B.LC;
1947 }
1948 
1949 
1951 {
1952  return asclin->FLAGS.B.LP;
1953 }
1954 
1955 
1956 IFX_INLINE boolean IfxAsclin_getModuleStatus(Ifx_ASCLIN *asclin)
1957 {
1958  return asclin->CLC.B.DISS;
1959 }
1960 
1961 
1963 {
1964  return asclin->FLAGS.B.PE;
1965 }
1966 
1967 
1969 {
1970  return asclin->BITCON.B.PRESCALER + 1;
1971 }
1972 
1973 
1975 {
1976  return asclin->FLAGS.B.RED;
1977 }
1978 
1979 
1981 {
1982  return asclin->IOCR.B.RXM;
1983 }
1984 
1985 
1987 {
1988  return asclin->FLAGS.B.RT;
1989 }
1990 
1991 
1993 {
1994  return asclin->RXFIFOCON.B.FILL;
1995 }
1996 
1997 
1999 {
2000  return asclin->FLAGS.B.RFL;
2001 }
2002 
2003 
2005 {
2006  return asclin->RXFIFOCON.B.OUTW;
2007 }
2008 
2009 
2011 {
2012  return asclin->FLAGS.B.RFO;
2013 }
2014 
2015 
2017 {
2018  return asclin->FLAGS.B.RFU;
2019 }
2020 
2021 
2023 {
2024  return asclin->FLAGS.B.RH;
2025 }
2026 
2027 
2029 {
2030  return asclin->FLAGS.B.RR;
2031 }
2032 
2033 
2035 {
2036  return asclin->FLAGS.B.TC;
2037 }
2038 
2039 
2041 {
2042  return asclin->IOCR.B.TXM;
2043 }
2044 
2045 
2047 {
2048  return asclin->TXFIFOCON.B.FILL;
2049 }
2050 
2051 
2053 {
2054  return asclin->FLAGS.B.TFL;
2055 }
2056 
2057 
2059 {
2060  return asclin->TXFIFOCON.B.INW;
2061 }
2062 
2063 
2065 {
2066  return asclin->FLAGS.B.TFO;
2067 }
2068 
2069 
2071 {
2072  return asclin->FLAGS.B.TH;
2073 }
2074 
2075 
2077 {
2078  return asclin->FLAGS.B.TR;
2079 }
2080 
2081 
2082 IFX_INLINE void IfxAsclin_disableAllFlags(Ifx_ASCLIN *asclin)
2083 {
2084  asclin->FLAGSENABLE.U = 0x00000000;
2085 }
2086 
2087 
2089 {
2090  asclin->LIN.CON.B.ABD = enable ? 1 : 0;
2091 }
2092 
2093 
2094 IFX_INLINE void IfxAsclin_enableBreakDetectedFlag(Ifx_ASCLIN *asclin, boolean enable)
2095 {
2096  asclin->FLAGSENABLE.B.BDE = enable ? 1 : 0;
2097 }
2098 
2099 
2100 IFX_INLINE void IfxAsclin_enableCollisionDetection(Ifx_ASCLIN *asclin, boolean enable)
2101 {
2102  asclin->FRAMECON.B.CEN = enable ? 1 : 0;
2103 }
2104 
2105 
2107 {
2108  asclin->FLAGSENABLE.B.CEE = enable ? 1 : 0;
2109 }
2110 
2111 
2112 IFX_INLINE void IfxAsclin_enableCts(Ifx_ASCLIN *asclin, boolean enable)
2113 {
2114  asclin->IOCR.B.CTSEN = enable ? 1 : 0;
2115 }
2116 
2117 
2119 {
2120  asclin->FLAGSENABLE.B.FEDE = enable ? 1 : 0;
2121 }
2122 
2123 
2124 IFX_INLINE void IfxAsclin_enableFrameErrorFlag(Ifx_ASCLIN *asclin, boolean enable)
2125 {
2126  asclin->FLAGSENABLE.B.FEE = enable ? 1 : 0;
2127 }
2128 
2129 
2130 IFX_INLINE void IfxAsclin_enableHardwareChecksum(Ifx_ASCLIN *asclin, boolean enable)
2131 {
2132  asclin->LIN.CON.B.CSEN = enable ? 1 : 0;
2133 }
2134 
2135 
2136 IFX_INLINE void IfxAsclin_enableHeaderTimeoutFlag(Ifx_ASCLIN *asclin, boolean enable)
2137 {
2138  asclin->FLAGSENABLE.B.HTE = enable ? 1 : 0;
2139 }
2140 
2141 
2143 {
2144  asclin->FLAGSENABLE.B.ABE = enable ? 1 : 0;
2145 }
2146 
2147 
2148 IFX_INLINE void IfxAsclin_enableLinChecksumErrorFlag(Ifx_ASCLIN *asclin, boolean enable)
2149 {
2150  asclin->FLAGSENABLE.B.LCE = enable ? 1 : 0;
2151 }
2152 
2153 
2154 IFX_INLINE void IfxAsclin_enableLinParityErrorFlag(Ifx_ASCLIN *asclin, boolean enable)
2155 {
2156  asclin->FLAGSENABLE.B.LPE = enable ? 1 : 0;
2157 }
2158 
2159 
2160 IFX_INLINE void IfxAsclin_enableLoopBackMode(Ifx_ASCLIN *asclin, boolean enable)
2161 {
2162  asclin->IOCR.B.LB = enable ? 1 : 0;
2163 }
2164 
2165 
2166 IFX_INLINE void IfxAsclin_enableParity(Ifx_ASCLIN *asclin, boolean enable)
2167 {
2168  asclin->FRAMECON.B.PEN = enable ? 1 : 0;
2169 }
2170 
2171 
2172 IFX_INLINE void IfxAsclin_enableParityErrorFlag(Ifx_ASCLIN *asclin, boolean enable)
2173 {
2174  asclin->FLAGSENABLE.B.PEE = enable ? 1 : 0;
2175 }
2176 
2177 
2179 {
2180  asclin->FLAGSENABLE.B.REDE = enable ? 1 : 0;
2181 }
2182 
2183 
2184 IFX_INLINE void IfxAsclin_enableResponseTimeoutFlag(Ifx_ASCLIN *asclin, boolean enable)
2185 {
2186  asclin->FLAGSENABLE.B.RTE = enable ? 1 : 0;
2187 }
2188 
2189 
2190 IFX_INLINE void IfxAsclin_enableRxFifoFillLevelFlag(Ifx_ASCLIN *asclin, boolean enable)
2191 {
2192  asclin->FLAGSENABLE.B.RFLE = enable ? 1 : 0;
2193 }
2194 
2195 
2196 IFX_INLINE void IfxAsclin_enableRxFifoInlet(Ifx_ASCLIN *asclin, boolean enable)
2197 {
2198  asclin->RXFIFOCON.B.ENI = enable ? 1 : 0;
2199 }
2200 
2201 
2202 IFX_INLINE void IfxAsclin_enableRxFifoOverflowFlag(Ifx_ASCLIN *asclin, boolean enable)
2203 {
2204  asclin->FLAGSENABLE.B.RFOE = enable ? 1 : 0;
2205 }
2206 
2207 
2208 IFX_INLINE void IfxAsclin_enableRxFifoUnderflowFlag(Ifx_ASCLIN *asclin, boolean enable)
2209 {
2210  asclin->FLAGSENABLE.B.RFUE = enable ? 1 : 0;
2211 }
2212 
2213 
2214 IFX_INLINE void IfxAsclin_enableRxHeaderEndFlag(Ifx_ASCLIN *asclin, boolean enable)
2215 {
2216  asclin->FLAGSENABLE.B.RHE = enable ? 1 : 0;
2217 }
2218 
2219 
2220 IFX_INLINE void IfxAsclin_enableRxResponseEndFlag(Ifx_ASCLIN *asclin, boolean enable)
2221 {
2222  asclin->FLAGSENABLE.B.RRE = enable ? 1 : 0;
2223 }
2224 
2225 
2227 {
2228  asclin->FLAGSENABLE.B.TCE = enable ? 1 : 0;
2229 }
2230 
2231 
2232 IFX_INLINE void IfxAsclin_enableTxFifoFillLevelFlag(Ifx_ASCLIN *asclin, boolean enable)
2233 {
2234  asclin->FLAGSENABLE.B.TFLE = enable ? 1 : 0;
2235 }
2236 
2237 
2238 IFX_INLINE void IfxAsclin_enableTxFifoOutlet(Ifx_ASCLIN *asclin, boolean enable)
2239 {
2240  asclin->TXFIFOCON.B.ENO = enable ? 1 : 0;
2241 }
2242 
2243 
2244 IFX_INLINE void IfxAsclin_enableTxFifoOverflowFlag(Ifx_ASCLIN *asclin, boolean enable)
2245 {
2246  asclin->FLAGSENABLE.B.TFOE = enable ? 1 : 0;
2247 }
2248 
2249 
2250 IFX_INLINE void IfxAsclin_enableTxHeaderEndFlag(Ifx_ASCLIN *asclin, boolean enable)
2251 {
2252  asclin->FLAGSENABLE.B.THE = enable ? 1 : 0;
2253 }
2254 
2255 
2256 IFX_INLINE void IfxAsclin_enableTxResponseEndFlag(Ifx_ASCLIN *asclin, boolean enable)
2257 {
2258  asclin->FLAGSENABLE.B.TRE = enable ? 1 : 0;
2259 }
2260 
2261 
2263 {
2264  asclin->IOCR.B.CPOL = cpol;
2265 }
2266 
2267 
2269 {
2270  asclin->IOCR.B.CTS = ctsi;
2271 }
2272 
2273 
2275 {
2276  asclin->FRAMECON.B.MODE = mode;
2277 }
2278 
2279 
2281 {
2282  asclin->IOCR.B.RCPOL = rcpol;
2283 }
2284 
2285 
2287 {
2288  asclin->IOCR.B.ALTI = alti;
2289 }
2290 
2291 
2293 {
2294  asclin->IOCR.B.SPOL = spol;
2295 }
2296 
2297 
2299 {
2300  IfxPort_setPinModeInput(cts->pin.port, cts->pin.pinIndex, inputMode);
2303 }
2304 
2305 
2307 {
2308  IfxPort_setPinModeOutput(rts->pin.port, rts->pin.pinIndex, outputMode, rts->select);
2309  IfxPort_setPinPadDriver(rts->pin.port, rts->pin.pinIndex, padDriver);
2310 }
2311 
2312 
2314 {
2315  IfxPort_setPinModeInput(rx->pin.port, rx->pin.pinIndex, inputMode);
2317 }
2318 
2319 
2321 {
2322  IfxPort_setPinModeOutput(sclk->pin.port, sclk->pin.pinIndex, outputMode, sclk->select);
2323  IfxPort_setPinPadDriver(sclk->pin.port, sclk->pin.pinIndex, padDriver);
2324 }
2325 
2326 
2328 {
2329  IfxPort_setPinModeOutput(slso->pin.port, slso->pin.pinIndex, outputMode, slso->select);
2330  IfxPort_setPinPadDriver(slso->pin.port, slso->pin.pinIndex, padDriver);
2331 }
2332 
2333 
2335 {
2336  IfxPort_setPinModeOutput(tx->pin.port, tx->pin.pinIndex, outputMode, tx->select);
2337  IfxPort_setPinPadDriver(tx->pin.port, tx->pin.pinIndex, padDriver);
2338 }
2339 
2340 
2342 {
2343  return asclin->RXDATA.U;
2344 }
2345 
2346 
2347 IFX_INLINE void IfxAsclin_writeTxData(Ifx_ASCLIN *asclin, uint32 data)
2348 {
2349  asclin->TXDATA.U = data;
2350 }
2351 
2352 
2353 #endif /* IFXASCLIN_H */