43 vadc->ACCPROT0.U |= (0x00000001 << protectionSet);
47 vadc->ACCPROT1.U |= (0x00000001 << (protectionSet & 0x1F));
60 uint32 mask = 1 << (IFX_VADC_GLOBCFG_DPCAL0_OFF + group);
64 vadc->GLOBCFG.U |= mask;
68 vadc->GLOBCFG.U &= ~mask;
84 vadc->ACCPROT0.U &= ~(0x00000001 << protectionSet);
88 vadc->ACCPROT1.U &= ~(0x00000001 << (protectionSet & 0x1F));
112 for (i = 0; i < 8; i++)
114 if (vadc->BRSPND[i].U)
133 if (0x7 == group->QSR0.B.FILL)
148 sint32 sourceResultRegister = -1;
149 Ifx_VADC_RES tmpResult;
154 sourceResultRegister = group->QCTRL0.B.SRCRESREG;
158 sourceResultRegister = group->ASCTRL.B.SRCRESREG;
162 sourceResultRegister = vadc->BRSCTRL.B.SRCRESREG;
166 if (sourceResultRegister > 0)
168 tmpResult.U = group->RES[sourceResultRegister].U;
176 tmpResult.B.VF = vadc->GLOBRES.B.VF;
177 tmpResult.B.FCR = vadc->GLOBRES.B.FCR;
178 tmpResult.B.CRS = vadc->GLOBRES.B.CRS;
179 tmpResult.B.EMUX = vadc->GLOBRES.B.EMUX;
180 tmpResult.B.CHNR = vadc->GLOBRES.B.CHNR;
181 tmpResult.B.DRC = vadc->GLOBRES.B.GNR;
182 tmpResult.B.RESULT = vadc->GLOBRES.B.RESULT;
188 tmpResult.U = group->RES[group->CHCTR[channel].B.RESREG].U;
219 if ((group & 0x1) != 0)
241 Ifx_VADC_GLOBCFG tempGLOBCFG;
242 tempGLOBCFG.U = vadc->GLOBCFG.U;
243 tempGLOBCFG.B.DIVA = arbiterClockDivider;
244 tempGLOBCFG.B.DIVWC = 1;
246 vadc->GLOBCFG.U = tempGLOBCFG.U;
253 Ifx_VADC_GLOBCFG tempGLOBCFG;
254 tempGLOBCFG.U = vadc->GLOBCFG.U;
255 tempGLOBCFG.B.DIVD = converterClockDivider;
256 tempGLOBCFG.B.DIVWC = 1;
258 vadc->GLOBCFG.U = tempGLOBCFG.U;
269 divD = (fadc / fAdcD - 1);
271 divD =
__minu(divD, 0x3u);
273 result = fadc / (divD + 1);
286 divA = (fadc << 2) / fAdcI;
288 divA = (divA + 2) >> 2;
289 divA =
__minu(divA - 1, 0x1Fu);
290 result = fadc / (divA + 1);
294 divA =
__minu(divA + 1, 0x1Fu);
296 result = fadc / (divA + 1);
322 vadc->KRST1.B.RST = 1;
323 vadc->KRST0.B.RST = 1;
325 while (vadc->KRST0.B.RSTSTAT == 0)
330 vadc->KRSTCLR.B.CLR = 1;
338 if (slotEnable !=
FALSE)
340 vadcG->ARBPR.U |= slotEnable << (IFX_VADC_G_ARBPR_ASEN0_OFF + slot);
341 vadcG->ARBPR.U &= ~(IFX_VADC_G_ARBPR_PRIO0_MSK << (slot * 4
u));
342 vadcG->ARBPR.U |= (prio << (slot * 4
u));
346 vadcG->ARBPR.U |= 0x1
u << (IFX_VADC_G_ARBPR_CSM0_OFF + (slot * 4
u));
350 vadcG->ARBPR.U &= ~(0x1
u << (IFX_VADC_G_ARBPR_CSM0_OFF + (slot * 4
u)));
355 vadcG->ARBPR.U &= ~(IFX_VADC_G_ARBPR_ASEN0_MSK << (IFX_VADC_G_ARBPR_ASEN0_OFF + slot));
364 group->ASSEL.U = (group->ASSEL.U & ~mask) | (channels & mask);
373 boolean calibrationRunning;
374 uint8 adcCalGroupNum;
386 calibrationRunning =
FALSE;
392 calibrationRunning =
TRUE;
399 }
while (calibrationRunning ==
TRUE);