iLLD_TC27xC  1.0
IfxPsi5.h
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1 /**
2  * \file IfxPsi5.h
3  * \brief PSI5 basic functionality
4  * \ingroup IfxLld_Psi5
5  *
6  * \version iLLD_0_1_0_10
7  * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
8  *
9  *
10  * IMPORTANT NOTICE
11  *
12  *
13  * Infineon Technologies AG (Infineon) is supplying this file for use
14  * exclusively with Infineon's microcontroller products. This file can be freely
15  * distributed within development tools that are supporting such microcontroller
16  * products.
17  *
18  * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
19  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
20  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
21  * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
22  * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
23  *
24  * \defgroup IfxLld_Psi5 PSI5
25  * \ingroup IfxLld
26  * \defgroup IfxLld_Psi5_Std Standard Driver
27  * \ingroup IfxLld_Psi5
28  * \defgroup IfxLld_Psi5_Std_Enumerations Enumerations
29  * \ingroup IfxLld_Psi5_Std
30  * \defgroup IfxLld_Psi5_Std_Channel Channel Status Functions
31  * \ingroup IfxLld_Psi5_Std
32  * \defgroup IfxLld_Psi5_Std_IO IO Pin Configuration Functions
33  * \ingroup IfxLld_Psi5_Std
34  */
35 
36 #ifndef IFXPSI5_H
37 #define IFXPSI5_H 1
38 
39 /******************************************************************************/
40 /*----------------------------------Includes----------------------------------*/
41 /******************************************************************************/
42 
43 #include "_Impl/IfxPsi5_cfg.h"
44 #include "_PinMap/IfxPsi5_PinMap.h"
45 
46 /******************************************************************************/
47 /*--------------------------------Enumerations--------------------------------*/
48 /******************************************************************************/
49 
50 /** \addtogroup IfxLld_Psi5_Std_Enumerations
51  * \{ */
52 /** \brief MODULE_PSI5.IOCRx.ALTI(x = 0,1,2),Alternate input selection
53  */
54 typedef enum
55 {
56  IfxPsi5_AlternateInput_0 = 0, /**< \brief Alternate Input 0 */
57  IfxPsi5_AlternateInput_1, /**< \brief Alternate Input 1 */
58  IfxPsi5_AlternateInput_2, /**< \brief Alternate Input 2 */
59  IfxPsi5_AlternateInput_3, /**< \brief Alternate Input 3 */
61 
62 /** \brief MODULE_PSI5.RCRCx.BRS(x = 0,1,2),Baud rate selection
63  */
64 typedef enum
65 {
66  IfxPsi5_BaudRate_125 = 0, /**< \brief Slow 125 kHz clock */
67  IfxPsi5_BaudRate_189 = 1 /**< \brief Fast 189 kHz clock */
69 
70 /** \brief MODULE_PSI5.RCRBx.CRCy(x = 0,1,2; y=0,1,2,3,4,5),CRC or parity selection
71  */
72 typedef enum
73 {
74  IfxPsi5_CRCorParity_parity = 0, /**< \brief parity selection */
75  IfxPsi5_CRCorParity_crc = 1 /**< \brief CRC selection */
77 
78 /** \brief Clock type
79  */
80 typedef enum
81 {
82  IfxPsi5_ClockType_fracDiv = 0, /**< \brief Fractional Divide clock */
83  IfxPsi5_ClockType_slowClock_125 = 1, /**< \brief Slow 125 kHz clock */
84  IfxPsi5_ClockType_fastClock_189 = 2, /**< \brief Fast 189 kHz clock */
85  IfxPsi5_ClockType_timeStamp = 3 /**< \brief Timestamp clock */
87 
88 /** \brief MODULE_PSI5.IOCRx.DEPTH(x = 0,1,2),Digital input filter depth
89  */
90 typedef enum
91 {
92  IfxPsi5_DigitalInputFilterDepth_0 = 0, /**< \brief Digital input filter depth is 0 */
93  IfxPsi5_DigitalInputFilterDepth_1, /**< \brief Digital input filter depth is 1 */
94  IfxPsi5_DigitalInputFilterDepth_2, /**< \brief Digital input filter depth is 2 */
95  IfxPsi5_DigitalInputFilterDepth_3, /**< \brief Digital input filter depth is 3 */
96  IfxPsi5_DigitalInputFilterDepth_4, /**< \brief Digital input filter depth is 4 */
97  IfxPsi5_DigitalInputFilterDepth_5, /**< \brief Digital input filter depth is 5 */
98  IfxPsi5_DigitalInputFilterDepth_6, /**< \brief Digital input filter depth is 6 */
99  IfxPsi5_DigitalInputFilterDepth_7, /**< \brief Digital input filter depth is 7 */
100  IfxPsi5_DigitalInputFilterDepth_8, /**< \brief Digital input filter depth is 8 */
101  IfxPsi5_DigitalInputFilterDepth_9, /**< \brief Digital input filter depth is 9 */
102  IfxPsi5_DigitalInputFilterDepth_10, /**< \brief Digital input filter depth is 10 */
103  IfxPsi5_DigitalInputFilterDepth_11, /**< \brief Digital input filter depth is 11 */
104  IfxPsi5_DigitalInputFilterDepth_12, /**< \brief Digital input filter depth is 12 */
105  IfxPsi5_DigitalInputFilterDepth_13, /**< \brief Digital input filter depth is 13 */
106  IfxPsi5_DigitalInputFilterDepth_14, /**< \brief Digital input filter depth is 14 */
107  IfxPsi5_DigitalInputFilterDepth_15, /**< \brief Digital input filter depth is 15 */
109 
110 /** \brief MODULE_PSI5.FDR.DM,Divider mode
111  */
112 typedef enum
113 {
114  IfxPsi5_DividerMode_spb = 0, /**< \brief divider mode is off */
115  IfxPsi5_DividerMode_normal = 1, /**< \brief divider mode is normal */
116  IfxPsi5_DividerMode_fractional = 2, /**< \brief divider mode is fractional */
117  IfxPsi5_DividerMode_off = 3 /**< \brief divider mode is off */
119 
120 /** \brief MODULE_PSI5.RCRBx.FECy(x = 0,1,2; y=0,1,2,3,4,5),Frame expectation control
121  */
122 typedef enum
123 {
124  IfxPsi5_FrameExpectation_notExpected = 0, /**< \brief No frame is expected */
125  IfxPsi5_FrameExpectation_expected = 1 /**< \brief Frame is expected */
127 
128 /** \brief MODULE_PSI5.RCRBx.MSGy(x = 0,1,2; y=0,1,2,3,4,5),Messaging bits presence
129  */
130 typedef enum
131 {
132  IfxPsi5_MessagingBits_absent = 0, /**< \brief No messaging bits */
133  IfxPsi5_MessagingBits_present = 1 /**< \brief 2 messaging bits */
135 
136 /** \brief MODULE_PSI5.RCRCx.TSR(x = 0,1,2),Timestamp select for receive data registers
137  */
138 typedef enum
139 {
140  IfxPsi5_ReceiveDataRegisterTimestamp_pulse = 0, /**< \brief Pulse based timestamp SPTSC to be stored in RDRHC */
141  IfxPsi5_ReceiveDataRegisterTimestamp_frame = 1 /**< \brief Start of frame based timestamp SPTSC to be stored in RDRHC */
143 
144 /** \brief MODULE_PSI5.RDRHx.SC(x = 0-2),Slot Id
145  */
146 typedef enum
147 {
148  IfxPsi5_Slot_0 = 0, /**< \brief slot 0 */
149  IfxPsi5_Slot_1, /**< \brief slot 1 */
150  IfxPsi5_Slot_2, /**< \brief slot 2 */
151  IfxPsi5_Slot_3, /**< \brief slot 3 */
152  IfxPsi5_Slot_4, /**< \brief slot 4 */
153  IfxPsi5_Slot_5, /**< \brief slot 5 */
154 } IfxPsi5_Slot;
155 
156 /** \brief MODULE_PSI5.PGCx.TBS(x = 0,1,2),Time base
157  */
158 typedef enum
159 {
160  IfxPsi5_TimeBase_internal = 0, /**< \brief Internal time stamp clock */
161  IfxPsi5_TimeBase_external = 1 /**< \brief External GTM inputs */
163 
164 /** \brief MODULE_PSI5.RCRCx.TSP(x = 0,1,2),MODULE_PSI5.RCRCx.TSF(x = 0,1,2)Timestamp register type
165  */
166 typedef enum
167 {
168  IfxPsi5_TimestampRegister_a = 0, /**< \brief Timestamp register A */
169  IfxPsi5_TimestampRegister_b = 1, /**< \brief Timestamp register B */
170  IfxPsi5_TimestampRegister_c = 2 /**< \brief Timestamp register C */
172 
173 /** \brief MODULE_PSI5.PGCx.ETS(x = 0,1,2),Trigger Id
174  */
175 typedef enum
176 {
177  IfxPsi5_Trigger_0 = 0, /**< \brief trigger 0 */
178  IfxPsi5_Trigger_1, /**< \brief trigger 1 */
179  IfxPsi5_Trigger_2, /**< \brief trigger 2 */
180  IfxPsi5_Trigger_3, /**< \brief trigger 3 */
181  IfxPsi5_Trigger_4, /**< \brief trigger 4 */
182  IfxPsi5_Trigger_5, /**< \brief trigger 5 */
184 
185 /** \brief Trigger type
186  */
187 typedef enum
188 {
189  IfxPsi5_TriggerType_periodic = 0, /**< \brief Periodic trigger */
190  IfxPsi5_TriggerType_external = 1, /**< \brief External trigger */
191  IfxPsi5_TriggerType_bypass = 2 /**< \brief Bypassed trigger */
193 
194 /** \brief MODULE_PSI5.RCRBx.VBSy(x = 0,1,2; y=0,1,2,3,4,5),Verbose mode
195  */
196 typedef enum
197 {
198  IfxPsi5_Verbose_off = 0, /**< \brief Verbose mode is turned off */
199  IfxPsi5_Verbose_on = 1 /**< \brief Verbose mode is turned on */
201 
202 /** \} */
203 
204 /** \addtogroup IfxLld_Psi5_Std_Channel
205  * \{ */
206 
207 /******************************************************************************/
208 /*-------------------------Inline Function Prototypes-------------------------*/
209 /******************************************************************************/
210 
211 /** \brief access function to get the CRCI status register contents for a channel
212  * \param psi5 pointer to the PSI5 register space
213  * \param channel channel Id
214  * \return Crci status register contents
215  */
217 
218 /** \brief access function to get the MEI status register contents for a channel
219  * \param psi5 pointer to the PSI5 register space
220  * \param channel channel Id
221  * \return Mei status register contents
222  */
224 
225 /** \brief access function to get the NBI status register contents for a channel
226  * \param psi5 pointer to the PSI5 register space
227  * \param channel channel Id
228  * \return Nbi status register contents
229  */
231 
232 /** \brief access function to get the NFI status register contents for a channel
233  * \param psi5 pointer to the PSI5 register space
234  * \param channel channel Id
235  * \return Nfi status register contents
236  */
238 
239 /** \brief access function to get the RDI status register contents for a channel
240  * \param psi5 pointer to the PSI5 register space
241  * \param channel channel Id
242  * \return Rdi status register contents
243  */
245 
246 /** \brief access function to get the RMI status register contents for a channel
247  * \param psi5 pointer to the PSI5 register space
248  * \param channel channel Id
249  * \return Rmi status register contents
250  */
252 
253 /** \brief access function to get the RSI status register contents for a channel
254  * \param psi5 pointer to the PSI5 register space
255  * \param channel channel Id
256  * \return Rsi status register contents
257  */
259 
260 /** \brief access function to get the TEI status register contents for a channel
261  * \param psi5 pointer to the PSI5 register space
262  * \param channel channel Id
263  * \return Tei status register contents
264  */
266 
267 /** \} */
268 
269 /** \addtogroup IfxLld_Psi5_Std_IO
270  * \{ */
271 
272 /******************************************************************************/
273 /*-------------------------Inline Function Prototypes-------------------------*/
274 /******************************************************************************/
275 
276 /** \brief Sets the alternate RX input
277  * \param psi5Ch pointer to the PSI5 channel register space
278  * \param alternateInput Alternate RX input selection
279  * \return None
280  */
281 IFX_INLINE void IfxPsi5_setRxInput(Ifx_PSI5_CH *psi5Ch, IfxPsi5_AlternateInput alternateInput);
282 
283 /** \brief Initializes a RX input
284  * \param rx the RX Pin which should be configured
285  * \param inputMode pin input mode which should be configured
286  * \return None
287  */
289 
290 /** \brief Initializes a TX output
291  * \param tx the TX Pin which should be configured
292  * \param outputMode the pin output mode which should be configured
293  * \param padDriver the pad driver mode which should be configured
294  * \return None
295  */
297 
298 /** \} */
299 
300 /******************************************************************************/
301 /*---------------------Inline Function Implementations------------------------*/
302 /******************************************************************************/
303 
305 {
306  return psi5->CRCIOV[channel].U;
307 }
308 
309 
311 {
312  return psi5->MEIOV[channel].U;
313 }
314 
315 
317 {
318  return psi5->NBIOV[channel].U;
319 }
320 
321 
323 {
324  return psi5->NFIOV[channel].U;
325 }
326 
327 
329 {
330  return psi5->RDIOV[channel].U;
331 }
332 
333 
335 {
336  return psi5->RMIOV[channel].U;
337 }
338 
339 
341 {
342  return psi5->RSIOV[channel].U;
343 }
344 
345 
347 {
348  return psi5->TEIOV[channel].U;
349 }
350 
351 
352 IFX_INLINE void IfxPsi5_setRxInput(Ifx_PSI5_CH *psi5Ch, IfxPsi5_AlternateInput alternateInput)
353 {
356  psi5Ch->IOCR.B.ALTI = alternateInput;
357  IfxScuWdt_setCpuEndinit(passwd);
358 }
359 
360 
362 {
363  IfxPort_setPinModeInput(rx->pin.port, rx->pin.pinIndex, inputMode);
364  Ifx_PSI5 *psi5 = rx->module;
365  Ifx_PSI5_CH *psi5Ch = &psi5->CH[rx->channelId];
367 }
368 
369 
371 {
372  IfxPort_setPinModeOutput(tx->pin.port, tx->pin.pinIndex, outputMode, tx->select);
373  IfxPort_setPinPadDriver(tx->pin.port, tx->pin.pinIndex, padDriver);
374 }
375 
376 
377 #endif /* IFXPSI5_H */