iLLD_TC27xC  1.0
IfxScu_cfg.h
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1 /**
2  * \file IfxScu_cfg.h
3  * \brief SCU on-chip implementation data
4  * \ingroup IfxLld_Scu
5  *
6  * \version iLLD_0_1_0_10
7  * \copyright Copyright (c) 2012 Infineon Technologies AG. All rights reserved.
8  *
9  *
10  * IMPORTANT NOTICE
11  *
12  *
13  * Infineon Technologies AG (Infineon) is supplying this file for use
14  * exclusively with Infineon's microcontroller products. This file can be freely
15  * distributed within development tools that are supporting such microcontroller
16  * products.
17  *
18  * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
19  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
20  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
21  * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
22  * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
23  *
24  */
25 
26 #ifndef IFXSCU_CFG_H
27 #define IFXSCU_CFG_H
28 /******************************************************************************/
29 #include "Ifx_Cfg.h"
30 #include "IfxScu_bf.h"
31 #include "IfxFlash_bf.h"
32 
33 /******************************************************************************/
34 /* Macro */
35 /******************************************************************************/
36 #ifndef IFX_CFG_SCU_XTAL_FREQUENCY
37 # define IFX_CFG_SCU_XTAL_FREQUENCY 20000000 /**< \brief Default External oscillator frequency */
38 # warning "IFX_CFG_SCU_XTAL_FREQUENCY not specified in your IfxCfg.h file."
39 # warning "Please doublecheck the external XTAL frequency with the default setting of 20 MHz!"
40 #endif
41 
42 #ifndef IFX_CFG_SCU_PLL_FREQUENCY
43 # define IFX_CFG_SCU_PLL_FREQUENCY 200000000 /**< \brief Default PLL frequency */
44 #endif
45 
46 #define IFXSCU_VCO_BASE_FREQUENCY (100000000.0)
47 #define IFXSCU_EVR_OSC_FREQUENCY (100000000.0)
48 
49 /*The following frequency is the PLL free running frequency */
50 /* FIXME is this not redundant to IFXSCU_VCO_BASE_FREQUENCY */
51 #define IFXSCU_PLL_FREERUNNING_FREQUENCY (100000000.0)
52 
53 /******************************************************************************/
54 /** \brief Macros to configure Pll steps,
55  * Macros to configure the Pll steps for different profiles of Crystal frequency and
56  * target frequencies. This configuration is important for the current jump controll
57  * during clock throttling.
58  * \ref IfxScuCcu_PllStepsConfig
59  */
60 
61 /******************** Pll step for 16MHz crystal Configurations ********************************/
62 #ifndef IFXSCU_CFG_PLL_STEPS_16MHZ_80MHZ
63 /** \brief Macro for Pll step for profile with 16MHz Crystal and 80MHz target */
64 #define IFXSCU_CFG_PLL_STEPS_16MHZ_80MHZ \
65  { /*Step 0 Config: 80MHz*/ \
66  (8 - 1), /*uint8 k2Step;*/ \
67  0.000100, /*float32 waitTime;*/ \
68  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
69  },
70 #endif /*#ifndef IFXSCU_CFG_PLL_STEPS_16MHZ_80MHZ */
71 
72 #ifndef IFXSCU_CFG_PLL_STEPS_16MHZ_133MHZ
73 /** \brief Macro for Pll step for profile with 16MHz Crystal and 133MHz target */
74 #define IFXSCU_CFG_PLL_STEPS_16MHZ_133MHZ \
75  { /*Step 0 Config: 114MHz*/ \
76  (7 - 1), /*uint8 k2Step;*/ \
77  0.000100, /*float32 waitTime;*/ \
78  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
79  }, \
80  { /*Step 1 Config: 133MHz*/ \
81  (6 - 1), /*uint8 k2Step;*/ \
82  0.000100, /*float32 waitTime;*/ \
83  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
84  },
85 #endif /*#ifndef IFXSCU_CFG_PLL_STEPS_16MHZ_133MHZ */
86 
87 #ifndef IFXSCU_CFG_PLL_STEPS_16MHZ_160MHZ
88 /** \brief Macro for Pll step for profile with 16MHz Crystal and 160MHz target */
89 #define IFXSCU_CFG_PLL_STEPS_16MHZ_160MHZ \
90  { /*Step 1 Config: 128MHz*/ \
91  (5 - 1), /*uint8 k2Step;*/ \
92  0.000100, /*float32 waitTime;*/ \
93  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
94  }, \
95  { /*Step 2 Config: 160MHz*/ \
96  (4 - 1), /*uint8 k2Step;*/ \
97  0.000100, /*float32 waitTime;*/ \
98  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
99  }
100 #endif /*#ifndef IFXSCU_CFG_PLL_STEPS_16MHZ_160MHZ */
101 
102 #ifndef IFXSCU_CFG_PLL_STEPS_16MHZ_200MHZ
103 /** \brief Macro for Pll step for profile with 16MHz Crystal and 200MHz target */
104 #define IFXSCU_CFG_PLL_STEPS_16MHZ_200MHZ \
105  { /*Step 0 Config: 120MHz*/ \
106  (6 - 1), /*uint8 k2Step;*/ \
107  0.000100, /*float32 waitTime;*/ \
108  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
109  }, \
110  { /*Step 1 Config: 150MHz*/ \
111  (5 - 1), /*uint8 k2Step;*/ \
112  0.000100, /*float32 waitTime;*/ \
113  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
114  }, \
115  { /*Step 2 Config: 200MHz*/ \
116  (4 - 1), /*uint8 k2Step;*/ \
117  0.000100, /*float32 waitTime;*/ \
118  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
119  }
120 #endif /*#ifndef IFXSCU_CFG_PLL_STEPS_16MHZ_200MHZ */
121 
122 #ifndef IFXSCU_CFG_PLL_STEPS_16MHZ_240MHZ
123 /** \brief Macro for Pll step for profile with 16MHz Crystal and 240MHz target */
124 #define IFXSCU_CFG_PLL_STEPS_16MHZ_240MHZ \
125  { /*Step 0 Config: 144MHz*/ \
126  (5 - 1), /*uint8 k2Step;*/ \
127  0.000100, /*float32 waitTime;*/ \
128  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
129  }, \
130  { /*Step 1 Config: 180MHz*/ \
131  (4 - 1), /*uint8 k2Step;*/ \
132  0.000100, /*float32 waitTime;*/ \
133  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
134  }, \
135  { /*Step 2 Config: 240MHz*/ \
136  (3 - 1), /*uint8 k2Step;*/ \
137  0.000100, /*float32 waitTime;*/ \
138  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
139  }
140 #endif /*#ifndef IFXSCU_CFG_PLL_STEPS_16MHZ_240MHZ */
141 
142 /******************** Pll step 20MHz crystal Configurations ********************************/
143 #ifndef IFXSCU_CFG_PLL_STEPS_20MHZ_80MHZ
144 /** \brief Macro for Pll step for profile with 20MHz Crystal and 80MHz target */
145 #define IFXSCU_CFG_PLL_STEPS_20MHZ_80MHZ \
146  { /*Step 0 Config: 80MHz*/ \
147  (8 - 1), /*uint8 k2Step;*/ \
148  0.000100, /*float32 waitTime;*/ \
149  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
150  },
151 #endif /*#ifndef IFXSCU_CFG_PLL_STEPS_20MHZ_80MHZ */
152 
153 #ifndef IFXSCU_CFG_PLL_STEPS_20MHZ_133MHZ
154 /** \brief Macro for Pll step for profile with 20MHz Crystal and 133MHz target */
155 #define IFXSCU_CFG_PLL_STEPS_20MHZ_133MHZ \
156  { /*Step 0 Config: 114MHz*/ \
157  (7 - 1), /*uint8 k2Step;*/ \
158  0.000100, /*float32 waitTime;*/ \
159  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
160  }, \
161  { /*Step 1 Config: 133MHz*/ \
162  (6 - 1), /*uint8 k2Step;*/ \
163  0.000100, /*float32 waitTime;*/ \
164  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
165  },
166 #endif /*#ifndef IFXSCU_CFG_PLL_STEPS_20MHZ_133MHZ */
167 
168 #ifndef IFXSCU_CFG_PLL_STEPS_20MHZ_160MHZ
169 /** \brief Macro for Pll step for profile with 20MHz Crystal and 160MHz target */
170 #define IFXSCU_CFG_PLL_STEPS_20MHZ_160MHZ \
171  { /*Step 1 Config: 128MHz*/ \
172  (5 - 1), /*uint8 k2Step;*/ \
173  0.000100, /*float32 waitTime;*/ \
174  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
175  }, \
176  { /*Step 2 Config: 160MHz*/ \
177  (4 - 1), /*uint8 k2Step;*/ \
178  0.000100, /*float32 waitTime;*/ \
179  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
180  }
181 #endif /*#ifndef IFXSCU_CFG_PLL_STEPS_20MHZ_160MHZ */
182 
183 #ifndef IFXSCU_CFG_PLL_STEPS_20MHZ_200MHZ
184 /** \brief Macro for Pll step for profile with 20MHz Crystal and 200MHz target */
185 #define IFXSCU_CFG_PLL_STEPS_20MHZ_200MHZ \
186  { /*Step 0 Config: 120MHz*/ \
187  (5 - 1), /*uint8 k2Step;*/ \
188  0.000100, /*float32 waitTime;*/ \
189  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
190  }, \
191  { /*Step 1 Config: 150MHz*/ \
192  (4 - 1), /*uint8 k2Step;*/ \
193  0.000100, /*float32 waitTime;*/ \
194  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
195  }, \
196  { /*Step 2 Config: 200MHz*/ \
197  (3 - 1), /*uint8 k2Step;*/ \
198  0.000100, /*float32 waitTime;*/ \
199  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
200  }
201 #endif /*#ifndef IFXSCU_CFG_PLL_STEPS_20MHZ_200MHZ */
202 
203 #ifndef IFXSCU_CFG_PLL_STEPS_20MHZ_240MHZ
204 /** \brief Macro for Pll step for profile with 20MHz Crystal and 240MHz target */
205 #define IFXSCU_CFG_PLL_STEPS_20MHZ_240MHZ \
206  { /*Step 0 Config: 144MHz*/ \
207  (5 - 1), /*uint8 k2Step;*/ \
208  0.000100, /*float32 waitTime;*/ \
209  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
210  }, \
211  { /*Step 1 Config: 180MHz*/ \
212  (4 - 1), /*uint8 k2Step;*/ \
213  0.000100, /*float32 waitTime;*/ \
214  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
215  }, \
216  { /*Step 2 Config: 240MHz*/ \
217  (3 - 1), /*uint8 k2Step;*/ \
218  0.000100, /*float32 waitTime;*/ \
219  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
220  }
221 #endif /*#ifndef IFXSCU_CFG_PLL_STEPS_20MHZ_240MHZ */
222 
223 #ifndef IFXSCU_CFG_PLL_STEPS_20MHZ_300MHZ
224 /** \brief Macro for Pll step for profile with 20MHz Crystal and 300MHz target */
225 #define IFXSCU_CFG_PLL_STEPS_20MHZ_300MHZ \
226  { /*Step 0 Config: 150MHz*/ \
227  (4 - 1), /*uint8 k2Step;*/ \
228  0.000100, /*float32 waitTime;*/ \
229  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
230  }, \
231  { /*Step 1 Config: 200MHz*/ \
232  (3 - 1), /*uint8 k2Step;*/ \
233  0.000100, /*float32 waitTime;*/ \
234  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
235  }, \
236  { /*Step 2 Config: 300MHz*/ \
237  (2 - 1), /*uint8 k2Step;*/ \
238  0.000100, /*float32 waitTime;*/ \
239  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
240  }
241 #endif /*#ifndef IFXSCU_CFG_PLL_STEPS_20MHZ_300MHZ */
242 
243 /******************** Pll step for 40MHz crystal Configurations ********************************/
244 #ifndef IFXSCU_CFG_PLL_STEPS_40MHZ_80MHZ
245 /** \brief Macro for Pll step for profile with 40MHz Crystal and 80MHz target */
246 #define IFXSCU_CFG_PLL_STEPS_40MHZ_80MHZ \
247  { /*Step 0 Config: 80MHz*/ \
248  (8 - 1), /*uint8 k2Step;*/ \
249  0.000100, /*float32 waitTime;*/ \
250  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
251  },
252 #endif /*#ifndef IFXSCU_CFG_PLL_STEPS_40MHZ_80MHZ */
253 
254 #ifndef IFXSCU_CFG_PLL_STEPS_40MHZ_133MHZ
255 /** \brief Macro for Pll step for profile with 40MHz Crystal and 133MHz target */
256 #define IFXSCU_CFG_PLL_STEPS_40MHZ_133MHZ \
257  { /*Step 0 Config: 114MHz*/ \
258  (7 - 1), /*uint8 k2Step;*/ \
259  0.000100, /*float32 waitTime;*/ \
260  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
261  }, \
262  { /*Step 1 Config: 133MHz*/ \
263  (6 - 1), /*uint8 k2Step;*/ \
264  0.000100, /*float32 waitTime;*/ \
265  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
266  },
267 #endif /*#ifndef IFXSCU_CFG_PLL_STEPS_40MHZ_133MHZ */
268 
269 #ifndef IFXSCU_CFG_PLL_STEPS_40MHZ_160MHZ
270 /** \brief Macro for Pll step for profile with 40MHz Crystal and 160MHz target */
271 #define IFXSCU_CFG_PLL_STEPS_40MHZ_160MHZ \
272  { /*Step 1 Config: 128MHz*/ \
273  (5 - 1), /*uint8 k2Step;*/ \
274  0.000100, /*float32 waitTime;*/ \
275  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
276  }, \
277  { /*Step 2 Config: 160MHz*/ \
278  (4 - 1), /*uint8 k2Step;*/ \
279  0.000100, /*float32 waitTime;*/ \
280  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
281  }
282 #endif /*#ifndef IFXSCU_CFG_PLL_STEPS_40MHZ_160MHZ */
283 
284 #ifndef IFXSCU_CFG_PLL_STEPS_40MHZ_200MHZ
285 /** \brief Macro for Pll step for profile with 40MHz Crystal and 200MHz target */
286 #define IFXSCU_CFG_PLL_STEPS_40MHZ_200MHZ \
287  { /*Step 0 Config: 120MHz*/ \
288  (5 - 1), /*uint8 k2Step;*/ \
289  0.000100, /*float32 waitTime;*/ \
290  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
291  }, \
292  { /*Step 1 Config: 150MHz*/ \
293  (4 - 1), /*uint8 k2Step;*/ \
294  0.000100, /*float32 waitTime;*/ \
295  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
296  }, \
297  { /*Step 2 Config: 200MHz*/ \
298  (3 - 1), /*uint8 k2Step;*/ \
299  0.000100, /*float32 waitTime;*/ \
300  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
301  }
302 #endif /*#ifndef IFXSCU_CFG_PLL_STEPS_40MHZ_200MHZ */
303 
304 #ifndef IFXSCU_CFG_PLL_STEPS_40MHZ_240MHZ
305 /** \brief Macro for Pll step for profile with 40MHz Crystal and 240MHz target */
306 #define IFXSCU_CFG_PLL_STEPS_40MHZ_240MHZ \
307  { /*Step 0 Config: 144MHz*/ \
308  (5 - 1), /*uint8 k2Step;*/ \
309  0.000100, /*float32 waitTime;*/ \
310  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
311  }, \
312  { /*Step 1 Config: 180MHz*/ \
313  (4 - 1), /*uint8 k2Step;*/ \
314  0.000100, /*float32 waitTime;*/ \
315  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
316  }, \
317  { /*Step 2 Config: 240MHz*/ \
318  (3 - 1), /*uint8 k2Step;*/ \
319  0.000100, /*float32 waitTime;*/ \
320  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
321  }
322 #endif /*#ifndef IFXSCU_CFG_PLL_STEPS_40MHZ_240MHZ */
323 
324 #ifndef IFXSCU_CFG_PLL_STEPS_40MHZ_300MHZ
325 /** \brief Macro for Pll step for profile with 40MHz Crystal and 300MHz target */
326 #define IFXSCU_CFG_PLL_STEPS_40MHZ_300MHZ \
327  { /*Step 0 Config: 150MHz*/ \
328  (4 - 1), /*uint8 k2Step;*/ \
329  0.000100, /*float32 waitTime;*/ \
330  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
331  }, \
332  { /*Step 1 Config: 200MHz*/ \
333  (3 - 1), /*uint8 k2Step;*/ \
334  0.000100, /*float32 waitTime;*/ \
335  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
336  }, \
337  { /*Step 2 Config: 300MHz*/ \
338  (2 - 1), /*uint8 k2Step;*/ \
339  0.000100, /*float32 waitTime;*/ \
340  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
341  }
342 #endif /*#ifndef IFXSCU_CFG_PLL_STEPS_40MHZ_300MHZ */
343 
344 /******************** Pll step for 8MHz crystal Configurations ********************************/
345 #ifndef IFXSCU_CFG_PLL_STEPS_8MHZ_80MHZ
346 /** \brief Macro for Pll step for profile with 8MHz Crystal and 80MHz target */
347 #define IFXSCU_CFG_PLL_STEPS_8MHZ_80MHZ \
348  { /*Step 0 Config: 80MHz*/ \
349  (5 - 1), /*uint8 k2Step;*/ \
350  0.000100, /*float32 waitTime;*/ \
351  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
352  },
353 #endif /*#ifndef IFXSCU_CFG_PLL_STEPS_8MHZ_80MHZ */
354 
355 #ifndef IFXSCU_CFG_PLL_STEPS_8MHZ_160MHZ
356 /** \brief Macro for Pll step for profile with 8MHz Crystal and 160MHz target */
357 #define IFXSCU_CFG_PLL_STEPS_8MHZ_160MHZ \
358  { /*Step 0 Config: 100MHz*/ \
359  (4 - 1), /*uint8 k2Step;*/ \
360  0.000100, /*float32 waitTime;*/ \
361  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
362  }, \
363  { /*Step 1 Config: 160MHz*/ \
364  (3 - 1), /*uint8 k2Step;*/ \
365  0.000100, /*float32 waitTime;*/ \
366  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
367  },
368 #endif /*#ifndef IFXSCU_CFG_PLL_STEPS_8MHZ_160MHZ */
369 
370 #ifndef IFXSCU_CFG_PLL_STEPS_8MHZ_200MHZ
371 /** \brief Macro for Pll step for profile with 8MHz Crystal and 200MHz target */
372 #define IFXSCU_CFG_PLL_STEPS_8MHZ_200MHZ \
373  { /*Step 0 Config: 120MHz*/ \
374  (5 - 1), /*uint8 k2Step;*/ \
375  0.000100, /*float32 waitTime;*/ \
376  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
377  }, \
378  { /*Step 0 Config: 150MHz*/ \
379  (4 - 1), /*uint8 k2Step;*/ \
380  0.000100, /*float32 waitTime;*/ \
381  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
382  }, \
383  { /*Step 1 Config: 200MHz*/ \
384  (3 - 1), /*uint8 k2Step;*/ \
385  0.000100, /*float32 waitTime;*/ \
386  0 /*IfxScu_PllStepsFunctionHook hookFunction;*/ \
387  },
388 #endif /*#ifndef IFXSCU_CFG_PLL_STEPS_8MHZ_200MHZ */
389 
390 /** \brief Macros to configure Initial Pll step.
391  * Macros to configure the Pll initial step, where the configuration of PDIV, NDIV and K2DIV are
392  * done for the internal Oscillator frequency.
393  * \ref IfxScuCcu_InitialStepConfig
394  */
395 
396 /****************** Initial Pll step for 16MHz crystal Configurations ******************************/
397 
398 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_80MHZ
399 /** \brief Macro for Initial Pll step, for profile with 16MHz Crystal and 80MHz target */
400 #define IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_80MHZ \
401 /*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/ \
402  {(1 - 1), (40 - 1), (7 - 1), 0.000200F}
403 #endif /*#ifndef IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_80MHZ */
404 
405 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_133MHZ
406 /** \brief Macro for Initial Pll step, for profile with 16MHz Crystal and 133MHz target */
407 #define IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_133MHZ \
408 /*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/ \
409  {(1 - 1), (50 - 1), (8 - 1), 0.000200F}
410 #endif /*#ifndef IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_133MHZ */
411 
412 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_160MHZ
413 /** \brief Macro for Initial Pll step, for profile with 16MHz Crystal and 160MHz target */
414 #define IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_160MHZ \
415 /*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/ \
416  {(1 - 1), (40 - 1), (6 - 1), 0.000200F}
417 #endif /*#ifndef IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_160MHZ */
418 
419 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_200MHZ
420 /** \brief Macro for Initial Pll step, for profile with 16MHz Crystal and 200MHz target */
421 #define IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_200MHZ \
422 /*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/ \
423  {(1 - 1), (50 - 1), (8 - 1), 0.000200F}
424 #endif /*#ifndef IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_200MHZ */
425 
426 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_240MHZ
427 /** \brief Macro for Initial Pll step, for profile with 16MHz Crystal and 240MHz target */
428 #define IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_240MHZ \
429 /*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/ \
430  {(1 - 1), (45 - 1), (7 - 1), 0.000200F}
431 #endif /*#ifndef IFXSCU_CFG_PLL_INITIAL_STEP_16MHZ_240MHZ */
432 
433 /****************** Initial Pll step for 20MHz crystal Configurations ******************************/
434 
435 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_80MHZ
436 /** \brief Macro for Initial Pll step, for profile with 20MHz Crystal and 80MHz target */
437 #define IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_80MHZ \
438 /*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/ \
439  {(2 - 1), (64 - 1), (7 - 1), 0.000200F}
440 #endif /*#ifndef IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_80MHZ */
441 
442 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_133MHZ
443 /** \brief Macro for Initial Pll step, for profile with 20MHz Crystal and 133MHz target */
444 #define IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_133MHZ \
445 /*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/ \
446  {(2 - 1), (80 - 1), (8 - 1), 0.000200F}
447 #endif /*#ifndef IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_133MHZ */
448 
449 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_160MHZ
450 /** \brief Macro for Initial Pll step, for profile with 20MHz Crystal and 160MHz target */
451 #define IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_160MHZ \
452 /*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/ \
453  {(2 - 1), (64 - 1), (6 - 1), 0.000200F}
454 #endif /*#ifndef IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_160MHZ */
455 
456 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_200MHZ
457 /** \brief Macro for Initial Pll step, for profile with 20MHz Crystal and 200MHz target */
458 #define IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_200MHZ \
459 /*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/ \
460  {(2 - 1), (60 - 1), (6 - 1), 0.000200F}
461 #endif /*#ifndef IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_200MHZ */
462 
463 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_240MHZ
464 /** \brief Macro for Initial Pll step, for profile with 20MHz Crystal and 240MHz target */
465 #define IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_240MHZ \
466 /*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/ \
467  {(2 - 1), (72 - 1), (7 - 1), 0.000200F}
468 #endif /*#ifndef IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_240MHZ */
469 
470 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_300MHZ
471 /** \brief Macro for Initial Pll step, for profile with 20MHz Crystal and 300MHz target */
472 #define IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_300MHZ \
473 /*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/ \
474  {(2 - 1), (60 - 1), (6 - 1), 0.000200F}
475 #endif /*#ifndef IFXSCU_CFG_PLL_INITIAL_STEP_20MHZ_300MHZ */
476 
477 /****************** Initial Pll step for 40MHz crystal Configurations ******************************/
478 
479 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_80MHZ
480 /** \brief Macro for Initial Pll step, for profile with 40MHz Crystal and 80MHz target */
481 #define IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_80MHZ \
482 /*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/ \
483  {(4 - 1), (64 - 1), (7 - 1), 0.000200F}
484 #endif /*#ifndef IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_80MHZ */
485 
486 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_133MHZ
487 /** \brief Macro for Initial Pll step, for profile with 40MHz Crystal and 133MHz target */
488 #define IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_133MHZ \
489 /*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/ \
490  {(4 - 1), (80 - 1), (8 - 1), 0.000200F}
491 #endif /*#ifndef IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_133MHZ */
492 
493 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_160MHZ
494 /** \brief Macro for Initial Pll step, for profile with 40MHz Crystal and 160MHz target */
495 #define IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_160MHZ \
496 /*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/ \
497  {(4 - 1), (64 - 1), (6 - 1), 0.000200F}
498 #endif /*#ifndef IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_160MHZ */
499 
500 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_200MHZ
501 /** \brief Macro for Initial Pll step, for profile with 40MHz Crystal and 200MHz target */
502 #define IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_200MHZ \
503 /*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/ \
504  {(4 - 1), (60 - 1), (6 - 1), 0.000200F}
505 #endif /*#ifndef IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_200MHZ */
506 
507 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_240MHZ
508 /** \brief Macro for Initial Pll step, for profile with 40MHz Crystal and 240MHz target */
509 #define IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_240MHZ \
510 /*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/ \
511  {(4 - 1), (72 - 1), (7 - 1), 0.000200F}
512 #endif /*#ifndef IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_240MHZ */
513 
514 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_300MHZ
515 /** \brief Macro for Initial Pll step, for profile with 40MHz Crystal and 300MHz target */
516 #define IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_300MHZ \
517 /*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/ \
518  {(4 - 1), (60 - 1), (6 - 1), 0.000200F}
519 #endif /*#ifndef IFXSCU_CFG_PLL_INITIAL_STEP_40MHZ_300MHZ */
520 
521 
522 /****************** Initial Pll step for 8MHz crystal Configurations ******************************/
523 
524 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_8MHZ_80MHZ
525 /** \brief Macro for Initial Pll step, for profile with 8MHz Crystal and 80MHz target */
526 #define IFXSCU_CFG_PLL_INITIAL_STEP_8MHZ_80MHZ \
527 /*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime } ??*/ \
528  {(1 - 1), (50 - 1), (5 - 1), 0.000200F}
529 #endif /*#ifndef IFXSCU_CFG_PLL_INITIAL_STEP_8MHZ_80MHZ */
530 
531 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_8MHZ_160MHZ
532 /** \brief Macro for Initial Pll step, for profile with 8MHz Crystal and 160MHz target */
533 #define IFXSCU_CFG_PLL_INITIAL_STEP_8MHZ_160MHZ \
534 /*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/ \
535  {(1 - 1), (60 - 1), (5 - 1), 0.000200F}
536 #endif /*#ifndef IFXSCU_CFG_PLL_INITIAL_STEP_8MHZ_160MHZ */
537 
538 #ifndef IFXSCU_CFG_PLL_INITIAL_STEP_8MHZ_200MHZ
539 /** \brief Macro for Initial Pll step, for profile with 8MHz Crystal and 200MHz target */
540 #define IFXSCU_CFG_PLL_INITIAL_STEP_8MHZ_200MHZ \
541 /*{ uint8 pDivider, uint8 nDivider, uint8 k2Initial, float32 waitTime }*/ \
542  {(1 - 1), (75 - 1), (6 - 1), 0.000200F}
543 #endif /*#ifndef IFXSCU_CFG_PLL_INITIAL_STEP_8MHZ_200MHZ */
544 
545 
546 /** \brief Macros to configure CCUCON registers.
547  * Macros to configure the Pll initial step, where the configuration of PDIV, NDIV and K2DIV are
548  * done for the internal Oscillator frequency.
549  * \ref IfxScuCcu_InitialStepConfig
550  */
551 
552 /** \brief Macros to configure CCUCON registers */
553 
554 #ifndef IFXSCU_CFG_MAXDIV_80MHZ
555 /** \brief Macro to configure MAXDIV at 80MHz target frequency */
556 #define IFXSCU_CFG_MAXDIV_80MHZ (1)
557 #endif /*#ifndef IFXSCU_CFG_MAXDIV_80MHZ */
558 
559 #ifndef IFXSCU_CFG_MAXDIV_133MHZ
560 /** \brief Macro to configure MAXDIV at 133MHz target frequency */
561 #define IFXSCU_CFG_MAXDIV_133MHZ (1)
562 #endif /*#ifndef IFXSCU_CFG_MAXDIV_133MHZ */
563 
564 #ifndef IFXSCU_CFG_MAXDIV_160MHZ
565 /** \brief Macro to configure MAXDIV at 160MHz target frequency */
566 #define IFXSCU_CFG_MAXDIV_160MHZ (1)
567 #endif /*#ifndef IFXSCU_CFG_MAXDIV_160MHZ */
568 
569 #ifndef IFXSCU_CFG_MAXDIV_200MHZ
570 /** \brief Macro to configure MAXDIV at 200MHz target frequency */
571 #define IFXSCU_CFG_MAXDIV_200MHZ (1)
572 #endif /*#ifndef IFXSCU_CFG_MAXDIV_200MHZ */
573 
574 #ifndef IFXSCU_CFG_MAXDIV_240MHZ
575 /** \brief Macro to configure MAXDIV at 240MHz target frequency */
576 #define IFXSCU_CFG_MAXDIV_240MHZ (1)
577 #endif /*#ifndef IFXSCU_CFG_MAXDIV_240MHZ */
578 
579 #ifndef IFXSCU_CFG_MAXDIV_300MHZ
580 /** \brief Macro to configure MAXDIV at 300MHz target frequency */
581 #define IFXSCU_CFG_MAXDIV_300MHZ (1)
582 #endif /*#ifndef IFXSCU_CFG_MAXDIV_300MHZ */
583 
584 #ifndef IFXSCU_CFG_SRIDIV_80MHZ
585 /** \brief Macro to configure SRIDIV at 80MHz target frequency */
586 #define IFXSCU_CFG_SRIDIV_80MHZ (IFXSCU_CFG_MAXDIV_80MHZ) /*Same as MAXDIV */
587 #endif /*#ifndef IFXSCU_CFG_SRIDIV_80MHZ */
588 
589 #ifndef IFXSCU_CFG_SRIDIV_133MHZ
590 /** \brief Macro to configure SRIDIV at 133MHz target frequency */
591 #define IFXSCU_CFG_SRIDIV_133MHZ (IFXSCU_CFG_MAXDIV_133MHZ) /*Same as MAXDIV */
592 #endif /*#ifndef IFXSCU_CFG_SRIDIV_133MHZ */
593 
594 #ifndef IFXSCU_CFG_SRIDIV_160MHZ
595 /** \brief Macro to configure SRIDIV at 160MHz target frequency */
596 #define IFXSCU_CFG_SRIDIV_160MHZ (IFXSCU_CFG_MAXDIV_160MHZ) /*Same as MAXDIV */
597 #endif /*#ifndef IFXSCU_CFG_SRIDIV_160MHZ */
598 
599 #ifndef IFXSCU_CFG_SRIDIV_200MHZ
600 /** \brief Macro to configure SRIDIV at 200MHz target frequency */
601 #define IFXSCU_CFG_SRIDIV_200MHZ (IFXSCU_CFG_MAXDIV_200MHZ) /*Same as MAXDIV */
602 #endif /*#ifndef IFXSCU_CFG_SRIDIV_200MHZ */
603 
604 #ifndef IFXSCU_CFG_SRIDIV_240MHZ
605 /** \brief Macro to configure SRIDIV at 240MHz target frequency */
606 #define IFXSCU_CFG_SRIDIV_240MHZ (IFXSCU_CFG_MAXDIV_240MHZ) /*Same as MAXDIV */
607 #endif /*#ifndef IFXSCU_CFG_SRIDIV_240MHZ */
608 
609 #ifndef IFXSCU_CFG_SRIDIV_300MHZ
610 /** \brief Macro to configure SRIDIV at 300MHz target frequency */
611 #define IFXSCU_CFG_SRIDIV_300MHZ (IFXSCU_CFG_MAXDIV_300MHZ) /*Same as MAXDIV */
612 #endif /*#ifndef IFXSCU_CFG_SRIDIV_300MHZ */
613 
614 #ifndef IFXSCU_CFG_BAUD1DIV_80MHZ
615 /** \brief Macro to configure BAUD1DIV at 80MHz target frequency */
616 #define IFXSCU_CFG_BAUD1DIV_80MHZ (IFXSCU_CFG_MAXDIV_80MHZ) /*Max: 100MHz */
617 #endif /*#ifndef IFXSCU_CFG_BAUD1DIV_80MHZ */
618 
619 #ifndef IFXSCU_CFG_BAUD1DIV_133MHZ
620 /** \brief Macro to configure BAUD1DIV at 133MHz target frequency */
621 #define IFXSCU_CFG_BAUD1DIV_133MHZ (IFXSCU_CFG_MAXDIV_133MHZ * 2) /*Max: 100MHz */
622 #endif /*#ifndef IFXSCU_CFG_BAUD1DIV_133MHZ */
623 
624 #ifndef IFXSCU_CFG_BAUD1DIV_160MHZ
625 /** \brief Macro to configure BAUD1DIV at 160MHz target frequency */
626 #define IFXSCU_CFG_BAUD1DIV_160MHZ (IFXSCU_CFG_MAXDIV_160MHZ * 2) /*Max: 100MHz */
627 #endif /*#ifndef IFXSCU_CFG_BAUD1DIV_160MHZ */
628 
629 #ifndef IFXSCU_CFG_BAUD1DIV_200MHZ
630 /** \brief Macro to configure BAUD1DIV at 200MHz target frequency */
631 #define IFXSCU_CFG_BAUD1DIV_200MHZ (IFXSCU_CFG_MAXDIV_200MHZ * 2) /*Max: 100MHz */
632 #endif /*#ifndef IFXSCU_CFG_BAUD1DIV_200MHZ */
633 
634 #ifndef IFXSCU_CFG_BAUD1DIV_240MHZ
635 /** \brief Macro to configure BAUD1DIV at 240MHz target frequency */
636 #define IFXSCU_CFG_BAUD1DIV_240MHZ (IFXSCU_CFG_MAXDIV_240MHZ * 3) /*Max: 100MHz */
637 #endif /*#ifndef IFXSCU_CFG_BAUD1DIV_240MHZ */
638 
639 #ifndef IFXSCU_CFG_BAUD1DIV_300MHZ
640 /** \brief Macro to configure BAUD1DIV at 300MHz target frequency */
641 #define IFXSCU_CFG_BAUD1DIV_300MHZ (IFXSCU_CFG_MAXDIV_300MHZ * 3) /*Max: 100MHz */
642 #endif /*#ifndef IFXSCU_CFG_BAUD1DIV_300MHZ */
643 
644 #ifndef IFXSCU_CFG_BAUD2DIV_80MHZ
645 /** \brief Macro to configure BAUD2DIV at 80MHz target frequency */
646 #define IFXSCU_CFG_BAUD2DIV_80MHZ (IFXSCU_CFG_MAXDIV_80MHZ) /*Same as MAXDIV */
647 #endif /*#ifndef IFXSCU_CFG_BAUD2DIV_80MHZ */
648 
649 #ifndef IFXSCU_CFG_BAUD2DIV_133MHZ
650 /** \brief Macro to configure BAUD2DIV at 133MHz target frequency */
651 #define IFXSCU_CFG_BAUD2DIV_133MHZ (IFXSCU_CFG_MAXDIV_133MHZ) /*Same as MAXDIV */
652 #endif /*#ifndef IFXSCU_CFG_BAUD2DIV_133MHZ */
653 
654 #ifndef IFXSCU_CFG_BAUD2DIV_160MHZ
655 /** \brief Macro to configure BAUD2DIV at 160MHz target frequency */
656 #define IFXSCU_CFG_BAUD2DIV_160MHZ (IFXSCU_CFG_MAXDIV_160MHZ) /*Same as MAXDIV */
657 #endif /*#ifndef IFXSCU_CFG_BAUD2DIV_160MHZ */
658 
659 #ifndef IFXSCU_CFG_BAUD2DIV_200MHZ
660 /** \brief Macro to configure BAUD2DIV at 200MHz target frequency */
661 #define IFXSCU_CFG_BAUD2DIV_200MHZ (IFXSCU_CFG_MAXDIV_200MHZ) /*Same as MAXDIV */
662 #endif /*#ifndef IFXSCU_CFG_BAUD2DIV_200MHZ */
663 
664 #ifndef IFXSCU_CFG_BAUD2DIV_240MHZ
665 /** \brief Macro to configure BAUD2DIV at 240MHz target frequency */
666 #define IFXSCU_CFG_BAUD2DIV_240MHZ (IFXSCU_CFG_MAXDIV_240MHZ) /*Same as MAXDIV */
667 #endif /*#ifndef IFXSCU_CFG_BAUD2DIV_240MHZ */
668 
669 #ifndef IFXSCU_CFG_BAUD2DIV_300MHZ
670 /** \brief Macro to configure BAUD2DIV at 300MHz target frequency */
671 #define IFXSCU_CFG_BAUD2DIV_300MHZ (IFXSCU_CFG_MAXDIV_300MHZ) /*Same as MAXDIV */
672 #endif /*#ifndef IFXSCU_CFG_BAUD2DIV_300MHZ */
673 
674 #ifndef IFXSCU_CFG_SPBDIV_80MHZ
675 /** \brief Macro to configure SPBDIV at 80MHz target frequency */
676 #define IFXSCU_CFG_SPBDIV_80MHZ (IFXSCU_CFG_MAXDIV_80MHZ) /*Max: 100MHz */
677 #endif /*#ifndef IFXSCU_CFG_SPBDIV_80MHZ */
678 
679 #ifndef IFXSCU_CFG_SPBDIV_133MHZ
680 /** \brief Macro to configure SPBDIV at 133MHz target frequency */
681 #define IFXSCU_CFG_SPBDIV_133MHZ (IFXSCU_CFG_MAXDIV_133MHZ * 2) /*Max: 100MHz */
682 #endif /*#ifndef IFXSCU_CFG_SPBDIV_133MHZ */
683 
684 #ifndef IFXSCU_CFG_SPBDIV_160MHZ
685 /** \brief Macro to configure SPBDIV at 160MHz target frequency */
686 #define IFXSCU_CFG_SPBDIV_160MHZ (IFXSCU_CFG_MAXDIV_160MHZ * 2) /*Max: 100MHz */
687 #endif /*#ifndef IFXSCU_CFG_SPBDIV_160MHZ */
688 
689 #ifndef IFXSCU_CFG_SPBDIV_200MHZ
690 /** \brief Macro to configure SPBDIV at 200MHz target frequency */
691 #define IFXSCU_CFG_SPBDIV_200MHZ (IFXSCU_CFG_MAXDIV_200MHZ * 2) /*Max: 100MHz */
692 #endif /*#ifndef IFXSCU_CFG_SPBDIV_200MHZ */
693 
694 #ifndef IFXSCU_CFG_SPBDIV_240MHZ
695 /** \brief Macro to configure SPBDIV at 240MHz target frequency */
696 #define IFXSCU_CFG_SPBDIV_240MHZ (IFXSCU_CFG_MAXDIV_240MHZ * 3) /*Max: 100MHz */
697 #endif /*#ifndef IFXSCU_CFG_SPBDIV_240MHZ */
698 
699 #ifndef IFXSCU_CFG_SPBDIV_300MHZ
700 /** \brief Macro to configure SPBDIV at 300MHz target frequency */
701 #define IFXSCU_CFG_SPBDIV_300MHZ (IFXSCU_CFG_MAXDIV_300MHZ * 3) /*Max: 100MHz */
702 #endif /*#ifndef IFXSCU_CFG_SPBDIV_300MHZ */
703 
704 #ifndef IFXSCU_CFG_FSI2DIV_80MHZ
705 /** \brief Macro to configure FSI2DIV at 80MHz target frequency */
706 #define IFXSCU_CFG_FSI2DIV_80MHZ (IFXSCU_CFG_MAXDIV_80MHZ) /*Same as MAXDIV */
707 #endif /*#ifndef IFXSCU_CFG_FSI2DIV_80MHZ */
708 
709 #ifndef IFXSCU_CFG_FSI2DIV_133MHZ
710 /** \brief Macro to configure FSI2DIV at 133MHz target frequency */
711 #define IFXSCU_CFG_FSI2DIV_133MHZ (IFXSCU_CFG_MAXDIV_133MHZ) /*Same as MAXDIV */
712 #endif /*#ifndef IFXSCU_CFG_FSI2DIV_133MHZ */
713 
714 #ifndef IFXSCU_CFG_FSI2DIV_160MHZ
715 /** \brief Macro to configure FSI2DIV at 160MHz target frequency */
716 #define IFXSCU_CFG_FSI2DIV_160MHZ (IFXSCU_CFG_MAXDIV_160MHZ) /*Same as MAXDIV */
717 #endif /*#ifndef IFXSCU_CFG_FSI2DIV_160MHZ */
718 
719 #ifndef IFXSCU_CFG_FSI2DIV_200MHZ
720 /** \brief Macro to configure FSI2DIV at 200MHz target frequency */
721 #define IFXSCU_CFG_FSI2DIV_200MHZ (IFXSCU_CFG_MAXDIV_200MHZ) /*Same as MAXDIV */
722 #endif /*#ifndef IFXSCU_CFG_FSI2DIV_200MHZ */
723 
724 #ifndef IFXSCU_CFG_FSI2DIV_240MHZ
725 /** \brief Macro to configure FSI2DIV at 240MHz target frequency */
726 #define IFXSCU_CFG_FSI2DIV_240MHZ (IFXSCU_CFG_MAXDIV_240MHZ) /*Same as MAXDIV */
727 #endif /*#ifndef IFXSCU_CFG_FSI2DIV_240MHZ */
728 
729 #ifndef IFXSCU_CFG_FSI2DIV_300MHZ
730 /** \brief Macro to configure FSI2DIV at 300MHz target frequency */
731 #define IFXSCU_CFG_FSI2DIV_300MHZ (IFXSCU_CFG_MAXDIV_300MHZ) /*Same as MAXDIV */
732 #endif /*#ifndef IFXSCU_CFG_FSI2DIV_300MHZ */
733 
734 #ifndef IFXSCU_CFG_FSIDIV_80MHZ
735 /** \brief Macro to configure FSIDIV at 80MHz target frequency */
736 #define IFXSCU_CFG_FSIDIV_80MHZ (IFXSCU_CFG_MAXDIV_80MHZ) /*Max: 100MHz */
737 #endif /*#ifndef IFXSCU_CFG_FSIDIV_80MHZ */
738 
739 #ifndef IFXSCU_CFG_FSIDIV_133MHZ
740 /** \brief Macro to configure FSIDIV at 133MHz target frequency */
741 #define IFXSCU_CFG_FSIDIV_133MHZ (IFXSCU_CFG_MAXDIV_133MHZ * 2) /*Max: 100MHz */
742 #endif /*#ifndef IFXSCU_CFG_FSIDIV_133MHZ */
743 
744 #ifndef IFXSCU_CFG_FSIDIV_160MHZ
745 /** \brief Macro to configure FSIDIV at 160MHz target frequency */
746 #define IFXSCU_CFG_FSIDIV_160MHZ (IFXSCU_CFG_MAXDIV_160MHZ * 2) /*Max: 100MHz */
747 #endif /*#ifndef IFXSCU_CFG_FSIDIV_160MHZ */
748 
749 #ifndef IFXSCU_CFG_FSIDIV_200MHZ
750 /** \brief Macro to configure FSIDIV at 200MHz target frequency */
751 #define IFXSCU_CFG_FSIDIV_200MHZ (IFXSCU_CFG_MAXDIV_200MHZ * 2) /*Max: 100MHz */
752 #endif /*#ifndef IFXSCU_CFG_FSIDIV_200MHZ */
753 
754 #ifndef IFXSCU_CFG_FSIDIV_240MHZ
755 /** \brief Macro to configure FSIDIV at 240MHz target frequency */
756 #define IFXSCU_CFG_FSIDIV_240MHZ (IFXSCU_CFG_MAXDIV_240MHZ * 2) /*Max: 100MHz */
757 #endif /*#ifndef IFXSCU_CFG_FSIDIV_240MHZ */
758 
759 #ifndef IFXSCU_CFG_FSIDIV_300MHZ
760 /** \brief Macro to configure FSIDIV at 300MHz target frequency */
761 #define IFXSCU_CFG_FSIDIV_300MHZ (IFXSCU_CFG_MAXDIV_300MHZ * 2) /*Max: 100MHz */
762 #endif /*#ifndef IFXSCU_CFG_FSIDIV_300MHZ */
763 
764 #ifndef IFXSCU_CFG_CANDIV_80MHZ
765 /** \brief Macro to configure CANDIV at 80MHz target frequency */
766 #define IFXSCU_CFG_CANDIV_80MHZ (IFXSCU_CFG_MAXDIV_80MHZ) /*Max: 100MHz */
767 #endif /*#ifndef IFXSCU_CFG_CANDIV_80MHZ */
768 
769 #ifndef IFXSCU_CFG_CANDIV_133MHZ
770 /** \brief Macro to configure CANDIV at 133MHz target frequency */
771 #define IFXSCU_CFG_CANDIV_133MHZ (IFXSCU_CFG_MAXDIV_133MHZ * 2) /*Max: 100MHz */
772 #endif /*#ifndef IFXSCU_CFG_CANDIV_133MHZ */
773 
774 #ifndef IFXSCU_CFG_CANDIV_160MHZ
775 /** \brief Macro to configure CANDIV at 160MHz target frequency */
776 #define IFXSCU_CFG_CANDIV_160MHZ (IFXSCU_CFG_MAXDIV_160MHZ * 2) /*Max: 100MHz */
777 #endif /*#ifndef IFXSCU_CFG_CANDIV_160MHZ */
778 
779 #ifndef IFXSCU_CFG_CANDIV_200MHZ
780 /** \brief Macro to configure CANDIV at 200MHz target frequency */
781 #define IFXSCU_CFG_CANDIV_200MHZ (IFXSCU_CFG_MAXDIV_200MHZ * 2) /*Max: 100MHz */
782 #endif /*#ifndef IFXSCU_CFG_CANDIV_200MHZ */
783 
784 #ifndef IFXSCU_CFG_CANDIV_240MHZ
785 /** \brief Macro to configure CANDIV at 240MHz target frequency */
786 #define IFXSCU_CFG_CANDIV_240MHZ (IFXSCU_CFG_MAXDIV_240MHZ * 3) /*Max: 100MHz */
787 #endif /*#ifndef IFXSCU_CFG_CANDIV_240MHZ */
788 
789 #ifndef IFXSCU_CFG_CANDIV_300MHZ
790 /** \brief Macro to configure CANDIV at 200MHz target frequency */
791 #define IFXSCU_CFG_CANDIV_300MHZ (IFXSCU_CFG_MAXDIV_300MHZ * 3) /*Max: 100MHz */
792 #endif /*#ifndef IFXSCU_CFG_CANDIV_300MHZ */
793 
794 #ifndef IFXSCU_CFG_ERAYDIV_80MHZ
795 /** \brief Macro to configure ERAYDIV at 80MHz target frequency */
796 #define IFXSCU_CFG_ERAYDIV_80MHZ (IFXSCU_CFG_MAXDIV_80MHZ) /*Max: 80MHz */
797 #endif /*#ifndef IFXSCU_CFG_ERAYDIV_80MHZ */
798 
799 #ifndef IFXSCU_CFG_ERAYDIV_133MHZ
800 /** \brief Macro to configure ERAYDIV at 133MHz target frequency */
801 #define IFXSCU_CFG_ERAYDIV_133MHZ (IFXSCU_CFG_MAXDIV_133MHZ * 2) /*Max: 80MHz */
802 #endif /*#ifndef IFXSCU_CFG_ERAYDIV_133MHZ */
803 
804 #ifndef IFXSCU_CFG_ERAYDIV_160MHZ
805 /** \brief Macro to configure ERAYDIV at 160MHz target frequency */
806 #define IFXSCU_CFG_ERAYDIV_160MHZ (IFXSCU_CFG_MAXDIV_160MHZ * 2) /*Max: 80MHz */
807 #endif /*#ifndef IFXSCU_CFG_ERAYDIV_160MHZ */
808 
809 #ifndef IFXSCU_CFG_ERAYDIV_200MHZ
810 /** \brief Macro to configure ERAYDIV at 200MHz target frequency */
811 #define IFXSCU_CFG_ERAYDIV_200MHZ (IFXSCU_CFG_MAXDIV_200MHZ * 3) /*Max: 80MHz */
812 #endif /*#ifndef IFXSCU_CFG_ERAYDIV_200MHZ */
813 
814 #ifndef IFXSCU_CFG_ERAYDIV_240MHZ
815 /** \brief Macro to configure ERAYDIV at 200MHz target frequency */
816 #define IFXSCU_CFG_ERAYDIV_240MHZ (IFXSCU_CFG_MAXDIV_240MHZ * 3) /*Max: 80MHz */
817 #endif /*#ifndef IFXSCU_CFG_ERAYDIV_240MHZ */
818 
819 #ifndef IFXSCU_CFG_ERAYDIV_300MHZ
820 /** \brief Macro to configure ERAYDIV at 300MHz target frequency */
821 #define IFXSCU_CFG_ERAYDIV_300MHZ (IFXSCU_CFG_MAXDIV_300MHZ * 4) /*Max: 80MHz */
822 #endif /*#ifndef IFXSCU_CFG_ERAYDIV_300MHZ */
823 
824 #ifndef IFXSCU_CFG_STMDIV_80MHZ
825 /** \brief Macro to configure STMDIV at 80MHz target frequency */
826 #define IFXSCU_CFG_STMDIV_80MHZ (IFXSCU_CFG_MAXDIV_80MHZ) /*Max: 100MHz */
827 #endif /*#ifndef IFXSCU_CFG_STMDIV_80MHZ */
828 
829 #ifndef IFXSCU_CFG_STMDIV_133MHZ
830 /** \brief Macro to configure STMDIV at 133MHz target frequency */
831 #define IFXSCU_CFG_STMDIV_133MHZ (IFXSCU_CFG_MAXDIV_133MHZ * 2) /*Max: 100MHz */
832 #endif /*#ifndef IFXSCU_CFG_STMDIV_133MHZ */
833 
834 #ifndef IFXSCU_CFG_STMDIV_160MHZ
835 /** \brief Macro to configure STMDIV at 160MHz target frequency */
836 #define IFXSCU_CFG_STMDIV_160MHZ (IFXSCU_CFG_MAXDIV_160MHZ * 2) /*Max: 100MHz */
837 #endif /*#ifndef IFXSCU_CFG_STMDIV_160MHZ */
838 
839 #ifndef IFXSCU_CFG_STMDIV_200MHZ
840 /** \brief Macro to configure STMDIV at 200MHz target frequency */
841 #define IFXSCU_CFG_STMDIV_200MHZ (IFXSCU_CFG_MAXDIV_200MHZ * 2) /*Max: 100MHz */
842 #endif /*#ifndef IFXSCU_CFG_STMDIV_200MHZ */
843 
844 #ifndef IFXSCU_CFG_STMDIV_240MHZ
845 /** \brief Macro to configure STMDIV at 240MHz target frequency */
846 #define IFXSCU_CFG_STMDIV_240MHZ (IFXSCU_CFG_MAXDIV_240MHZ * 3) /*Max: 100MHz */
847 #endif /*#ifndef IFXSCU_CFG_STMDIV_240MHZ */
848 
849 #ifndef IFXSCU_CFG_STMDIV_300MHZ
850 /** \brief Macro to configure STMDIV at 300MHz target frequency */
851 #define IFXSCU_CFG_STMDIV_300MHZ (IFXSCU_CFG_MAXDIV_300MHZ * 3) /*Max: 100MHz */
852 #endif /*#ifndef IFXSCU_CFG_STMDIV_300MHZ */
853 
854 #ifndef IFXSCU_CFG_GTMDIV_80MHZ
855 /** \brief Macro to configure GTMDIV at 80MHz target frequency */
856 #define IFXSCU_CFG_GTMDIV_80MHZ (IFXSCU_CFG_MAXDIV_80MHZ) /*Max: 100MHz */
857 #endif /*#ifndef IFXSCU_CFG_GTMDIV_80MHZ */
858 
859 #ifndef IFXSCU_CFG_GTMDIV_133MHZ
860 /** \brief Macro to configure GTMDIV at 133MHz target frequency */
861 #define IFXSCU_CFG_GTMDIV_133MHZ (IFXSCU_CFG_MAXDIV_133MHZ * 2) /*Max: 100MHz */
862 #endif /*#ifndef IFXSCU_CFG_GTMDIV_133MHZ */
863 
864 #ifndef IFXSCU_CFG_GTMDIV_160MHZ
865 /** \brief Macro to configure GTMDIV at 160MHz target frequency */
866 #define IFXSCU_CFG_GTMDIV_160MHZ (IFXSCU_CFG_MAXDIV_160MHZ * 2) /*Max: 100MHz */
867 #endif /*#ifndef IFXSCU_CFG_GTMDIV_160MHZ */
868 
869 #ifndef IFXSCU_CFG_GTMDIV_200MHZ
870 /** \brief Macro to configure GTMDIV at 200MHz target frequency */
871 #define IFXSCU_CFG_GTMDIV_200MHZ (IFXSCU_CFG_MAXDIV_200MHZ * 2) /*Max: 100MHz */
872 #endif /*#ifndef IFXSCU_CFG_GTMDIV_200MHZ */
873 
874 #ifndef IFXSCU_CFG_GTMDIV_240MHZ
875 /** \brief Macro to configure GTMDIV at 240MHz target frequency */
876 #define IFXSCU_CFG_GTMDIV_240MHZ (IFXSCU_CFG_MAXDIV_240MHZ * 3) /*Max: 100MHz */
877 #endif /*#ifndef IFXSCU_CFG_GTMDIV_240MHZ */
878 
879 #ifndef IFXSCU_CFG_GTMDIV_300MHZ
880 /** \brief Macro to configure GTMDIV at 300MHz target frequency */
881 #define IFXSCU_CFG_GTMDIV_300MHZ (IFXSCU_CFG_MAXDIV_300MHZ * 3) /*Max: 100MHz */
882 #endif /*#ifndef IFXSCU_CFG_GTMDIV_300MHZ */
883 
884 #ifndef IFXSCU_CFG_ETHDIV_80MHZ
885 /** \brief Macro to configure ETHDIV at 80MHz target frequency */
886 #define IFXSCU_CFG_ETHDIV_80MHZ (IFXSCU_CFG_MAXDIV_80MHZ * 2)
887 #endif /*#ifndef IFXSCU_CFG_ETHDIV_80MHZ */
888 
889 #ifndef IFXSCU_CFG_ETHDIV_133MHZ
890 /** \brief Macro to configure ETHDIV at 133MHz target frequency */
891 #define IFXSCU_CFG_ETHDIV_133MHZ (IFXSCU_CFG_MAXDIV_133MHZ * 3)
892 #endif /*#ifndef IFXSCU_CFG_ETHDIV_133MHZ */
893 
894 #ifndef IFXSCU_CFG_ETHDIV_160MHZ
895 /** \brief Macro to configure ETHDIV at 160MHz target frequency */
896 #define IFXSCU_CFG_ETHDIV_160MHZ (IFXSCU_CFG_MAXDIV_160MHZ * 4)
897 #endif /*#ifndef IFXSCU_CFG_ETHDIV_160MHZ */
898 
899 #ifndef IFXSCU_CFG_ETHDIV_200MHZ
900 /** \brief Macro to configure ETHDIV at 200MHz target frequency */
901 #define IFXSCU_CFG_ETHDIV_200MHZ (IFXSCU_CFG_MAXDIV_200MHZ * 4)
902 #endif /*#ifndef IFXSCU_CFG_ETHDIV_200MHZ */
903 
904 #ifndef IFXSCU_CFG_ETHDIV_240MHZ
905 /** \brief Macro to configure ETHDIV at 240MHz target frequency */
906 #define IFXSCU_CFG_ETHDIV_240MHZ (IFXSCU_CFG_MAXDIV_240MHZ * 5)
907 #endif /*#ifndef IFXSCU_CFG_ETHDIV_240MHZ */
908 
909 #ifndef IFXSCU_CFG_ETHDIV_300MHZ
910 /** \brief Macro to configure ETHDIV at 300MHz target frequency */
911 #define IFXSCU_CFG_ETHDIV_300MHZ (IFXSCU_CFG_MAXDIV_300MHZ * 6)
912 #endif /*#ifndef IFXSCU_CFG_ETHDIV_300MHZ */
913 
914 #ifndef IFXSCU_CFG_ASCLINFDIV_80MHZ
915 /** \brief Macro to configure ASCLINFDIV at 80MHz target frequency */
916 #define IFXSCU_CFG_ASCLINFDIV_80MHZ (IFXSCU_CFG_MAXDIV_80MHZ) /*Same as MAXDIV */
917 #endif /*#ifndef IFXSCU_CFG_ASCLINFDIV_80MHZ */
918 
919 #ifndef IFXSCU_CFG_ASCLINFDIV_133MHZ
920 /** \brief Macro to configure ASCLINFDIV at 133MHz target frequency */
921 #define IFXSCU_CFG_ASCLINFDIV_133MHZ (IFXSCU_CFG_MAXDIV_133MHZ) /*Same as MAXDIV */
922 #endif /*#ifndef IFXSCU_CFG_ASCLINFDIV_133MHZ */
923 
924 #ifndef IFXSCU_CFG_ASCLINFDIV_160MHZ
925 /** \brief Macro to configure ASCLINFDIV at 160MHz target frequency */
926 #define IFXSCU_CFG_ASCLINFDIV_160MHZ (IFXSCU_CFG_MAXDIV_160MHZ) /*Same as MAXDIV */
927 #endif /*#ifndef IFXSCU_CFG_ASCLINFDIV_160MHZ */
928 
929 #ifndef IFXSCU_CFG_ASCLINFDIV_200MHZ
930 /** \brief Macro to configure ASCLINFDIV at 200MHz target frequency */
931 #define IFXSCU_CFG_ASCLINFDIV_200MHZ (IFXSCU_CFG_MAXDIV_200MHZ) /*Same as MAXDIV */
932 #endif /*#ifndef IFXSCU_CFG_ASCLINFDIV_200MHZ */
933 
934 #ifndef IFXSCU_CFG_ASCLINFDIV_240MHZ
935 /** \brief Macro to configure ASCLINFDIV at 240MHz target frequency */
936 #define IFXSCU_CFG_ASCLINFDIV_240MHZ (IFXSCU_CFG_MAXDIV_240MHZ) /*Same as MAXDIV */
937 #endif /*#ifndef IFXSCU_CFG_ASCLINFDIV_240MHZ */
938 
939 #ifndef IFXSCU_CFG_ASCLINFDIV_300MHZ
940 /** \brief Macro to configure ASCLINFDIV at 300MHz target frequency */
941 #define IFXSCU_CFG_ASCLINFDIV_300MHZ (IFXSCU_CFG_MAXDIV_300MHZ) /*Same as MAXDIV */
942 #endif /*#ifndef IFXSCU_CFG_ASCLINFDIV_300MHZ */
943 
944 #ifndef IFXSCU_CFG_ASCLINSDIV_80MHZ
945 /** \brief Macro to configure ASCLINSDIV at 80MHz target frequency */
946 #define IFXSCU_CFG_ASCLINSDIV_80MHZ (IFXSCU_CFG_MAXDIV_80MHZ) /*Max: 100MHz */
947 #endif /*#ifndef IFXSCU_CFG_ASCLINSDIV_80MHZ */
948 
949 #ifndef IFXSCU_CFG_ASCLINSDIV_133MHZ
950 /** \brief Macro to configure ASCLINSDIV at 133MHz target frequency */
951 #define IFXSCU_CFG_ASCLINSDIV_133MHZ (IFXSCU_CFG_MAXDIV_133MHZ * 2) /*Max: 100MHz */
952 #endif /*#ifndef IFXSCU_CFG_ASCLINSDIV_133MHZ */
953 
954 #ifndef IFXSCU_CFG_ASCLINSDIV_160MHZ
955 /** \brief Macro to configure ASCLINSDIV at 160MHz target frequency */
956 #define IFXSCU_CFG_ASCLINSDIV_160MHZ (IFXSCU_CFG_MAXDIV_160MHZ * 2) /*Max: 100MHz */
957 #endif /*#ifndef IFXSCU_CFG_ASCLINSDIV_160MHZ */
958 
959 #ifndef IFXSCU_CFG_ASCLINSDIV_200MHZ
960 /** \brief Macro to configure ASCLINSDIV at 200MHz target frequency */
961 #define IFXSCU_CFG_ASCLINSDIV_200MHZ (IFXSCU_CFG_MAXDIV_200MHZ * 2) /*Max: 100MHz */
962 #endif /*#ifndef IFXSCU_CFG_ASCLINSDIV_200MHZ */
963 
964 #ifndef IFXSCU_CFG_ASCLINSDIV_240MHZ
965 /** \brief Macro to configure ASCLINSDIV at 240MHz target frequency */
966 #define IFXSCU_CFG_ASCLINSDIV_240MHZ (IFXSCU_CFG_MAXDIV_240MHZ * 3) /*Max: 100MHz */
967 #endif /*#ifndef IFXSCU_CFG_ASCLINSDIV_240MHZ */
968 
969 #ifndef IFXSCU_CFG_ASCLINSDIV_300MHZ
970 /** \brief Macro to configure ASCLINSDIV at 300MHz target frequency */
971 #define IFXSCU_CFG_ASCLINSDIV_300MHZ (IFXSCU_CFG_MAXDIV_300MHZ * 3) /*Max: 100MHz */
972 #endif /*#ifndef IFXSCU_CFG_ASCLINSDIV_200MHZ */
973 
974 #ifndef IFXSCU_CFG_BBBDIV_80MHZ
975 /** \brief Macro to configure BBBDIV at 80MHz target frequency */
976 #define IFXSCU_CFG_BBBDIV_80MHZ (IFXSCU_CFG_SRIDIV_80MHZ * 2)
977 #endif /*#ifndef IFXSCU_CFG_BBBDIV_80MHZ */
978 
979 #ifndef IFXSCU_CFG_BBBDIV_133MHZ
980 /** \brief Macro to configure BBBDIV at 133MHz target frequency */
981 #define IFXSCU_CFG_BBBDIV_133MHZ (IFXSCU_CFG_SRIDIV_133MHZ * 2)
982 #endif /*#ifndef IFXSCU_CFG_BBBDIV_133MHZ */
983 
984 #ifndef IFXSCU_CFG_BBBDIV_160MHZ
985 /** \brief Macro to configure BBBDIV at 160MHz target frequency */
986 #define IFXSCU_CFG_BBBDIV_160MHZ (IFXSCU_CFG_SRIDIV_160MHZ * 2)
987 #endif /*#ifndef IFXSCU_CFG_BBBDIV_160MHZ */
988 
989 #ifndef IFXSCU_CFG_BBBDIV_200MHZ
990 /** \brief Macro to configure BBBDIV at 200MHz target frequency */
991 #define IFXSCU_CFG_BBBDIV_200MHZ (IFXSCU_CFG_SRIDIV_200MHZ * 2)
992 #endif /*#ifndef IFXSCU_CFG_BBBDIV_200MHZ */
993 
994 #ifndef IFXSCU_CFG_BBBDIV_240MHZ
995 /** \brief Macro to configure BBBDIV at 240MHz target frequency */
996 #define IFXSCU_CFG_BBBDIV_240MHZ (IFXSCU_CFG_SRIDIV_240MHZ * 2)
997 #endif /*#ifndef IFXSCU_CFG_BBBDIV_240MHZ */
998 
999 #ifndef IFXSCU_CFG_BBBDIV_300MHZ
1000 /** \brief Macro to configure BBBDIV at 300MHz target frequency */
1001 #define IFXSCU_CFG_BBBDIV_300MHZ (IFXSCU_CFG_SRIDIV_300MHZ * 2)
1002 #endif /*#ifndef IFXSCU_CFG_BBBDIV_300MHZ */
1003 
1004 #ifndef IFXSCU_CFG_CPU0DIV_80MHZ
1005 /** \brief Macro to configure CPU0DIV at 80MHz target frequency */
1006 #define IFXSCU_CFG_CPU0DIV_80MHZ (0) /*Same as SRIDIV */
1007 #endif /*#ifndef IFXSCU_CFG_CPU0DIV_80MHZ */
1008 
1009 #ifndef IFXSCU_CFG_CPU0DIV_133MHZ
1010 /** \brief Macro to configure CPU0DIV at 133MHz target frequency */
1011 #define IFXSCU_CFG_CPU0DIV_133MHZ (0) /*Same as SRIDIV */
1012 #endif /*#ifndef IFXSCU_CFG_CPU0DIV_133MHZ */
1013 
1014 #ifndef IFXSCU_CFG_CPU0DIV_160MHZ
1015 /** \brief Macro to configure CPU0DIV at 160MHz target frequency */
1016 #define IFXSCU_CFG_CPU0DIV_160MHZ (0) /*Same as SRIDIV */
1017 #endif /*#ifndef IFXSCU_CFG_CPU0DIV_160MHZ */
1018 
1019 #ifndef IFXSCU_CFG_CPU0DIV_200MHZ
1020 /** \brief Macro to configure CPU0DIV at 200MHz target frequency */
1021 #define IFXSCU_CFG_CPU0DIV_200MHZ (0) /*Same as SRIDIV */
1022 #endif /*#ifndef IFXSCU_CFG_CPU0DIV_200MHZ */
1023 
1024 #ifndef IFXSCU_CFG_CPU0DIV_240MHZ
1025 /** \brief Macro to configure CPU0DIV at 240MHz target frequency */
1026 #define IFXSCU_CFG_CPU0DIV_240MHZ (0) /*Same as SRIDIV */
1027 #endif /*#ifndef IFXSCU_CFG_CPU0DIV_240MHZ */
1028 
1029 #ifndef IFXSCU_CFG_CPU0DIV_300MHZ
1030 /** \brief Macro to configure CPU0DIV at 300MHz target frequency */
1031 #define IFXSCU_CFG_CPU0DIV_300MHZ (0) /*Same as SRIDIV */
1032 #endif /*#ifndef IFXSCU_CFG_CPU0DIV_300MHZ */
1033 
1034 #ifndef IFXSCU_CFG_CPU1DIV_80MHZ
1035 /** \brief Macro to configure CPU1DIV at 80MHz target frequency */
1036 #define IFXSCU_CFG_CPU1DIV_80MHZ (0) /*Same as SRIDIV */
1037 #endif /*#ifndef IFXSCU_CFG_CPU1DIV_80MHZ */
1038 
1039 #ifndef IFXSCU_CFG_CPU1DIV_133MHZ
1040 /** \brief Macro to configure CPU1DIV at 133MHz target frequency */
1041 #define IFXSCU_CFG_CPU1DIV_133MHZ (0) /*Same as SRIDIV */
1042 #endif /*#ifndef IFXSCU_CFG_CPU1DIV_133MHZ */
1043 
1044 #ifndef IFXSCU_CFG_CPU1DIV_160MHZ
1045 /** \brief Macro to configure CPU1DIV at 160MHz target frequency */
1046 #define IFXSCU_CFG_CPU1DIV_160MHZ (0) /*Same as SRIDIV */
1047 #endif /*#ifndef IFXSCU_CFG_CPU1DIV_160MHZ */
1048 
1049 #ifndef IFXSCU_CFG_CPU1DIV_200MHZ
1050 /** \brief Macro to configure CPU1DIV at 200MHz target frequency */
1051 #define IFXSCU_CFG_CPU1DIV_200MHZ (0) /*Same as SRIDIV */
1052 #endif /*#ifndef IFXSCU_CFG_CPU1DIV_200MHZ */
1053 
1054 #ifndef IFXSCU_CFG_CPU1DIV_240MHZ
1055 /** \brief Macro to configure CPU1DIV at 240MHz target frequency */
1056 #define IFXSCU_CFG_CPU1DIV_240MHZ (0) /*Same as SRIDIV */
1057 #endif /*#ifndef IFXSCU_CFG_CPU1DIV_240MHZ */
1058 
1059 #ifndef IFXSCU_CFG_CPU1DIV_300MHZ
1060 /** \brief Macro to configure CPU1DIV at 300MHz target frequency */
1061 #define IFXSCU_CFG_CPU1DIV_300MHZ (0) /*Same as SRIDIV */
1062 #endif /*#ifndef IFXSCU_CFG_CPU1DIV_300MHZ */
1063 
1064 #ifndef IFXSCU_CFG_CPU2DIV_80MHZ
1065 /** \brief Macro to configure CPU2DIV at 80MHz target frequency */
1066 #define IFXSCU_CFG_CPU2DIV_80MHZ (0) /*Same as SRIDIV */
1067 #endif /*#ifndef IFXSCU_CFG_CPU2DIV_80MHZ */
1068 
1069 #ifndef IFXSCU_CFG_CPU2DIV_133MHZ
1070 /** \brief Macro to configure CPU2DIV at 133MHz target frequency */
1071 #define IFXSCU_CFG_CPU2DIV_133MHZ (0) /*Same as SRIDIV */
1072 #endif /*#ifndef IFXSCU_CFG_CPU2DIV_133MHZ */
1073 
1074 #ifndef IFXSCU_CFG_CPU2DIV_160MHZ
1075 /** \brief Macro to configure CPU2DIV at 160MHz target frequency */
1076 #define IFXSCU_CFG_CPU2DIV_160MHZ (0) /*Same as SRIDIV */
1077 #endif /*#ifndef IFXSCU_CFG_CPU2DIV_160MHZ */
1078 
1079 #ifndef IFXSCU_CFG_CPU2DIV_200MHZ
1080 /** \brief Macro to configure CPU2DIV at 200MHz target frequency */
1081 #define IFXSCU_CFG_CPU2DIV_200MHZ (0) /*Same as SRIDIV */
1082 #endif /*#ifndef IFXSCU_CFG_CPU2DIV_200MHZ */
1083 
1084 #ifndef IFXSCU_CFG_CPU2DIV_240MHZ
1085 /** \brief Macro to configure CPU2DIV at 240MHz target frequency */
1086 #define IFXSCU_CFG_CPU2DIV_240MHZ (0) /*Same as SRIDIV */
1087 #endif /*#ifndef IFXSCU_CFG_CPU2DIV_240MHZ */
1088 
1089 #ifndef IFXSCU_CFG_CPU2DIV_300MHZ
1090 /** \brief Macro to configure CPU2DIV at 300MHz target frequency */
1091 #define IFXSCU_CFG_CPU2DIV_300MHZ (0) /*Same as SRIDIV */
1092 #endif /*#ifndef IFXSCU_CFG_CPU2DIV_300MHZ */
1093 
1094 
1095 
1096 /** \brief Macros to configure FLASH.FCON register for flash waitstate configuration.
1097  * \ref IfxScuCcu_InitialStepConfig
1098  */
1099 
1100 #ifndef IFXSCU_CFG_FLASH_FCON_WSPFLASH_80MHZ
1101 /** \brief Macro to configure FCON.WSPFLASH at 80MHz target frequency */
1102 #define IFXSCU_CFG_FLASH_FCON_WSPFLASH_80MHZ (3-1)
1103 #endif /*#ifndef IFXSCU_CFG_FLASH_FCON_WSPFLASH_80MHZ */
1104 
1105 #ifndef IFXSCU_CFG_FLASH_FCON_WSPFLASH_133MHZ
1106 /** \brief Macro to configure FCON.WSPFLASH at 133MHz target frequency */
1107 #define IFXSCU_CFG_FLASH_FCON_WSPFLASH_133MHZ (4-1)
1108 #endif /*#ifndef IFXSCU_CFG_FLASH_FCON_WSPFLASH_133MHZ */
1109 
1110 #ifndef IFXSCU_CFG_FLASH_FCON_WSPFLASH_160MHZ
1111 /** \brief Macro to configure FCON.WSPFLASH at 160MHz target frequency */
1112 #define IFXSCU_CFG_FLASH_FCON_WSPFLASH_160MHZ (5-1)
1113 #endif /*#ifndef IFXSCU_CFG_FLASH_FCON_WSPFLASH_160MHZ */
1114 
1115 #ifndef IFXSCU_CFG_FLASH_FCON_WSPFLASH_200MHZ
1116 /** \brief Macro to configure FCON.WSPFLASH at 200MHz target frequency */
1117 #define IFXSCU_CFG_FLASH_FCON_WSPFLASH_200MHZ (6-1)
1118 #endif /*#ifndef IFXSCU_CFG_FLASH_FCON_WSPFLASH_200MHZ */
1119 
1120 #ifndef IFXSCU_CFG_FLASH_FCON_WSPFLASH_240MHZ
1121 /** \brief Macro to configure FCON.WSPFLASH at 240MHz target frequency */
1122 #define IFXSCU_CFG_FLASH_FCON_WSPFLASH_240MHZ (8-1)
1123 #endif /*#ifndef IFXSCU_CFG_FLASH_FCON_WSPFLASH_240MHZ */
1124 
1125 #ifndef IFXSCU_CFG_FLASH_FCON_WSPFLASH_300MHZ
1126 /** \brief Macro to configure FCON.WSPFLASH at 300MHz target frequency */
1127 #define IFXSCU_CFG_FLASH_FCON_WSPFLASH_300MHZ (9-1)
1128 #endif /*#ifndef IFXSCU_CFG_FLASH_FCON_WSPFLASH_300MHZ */
1129 
1130 
1131 #ifndef IFXSCU_CFG_FLASH_FCON_WSECPF_80MHZ
1132 /** \brief Macro to configure FCON.WSECP_ at 80MHz target frequency */
1133 #define IFXSCU_CFG_FLASH_FCON_WSECPF_80MHZ (1-1)
1134 #endif /*#ifndef IFXSCU_CFG_FLASH_FCON_WSECPF_80MHZ */
1135 
1136 #ifndef IFXSCU_CFG_FLASH_FCON_WSECPF_133MHZ
1137 /** \brief Macro to configure FCON.WSECPF at 133MHz target frequency */
1138 #define IFXSCU_CFG_FLASH_FCON_WSECPF_133MHZ (2-1)
1139 #endif /*#ifndef IFXSCU_CFG_FLASH_FCON_WSECPF_133MHZ */
1140 
1141 #ifndef IFXSCU_CFG_FLASH_FCON_WSECPF_160MHZ
1142 /** \brief Macro to configure FCON.WSECPF at 160MHz target frequency */
1143 #define IFXSCU_CFG_FLASH_FCON_WSECPF_160MHZ (2-1)
1144 #endif /*#ifndef IFXSCU_CFG_FLASH_FCON_WSECPF_160MHZ */
1145 
1146 #ifndef IFXSCU_CFG_FLASH_FCON_WSECPF_200MHZ
1147 /** \brief Macro to configure FCON.WSECPF at 200MHz target frequency */
1148 #define IFXSCU_CFG_FLASH_FCON_WSECPF_200MHZ (2-1)
1149 #endif /*#ifndef IFXSCU_CFG_FLASH_FCON_WSECPF_200MHZ */
1150 
1151 #ifndef IFXSCU_CFG_FLASH_FCON_WSECPF_240MHZ
1152 /** \brief Macro to configure FCON.WSECPF_ at 240MHz target frequency */
1153 #define IFXSCU_CFG_FLASH_FCON_WSECPF_240MHZ (3-1)
1154 #endif /*#ifndef IFXSCU_CFG_FLASH_FCON_WSECPF_240MHZ */
1155 
1156 #ifndef IFXSCU_CFG_FLASH_FCON_WSECPF_300MHZ
1157 /** \brief Macro to configure FCON.WSECPF at 300MHz target frequency */
1158 #define IFXSCU_CFG_FLASH_FCON_WSECPF_300MHZ (3-1)
1159 #endif /*#ifndef IFXSCU_CFG_FLASH_FCON_WSECPF_300MHZ */
1160 
1161 
1162 #ifndef IFXSCU_CFG_FLASH_FCON_WSDFLASH_80MHZ
1163 /** \brief Macro to configure FCON.WSDFLASH at 80MHz target frequency */
1164 #define IFXSCU_CFG_FLASH_FCON_WSDFLASH_80MHZ (16-1)
1165 #endif /*#ifndef IFXSCU_CFG_FLASH_FCON_WSDFLASH_80MHZ */
1166 
1167 #ifndef IFXSCU_CFG_FLASH_FCON_WSDFLASH_133MHZ
1168 /** \brief Macro to configure FCON.WSDFLASH_ at 133MHz target frequency, where fSRI= 133/2= 66.5MHZ */
1169 #define IFXSCU_CFG_FLASH_FCON_WSDFLASH_133MHZ (14-1)
1170 #endif /*#ifndef IFXSCU_CFG_FLASH_FCON_WSDFLASH_133MHZ */
1171 
1172 #ifndef IFXSCU_CFG_FLASH_FCON_WSDFLASH_160MHZ
1173 /** \brief Macro to configure FCON.WSDFLASH at 160MHz target frequency, where fSRI= 160/2= 80MHZ */
1174 #define IFXSCU_CFG_FLASH_FCON_WSDFLASH_160MHZ (16-1)
1175 #endif /*#ifndef IFXSCU_CFG_FLASH_FCON_WSDFLASH_160MHZ */
1176 
1177 #ifndef IFXSCU_CFG_FLASH_FCON_WSDFLASH_200MHZ
1178 /** \brief Macro to configure FCON.WSDFLASH at 200MHz target frequency, where fSRI= 200/2= 100MHZ */
1179 #define IFXSCU_CFG_FLASH_FCON_WSDFLASH_200MHZ (20-1)
1180 #endif /*#ifndef IFXSCU_CFG_FLASH_FCON_WSDFLASH_200MHZ */
1181 
1182 #ifndef IFXSCU_CFG_FLASH_FCON_WSDFLASH_240MHZ
1183 /** \brief Macro to configure FCON.WSDFLASH at 240MHz target frequency, where fSRI= 240/3= 80MHZ */
1184 #define IFXSCU_CFG_FLASH_FCON_WSDFLASH_240MHZ (16-1)
1185 #endif /*#ifndef IFXSCU_CFG_FLASH_FCON_WSDFLASH_240MHZ */
1186 
1187 #ifndef IFXSCU_CFG_FLASH_FCON_WSDFLASH_300MHZ
1188 /** \brief Macro to configure FCON.WSDFLASH at 300MHz target frequency, where fSRI= 300/3= 100MHZ */
1189 #define IFXSCU_CFG_FLASH_FCON_WSDFLASH_300MHZ (20-1)
1190 #endif /*#ifndef IFXSCU_CFG_FLASH_FCON_WSDFLASH_300MHZ */
1191 
1192 
1193 #ifndef IFXSCU_CFG_FLASH_FCON_WSECDF_80MHZ
1194 /** \brief Macro to configure FCON.WSECDF at 80MHz target frequency */
1195 #define IFXSCU_CFG_FLASH_FCON_WSECDF_80MHZ (2-1)
1196 #endif /*#ifndef IFXSCU_CFG_FLASH_FCON_WSECDF_80MHZ */
1197 
1198 #ifndef IFXSCU_CFG_FLASH_FCON_WSECDF_133MHZ
1199 /** \brief Macro to configure FCON.WSECDF at 133MHz target frequency, where fSRI= 133/2= 66.5MHZ */
1200 #define IFXSCU_CFG_FLASH_FCON_WSECDF_133MHZ (2-1)
1201 #endif /*#ifndef IFXSCU_CFG_FLASH_FCON_WSECDF_133MHZ */
1202 
1203 #ifndef IFXSCU_CFG_FLASH_FCON_WSECDF_160MHZ
1204 /** \brief Macro to configure FCON.WSECDF at 160MHz target frequency, where fSRI= 160/2= 80MHZ */
1205 #define IFXSCU_CFG_FLASH_FCON_WSECDF_160MHZ (2-1)
1206 #endif /*#ifndef IFXSCU_CFG_FLASH_FCON_WSECDF_160MHZ */
1207 
1208 #ifndef IFXSCU_CFG_FLASH_FCON_WSECDF_200MHZ
1209 /** \brief Macro to configure FCON.WSECDF at 200MHz target frequency, where fSRI= 200/2= 100MHZ */
1210 #define IFXSCU_CFG_FLASH_FCON_WSECDF_200MHZ (2-1)
1211 #endif /*#ifndef IFXSCU_CFG_FLASH_FCON_WSECDF_200MHZ */
1212 
1213 #ifndef IFXSCU_CFG_FLASH_FCON_WSECDF_240MHZ
1214 /** \brief Macro to configure FCON.WSECDF at 240MHz target frequency, where fSRI= 240/3= 80MHZ */
1215 #define IFXSCU_CFG_FLASH_FCON_WSECDF_240MHZ (2-1)
1216 #endif /*#ifndef IFXSCU_CFG_FLASH_FCON_WSECDF_240MHZ */
1217 
1218 #ifndef IFXSCU_CFG_FLASH_FCON_WSECDF_300MHZ
1219 /** \brief Macro to configure FCON.WSECDF at 300MHz target frequency, where fSRI= 300/3= 100MHZ */
1220 #define IFXSCU_CFG_FLASH_FCON_WSECDF_300MHZ (2-1)
1221 #endif /*#ifndef IFXSCU_CFG_FLASH_FCON_WSECDF_300MHZ */
1222 
1223 /** \brief Macros to configure FLASH.FCON registers */
1224 #define IFXSCU_CFG_FLASH_WAITSTATE_MSK \
1225  ( \
1226  (IFX_FLASH_FCON_WSPFLASH_MSK << IFX_FLASH_FCON_WSPFLASH_OFF) | \
1227  (IFX_FLASH_FCON_WSECPF_MSK << IFX_FLASH_FCON_WSECPF_OFF) | \
1228  (IFX_FLASH_FCON_WSDFLASH_MSK << IFX_FLASH_FCON_WSDFLASH_OFF) | \
1229  (IFX_FLASH_FCON_WSECDF_MSK << IFX_FLASH_FCON_WSECDF_OFF))
1230 
1231 #define IFXSCU_CFG_FLASH_WAITSTATE_VAL_BASIC_(pllFreq) \
1232  ( \
1233  (IFXSCU_CFG_FLASH_FCON_WSPFLASH_##pllFreq << IFX_FLASH_FCON_WSPFLASH_OFF)| \
1234  (IFXSCU_CFG_FLASH_FCON_WSECPF_##pllFreq << IFX_FLASH_FCON_WSECPF_OFF) | \
1235  (IFXSCU_CFG_FLASH_FCON_WSDFLASH_##pllFreq << IFX_FLASH_FCON_WSDFLASH_OFF)| \
1236  (IFXSCU_CFG_FLASH_FCON_WSECDF_##pllFreq << IFX_FLASH_FCON_WSECDF_OFF))
1237 
1238 #define IFXSCU_CFG_FLASH_WAITSTATE_VAL_BASIC(pllFreq) IFXSCU_CFG_FLASH_WAITSTATE_VAL_BASIC_(pllFreq)
1239 
1240 #define IFXSCU_CFG_FLASH_WAITSTATE_VAL IFXSCU_CFG_FLASH_WAITSTATE_VAL_BASIC(IFXSCU_CFG_PLL_FREQ)
1241 
1242 
1243 /** \brief Macros to configure CCUCON0 Clock distribution */
1244 #define IFXSCU_CFG_CCUCON0_MASK \
1245  ( \
1246  (IFX_SCU_CCUCON0_BAUD1DIV_MSK << IFX_SCU_CCUCON0_BAUD1DIV_OFF) | \
1247  (IFX_SCU_CCUCON0_BAUD2DIV_MSK << IFX_SCU_CCUCON0_BAUD2DIV_OFF) | \
1248  (IFX_SCU_CCUCON0_SRIDIV_MSK << IFX_SCU_CCUCON0_SRIDIV_OFF) | \
1249  (IFX_SCU_CCUCON0_SPBDIV_MSK << IFX_SCU_CCUCON0_SPBDIV_OFF) | \
1250  (IFX_SCU_CCUCON0_FSI2DIV_MSK << IFX_SCU_CCUCON0_FSI2DIV_OFF) | \
1251  (IFX_SCU_CCUCON0_FSIDIV_MSK << IFX_SCU_CCUCON0_FSIDIV_OFF))
1252 
1253 #define IFXSCU_CFG_CCUCON0_BASIC_(pllFreq) \
1254  (uint32)( \
1255  (IFXSCU_CFG_BAUD1DIV_##pllFreq << IFX_SCU_CCUCON0_BAUD1DIV_OFF) | \
1256  (IFXSCU_CFG_BAUD2DIV_##pllFreq << IFX_SCU_CCUCON0_BAUD2DIV_OFF) | \
1257  (IFXSCU_CFG_SRIDIV_##pllFreq << IFX_SCU_CCUCON0_SRIDIV_OFF) | \
1258  (IFXSCU_CFG_SPBDIV_##pllFreq << IFX_SCU_CCUCON0_SPBDIV_OFF) | \
1259  (IFXSCU_CFG_FSI2DIV_##pllFreq << IFX_SCU_CCUCON0_FSI2DIV_OFF) | \
1260  (IFXSCU_CFG_FSIDIV_##pllFreq << IFX_SCU_CCUCON0_FSIDIV_OFF))
1261 
1262 #define IFXSCU_CFG_CCUCON0_BASIC(pllFreq) IFXSCU_CFG_CCUCON0_BASIC_(pllFreq)
1263 
1264 #define IFXSCU_CFG_CCUCON0 IFXSCU_CFG_CCUCON0_BASIC(IFXSCU_CFG_PLL_FREQ)
1265 
1266 /** \brief Macros to configure CCUCON1 Clock distribution */
1267 #define IFXSCU_CFG_CCUCON1_MASK \
1268  ( \
1269  (IFX_SCU_CCUCON1_CANDIV_MSK << IFX_SCU_CCUCON1_CANDIV_OFF) | \
1270  (IFX_SCU_CCUCON1_ERAYDIV_MSK << IFX_SCU_CCUCON1_ERAYDIV_OFF) | \
1271  (IFX_SCU_CCUCON1_STMDIV_MSK << IFX_SCU_CCUCON1_STMDIV_OFF) | \
1272  (IFX_SCU_CCUCON1_GTMDIV_MSK << IFX_SCU_CCUCON1_GTMDIV_OFF) | \
1273  (IFX_SCU_CCUCON1_ETHDIV_MSK << IFX_SCU_CCUCON1_ETHDIV_OFF) | \
1274  (IFX_SCU_CCUCON1_ASCLINFDIV_MSK << IFX_SCU_CCUCON1_ASCLINFDIV_OFF) | \
1275  (IFX_SCU_CCUCON1_ASCLINSDIV_MSK << IFX_SCU_CCUCON1_ASCLINSDIV_OFF))
1276 
1277 #define IFXSCU_CFG_CCUCON1_BASIC_(pllFreq) \
1278  (uint32)( \
1279  (IFXSCU_CFG_CANDIV_##pllFreq << IFX_SCU_CCUCON1_CANDIV_OFF) | \
1280  (IFXSCU_CFG_ERAYDIV_##pllFreq << IFX_SCU_CCUCON1_ERAYDIV_OFF) | \
1281  (IFXSCU_CFG_STMDIV_##pllFreq << IFX_SCU_CCUCON1_STMDIV_OFF) | \
1282  (IFXSCU_CFG_GTMDIV_##pllFreq << IFX_SCU_CCUCON1_GTMDIV_OFF) | \
1283  (IFXSCU_CFG_ETHDIV_##pllFreq << IFX_SCU_CCUCON1_ETHDIV_OFF) | \
1284  (IFXSCU_CFG_ASCLINFDIV_##pllFreq << IFX_SCU_CCUCON1_ASCLINFDIV_OFF) | \
1285  (IFXSCU_CFG_ASCLINSDIV_##pllFreq << IFX_SCU_CCUCON1_ASCLINSDIV_OFF))
1286 
1287 #define IFXSCU_CFG_CCUCON1_BASIC(pllFreq) IFXSCU_CFG_CCUCON1_BASIC_(pllFreq)
1288 
1289 #define IFXSCU_CFG_CCUCON1 IFXSCU_CFG_CCUCON1_BASIC(IFXSCU_CFG_PLL_FREQ)
1290 
1291 /** \brief Macros to configure CCUCON2 Clock distribution */
1292 #define IFXSCU_CFG_CCUCON2_MASK \
1293  ( \
1294  (IFX_SCU_CCUCON2_BBBDIV_MSK << IFX_SCU_CCUCON2_BBBDIV_OFF))
1295 
1296 #define IFXSCU_CFG_CCUCON2_BASIC_(pllFreq) \
1297  (uint32)( \
1298  (IFXSCU_CFG_BBBDIV_##pllFreq << IFX_SCU_CCUCON2_BBBDIV_OFF))
1299 
1300 #define IFXSCU_CFG_CCUCON2_BASIC(pllFreq) IFXSCU_CFG_CCUCON2_BASIC_(pllFreq)
1301 
1302 #define IFXSCU_CFG_CCUCON2 IFXSCU_CFG_CCUCON2_BASIC(IFXSCU_CFG_PLL_FREQ)
1303 
1304 /** \brief Macros to configure CCUCON5 Clock distribution */
1305 #define IFXSCU_CFG_CCUCON5_MASK \
1306  ( \
1307  (IFX_SCU_CCUCON5_MAXDIV_MSK << IFX_SCU_CCUCON5_MAXDIV_OFF))
1308 
1309 #define IFXSCU_CFG_CCUCON5_BASIC_(pllFreq) \
1310  (uint32)( \
1311  (IFXSCU_CFG_MAXDIV_##pllFreq << IFX_SCU_CCUCON5_MAXDIV_OFF))
1312 
1313 #define IFXSCU_CFG_CCUCON5_BASIC(pllFreq) IFXSCU_CFG_CCUCON5_BASIC_(pllFreq)
1314 
1315 #define IFXSCU_CFG_CCUCON5 IFXSCU_CFG_CCUCON5_BASIC(IFXSCU_CFG_PLL_FREQ)
1316 
1317 /** \brief Macros to configure CCUCON6 Clock distribution */
1318 #define IFXSCU_CFG_CCUCON6_MASK \
1319  ( \
1320  (IFX_SCU_CCUCON6_CPU0DIV_MSK << IFX_SCU_CCUCON6_CPU0DIV_OFF))
1321 
1322 #define IFXSCU_CFG_CCUCON6_BASIC_(pllFreq) \
1323  (uint32)( \
1324  (IFXSCU_CFG_CPU0DIV_##pllFreq << IFX_SCU_CCUCON6_CPU0DIV_OFF))
1325 
1326 #define IFXSCU_CFG_CCUCON6_BASIC(pllFreq) IFXSCU_CFG_CCUCON6_BASIC_(pllFreq)
1327 
1328 #define IFXSCU_CFG_CCUCON6 IFXSCU_CFG_CCUCON6_BASIC(IFXSCU_CFG_PLL_FREQ)
1329 
1330 /** \brief Macros to configure CCUCON7 Clock distribution */
1331 #define IFXSCU_CFG_CCUCON7_MASK \
1332  ( \
1333  (IFX_SCU_CCUCON7_CPU1DIV_MSK << IFX_SCU_CCUCON7_CPU1DIV_OFF))
1334 
1335 #define IFXSCU_CFG_CCUCON7_BASIC_(pllFreq) \
1336  (uint32)( \
1337  (IFXSCU_CFG_CPU1DIV_##pllFreq << IFX_SCU_CCUCON7_CPU1DIV_OFF))
1338 
1339 #define IFXSCU_CFG_CCUCON7_BASIC(pllFreq) IFXSCU_CFG_CCUCON7_BASIC_(pllFreq)
1340 
1341 #define IFXSCU_CFG_CCUCON7 IFXSCU_CFG_CCUCON7_BASIC(IFXSCU_CFG_PLL_FREQ)
1342 
1343 /** \brief Macros to configure CCUCON8 Clock distribution */
1344 #define IFXSCU_CFG_CCUCON8_MASK \
1345  ( \
1346  (IFX_SCU_CCUCON8_CPU2DIV_MSK << IFX_SCU_CCUCON8_CPU2DIV_OFF))
1347 
1348 #define IFXSCU_CFG_CCUCON8_BASIC_(pllFreq) \
1349  (uint32)( \
1350  (IFXSCU_CFG_CPU2DIV_##pllFreq << IFX_SCU_CCUCON8_CPU2DIV_OFF))
1351 
1352 #define IFXSCU_CFG_CCUCON8_BASIC(pllFreq) IFXSCU_CFG_CCUCON8_BASIC_(pllFreq)
1353 
1354 #define IFXSCU_CFG_CCUCON8 IFXSCU_CFG_CCUCON8_BASIC(IFXSCU_CFG_PLL_FREQ)
1355 
1356 #define IFXSCU_CFG_CLK_DISTRIBUTION \
1357  { \
1358 /* { uint32 value, uint32 mask }*/ \
1359  {IFXSCU_CFG_CCUCON0, IFXSCU_CFG_CCUCON0_MASK}, /*IfxScuCcu_CcuconRegConfig ccucon0;*/ \
1360  {IFXSCU_CFG_CCUCON1, IFXSCU_CFG_CCUCON1_MASK}, /*IfxScuCcu_CcuconRegConfig ccucon1;*/ \
1361  {IFXSCU_CFG_CCUCON2, IFXSCU_CFG_CCUCON2_MASK}, /*IfxScuCcu_CcuconRegConfig ccucon2;*/ \
1362  {IFXSCU_CFG_CCUCON5, IFXSCU_CFG_CCUCON5_MASK}, /*IfxScuCcu_CcuconRegConfig ccucon5;*/ \
1363  {IFXSCU_CFG_CCUCON6, IFXSCU_CFG_CCUCON6_MASK}, /*IfxScuCcu_CcuconRegConfig ccucon6;*/ \
1364  {IFXSCU_CFG_CCUCON7, IFXSCU_CFG_CCUCON7_MASK}, /*IfxScuCcu_CcuconRegConfig ccucon7;*/ \
1365  {IFXSCU_CFG_CCUCON8, IFXSCU_CFG_CCUCON8_MASK} /*IfxScuCcu_CcuconRegConfig ccucon8;*/ \
1366  }
1367 
1368 /*Utility macros for the configuration structure */
1369 /*macro for pll steps configuration */
1370 #define IFXSCU_CFG_PLL_STEPS_BASIC_(xtalFreq, pllFreq) IFXSCU_CFG_PLL_STEPS_##xtalFreq##_##pllFreq
1371 #define IFXSCU_CFG_PLL_STEPS_BASIC(xtalFreq, pllFreq) IFXSCU_CFG_PLL_STEPS_BASIC_(xtalFreq, pllFreq)
1372 #define IFXSCU_CFG_PLL_STEPS IFXSCU_CFG_PLL_STEPS_BASIC(IFXSCU_CFG_XTAL_FREQ, IFXSCU_CFG_PLL_FREQ)
1373 
1374 /*macro for pll initial step configuration */
1375 #define IFXSCU_CFG_PLL_INITIAL_STEP_BASIC_(xtalFreq, pllFreq) IFXSCU_CFG_PLL_INITIAL_STEP_##xtalFreq##_##pllFreq
1376 #define IFXSCU_CFG_PLL_INITIAL_STEP_BASIC(xtalFreq, pllFreq) IFXSCU_CFG_PLL_INITIAL_STEP_BASIC_(xtalFreq, pllFreq)
1377 #define IFXSCU_CFG_PLL_INITIAL_STEP IFXSCU_CFG_PLL_INITIAL_STEP_BASIC(IFXSCU_CFG_XTAL_FREQ, IFXSCU_CFG_PLL_FREQ)
1378 
1379 #define IFXSCU_CFG_FLASH_WAITSTATE \
1380 /* { uint32 value, uint32 mask }*/ \
1381  {IFXSCU_CFG_FLASH_WAITSTATE_VAL, IFXSCU_CFG_FLASH_WAITSTATE_MSK}
1382 
1383 
1384 #if (IFX_CFG_SCU_XTAL_FREQUENCY == (20000000))
1385 #define IFXSCU_CFG_XTAL_FREQ 20MHZ
1386 #elif (IFX_CFG_SCU_XTAL_FREQUENCY == (40000000))
1387 #define IFXSCU_CFG_XTAL_FREQ 40MHZ
1388 #elif (IFX_CFG_SCU_XTAL_FREQUENCY == (16000000))
1389 #define IFXSCU_CFG_XTAL_FREQ 16MHZ
1390 #elif (IFX_CFG_SCU_XTAL_FREQUENCY == (8000000))
1391 #define IFXSCU_CFG_XTAL_FREQ 8MHZ
1392 #else
1393 #error "Wrong XTAL frequency configuration! check IFX_CFG_SCU_XTAL_FREQUENCY configuration in Ifx_Cfg.h."
1394 #error "Aurix Triboard supported crystal frequencies are 8MHz, 16MHz, 20MHz and 40MHz"
1395 #endif
1396 
1397 #if (IFX_CFG_SCU_PLL_FREQUENCY == (80000000))
1398 #define IFXSCU_CFG_PLL_FREQ 80MHZ
1399 #elif (IFX_CFG_SCU_PLL_FREQUENCY == (133000000)) && (IFX_CFG_SCU_XTAL_FREQUENCY != (8000000))
1400 #define IFXSCU_CFG_PLL_FREQ 133MHZ
1401 #elif (IFX_CFG_SCU_PLL_FREQUENCY == (160000000))
1402 #define IFXSCU_CFG_PLL_FREQ 160MHZ
1403 #elif (IFX_CFG_SCU_PLL_FREQUENCY == (200000000))
1404 #define IFXSCU_CFG_PLL_FREQ 200MHZ
1405 #else
1406 #error "Wrong PLL frequency configuration!, check IFX_CFG_SCU_PLL_FREQUENCY configuration in Ifx_Cfg.h."
1407 #error "Supported PLL frequencies are 80MHz, 133MHz (8MHz XTAL doesn't support), 160Mhz, and 200MHz."
1408 #endif
1409 
1410 /******************************************************************************/
1411 /* Enum */
1412 /******************************************************************************/
1413 /** Clock selection */
1414 typedef enum
1415 {
1419 
1420 /** Input selection for PLL and PLL ERAY */
1421 typedef enum
1422 {
1426 
1427 /** Input frequency request control */
1428 typedef enum
1429 {
1434 
1435 typedef enum
1436 {
1437  IfxScu_PMCSR_REQSLP_Run = 0U, /* 00 Request CPU Run Mode */
1438  IfxScu_PMCSR_REQSLP_Idle = 1U, /* 01 Request CPU Idle Mode */
1439  IfxScu_PMCSR_REQSLP_Sleep = 2U, /* 10 Request CPU System Sleep Mode */
1440  IfxScu_PMCSR_REQSLP_Stby = 3U /* 11 Request System Standby Mode */
1442 
1443 /******************************************************************************/
1444 
1445 #endif /* IFXSCU_CFG_H */