iLLD_TC27xC  1.0
IfxGtm_cfg.h
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1 /**
2  * \file IfxGtm_cfg.h
3  * \brief Gtm on-chip implementation data
4  * \ingroup IfxLld_Gtm
5  *
6  * \version iLLD_0_1_0_10
7  * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
8  *
9  *
10  * IMPORTANT NOTICE
11  *
12  *
13  * Infineon Technologies AG (Infineon) is supplying this file for use
14  * exclusively with Infineon's microcontroller products. This file can be freely
15  * distributed within development tools that are supporting such microcontroller
16  * products.
17  *
18  * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
19  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
20  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
21  * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
22  * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
23  *
24  * \defgroup IfxLld_Gtm_Impl Implementation
25  * \ingroup IfxLld_Gtm
26  * \defgroup IfxLld_Gtm_Impl_Enumerations Enumerations
27  * \ingroup IfxLld_Gtm_Impl
28  * \defgroup IfxLld_Gtm_Impl_Data_Structures Data Structures
29  * \ingroup IfxLld_Gtm_Impl
30  */
31 
32 #ifndef IFXGTM_CFG_H
33 #define IFXGTM_CFG_H 1
34 
35 /******************************************************************************/
36 /*----------------------------------Includes----------------------------------*/
37 /******************************************************************************/
38 
40 #include "Ifx_Cfg.h"
41 #include "IfxGtm_reg.h"
42 #include "Port/Std/IfxPort.h"
43 
44 /******************************************************************************/
45 /*-----------------------------------Macros-----------------------------------*/
46 /******************************************************************************/
47 
48 /** \brief Mask for CMU_CLK_EN register (Enable): CLK0
49  */
50 #define IFXGTM_CMU_CLKEN_CLK0 (0x00000002)
51 
52 /** \brief Mask for CMU_CLK_EN register (Enable): CLK1
53  */
54 #define IFXGTM_CMU_CLKEN_CLK1 (0x00000008)
55 
56 /** \brief Mask for CMU_CLK_EN register (Enable): CLK2
57  */
58 #define IFXGTM_CMU_CLKEN_CLK2 (0x00000020)
59 
60 /** \brief Mask for CMU_CLK_EN register (Enable): CLK3
61  */
62 #define IFXGTM_CMU_CLKEN_CLK3 (0x00000080)
63 
64 /** \brief Mask for CMU_CLK_EN register (Enable): CLK4
65  */
66 #define IFXGTM_CMU_CLKEN_CLK4 (0x00000200)
67 
68 /** \brief Mask for CMU_CLK_EN register (Enable): CLK5
69  */
70 #define IFXGTM_CMU_CLKEN_CLK5 (0x00000800)
71 
72 /** \brief Mask for CMU_CLK_EN register (Enable): CLK6
73  */
74 #define IFXGTM_CMU_CLKEN_CLK6 (0x00002000)
75 
76 /** \brief Mask for CMU_CLK_EN register (Enable): CLK7
77  */
78 #define IFXGTM_CMU_CLKEN_CLK7 (0x00008000)
79 
80 /** \brief Mask for CMU_CLK_EN register (Enable): ECLK0
81  */
82 #define IFXGTM_CMU_CLKEN_ECLK0 (0x00020000)
83 
84 /** \brief Mask for CMU_CLK_EN register (Enable): ECLK1
85  */
86 #define IFXGTM_CMU_CLKEN_ECLK1 (0x00080000)
87 
88 /** \brief Mask for CMU_CLK_EN register (Enable): ECLK2
89  */
90 #define IFXGTM_CMU_CLKEN_ECLK2 (0x00200000)
91 
92 /** \brief Mask for CMU_CLK_EN register (Enable): FXCLK
93  */
94 #define IFXGTM_CMU_CLKEN_FXCLK (0x00800000)
95 
96 /** \brief Mask for CMU_CLK_EN register (Enable): ALL clocks
97  */
98 #define IFXGTM_CMU_CLKEN_ALL (0x00AAAAAA)
99 
100 /** \brief Mask for CMU_CLK_EN register (Disable): CLK0
101  */
102 #define IFXGTM_CMU_CLKDIS_CLK0 (0x00000001)
103 
104 /** \brief Mask for CMU_CLK_EN register (Disable): CLK1
105  */
106 #define IFXGTM_CMU_CLKDIS_CLK1 (0x00000004)
107 
108 /** \brief Mask for CMU_CLK_EN register (Disable): CLK2
109  */
110 #define IFXGTM_CMU_CLKDIS_CLK2 (0x00000010)
111 
112 /** \brief Mask for CMU_CLK_EN register (Disable): CLK3
113  */
114 #define IFXGTM_CMU_CLKDIS_CLK3 (0x00000040)
115 
116 /** \brief Mask for CMU_CLK_EN register (Disable): CLK4
117  */
118 #define IFXGTM_CMU_CLKDIS_CLK4 (0x00000100)
119 
120 /** \brief Mask for CMU_CLK_EN register (Disable): CLK5
121  */
122 #define IFXGTM_CMU_CLKDIS_CLK5 (0x00000400)
123 
124 /** \brief Mask for CMU_CLK_EN register (Disable): CLK6
125  */
126 #define IFXGTM_CMU_CLKDIS_CLK6 (0x00001000)
127 
128 /** \brief Mask for CMU_CLK_EN register (Disable): CLK7
129  */
130 #define IFXGTM_CMU_CLKDIS_CLK7 (0x00004000)
131 
132 /** \brief Mask for CMU_CLK_EN register (Disable): ECLK0
133  */
134 #define IFXGTM_CMU_CLKDIS_ECLK0 (0x00010000)
135 
136 /** \brief Mask for CMU_CLK_EN register (Disable): ECLK1
137  */
138 #define IFXGTM_CMU_CLKDIS_ECLK1 (0x00040000)
139 
140 /** \brief Mask for CMU_CLK_EN register (Disable): ECLK2
141  */
142 #define IFXGTM_CMU_CLKDIS_ECLK2 (0x00100000)
143 
144 /** \brief Mask for CMU_CLK_EN register (Disable): FXCLK
145  */
146 #define IFXGTM_CMU_CLKDIS_FXCLK (0x00400000)
147 
148 /** \brief Mask for CMU_CLK_EN register (Disable): ALL clocks
149  */
150 #define IFXGTM_CMU_CLKDIS_ALL (0x00555555)
151 
152 
153 /******************************************************************************/
154 /*------------------------------Type Definitions------------------------------*/
155 /******************************************************************************/
156 
157 typedef volatile struct IfxGtm_Tom_TGC Ifx_GTM_TOM_TGC;
158 
159 
160 
161 
162 /******************************************************************************/
163 /*--------------------------------Enumerations--------------------------------*/
164 /******************************************************************************/
165 
166 /** \addtogroup IfxLld_Gtm_Impl_Enumerations
167  * \{ */
168 /** \brief Enum for ATOM objects
169  */
170 typedef enum
171 {
172  IfxGtm_Atom_0 = 0, /**< \brief ATOM object 0 */
173  IfxGtm_Atom_1, /**< \brief ATOM object 1 */
174  IfxGtm_Atom_2, /**< \brief ATOM object 2 */
175  IfxGtm_Atom_3, /**< \brief ATOM object 3 */
176  IfxGtm_Atom_4, /**< \brief ATOM object 4 */
177 } IfxGtm_Atom;
178 
179 /** \brief Enum for ATOM channels
180  */
181 typedef enum
182 {
183  IfxGtm_Atom_Ch_none = -1, /**< \brief Not Selected */
184  IfxGtm_Atom_Ch_0 = 0, /**< \brief ATOM channel 0 */
185  IfxGtm_Atom_Ch_1, /**< \brief ATOM channel 1 */
186  IfxGtm_Atom_Ch_2, /**< \brief ATOM channel 2 */
187  IfxGtm_Atom_Ch_3, /**< \brief ATOM channel 3 */
188  IfxGtm_Atom_Ch_4, /**< \brief ATOM channel 4 */
189  IfxGtm_Atom_Ch_5, /**< \brief ATOM channel 5 */
190  IfxGtm_Atom_Ch_6, /**< \brief ATOM channel 6 */
191  IfxGtm_Atom_Ch_7, /**< \brief ATOM channel 7 */
193 
194 /** \brief Enum for Dpll subincrements
195  */
196 typedef enum
197 {
198  IfxGtm_Dpll_SubInc_1 = 0, /**< \brief subincrement1 */
199  IfxGtm_Dpll_SubInc_2, /**< \brief subincrement2 */
201 
202 /** \brief Enum Enable disable feature control
203  */
204 typedef enum
205 {
206  IfxGtm_FeatureControl_disabled = 0, /**< \brief disabled */
207  IfxGtm_FeatureControl_disable = 1, /**< \brief disable */
208  IfxGtm_FeatureControl_enable = 2, /**< \brief enable */
209  IfxGtm_FeatureControl_enabled = 3 /**< \brief enabled */
211 
212 /** \brief Enum for TIM objects
213  */
214 typedef enum
215 {
216  IfxGtm_Tim_0 = 0, /**< \brief TIM object 0 */
217  IfxGtm_Tim_1, /**< \brief TIM object 1 */
218  IfxGtm_Tim_2, /**< \brief TIM object 2 */
219  IfxGtm_Tim_3, /**< \brief TIM object 3 */
220 } IfxGtm_Tim;
221 
222 /** \brief Enum for TIM channels
223  */
224 typedef enum
225 {
226  IfxGtm_Tim_Ch_0 = 0, /**< \brief TIM channel 0 */
227  IfxGtm_Tim_Ch_1, /**< \brief TIM channel 1 */
228  IfxGtm_Tim_Ch_2, /**< \brief TIM channel 2 */
229  IfxGtm_Tim_Ch_3, /**< \brief TIM channel 3 */
230  IfxGtm_Tim_Ch_4, /**< \brief TIM channel 4 */
231  IfxGtm_Tim_Ch_5, /**< \brief TIM channel 5 */
232  IfxGtm_Tim_Ch_6, /**< \brief TIM channel 6 */
233  IfxGtm_Tim_Ch_7, /**< \brief TIM channel 7 */
234 } IfxGtm_Tim_Ch;
235 
236 /** \brief Enum for TOM objects
237  */
238 typedef enum
239 {
240  IfxGtm_Tom_0 = 0, /**< \brief TOM object 0 */
241  IfxGtm_Tom_1, /**< \brief TOM object 1 */
242  IfxGtm_Tom_2, /**< \brief TOM object 2 */
243 } IfxGtm_Tom;
244 
245 /** \brief Enum for TOM channels
246  */
247 typedef enum
248 {
249  IfxGtm_Tom_Ch_none = -1, /**< \brief Not Selected */
250  IfxGtm_Tom_Ch_0 = 0, /**< \brief TOM channel 0 */
251  IfxGtm_Tom_Ch_1, /**< \brief TOM channel 1 */
252  IfxGtm_Tom_Ch_2, /**< \brief TOM channel 2 */
253  IfxGtm_Tom_Ch_3, /**< \brief TOM channel 3 */
254  IfxGtm_Tom_Ch_4, /**< \brief TOM channel 4 */
255  IfxGtm_Tom_Ch_5, /**< \brief TOM channel 5 */
256  IfxGtm_Tom_Ch_6, /**< \brief TOM channel 6 */
257  IfxGtm_Tom_Ch_7, /**< \brief TOM channel 7 */
258  IfxGtm_Tom_Ch_8, /**< \brief TOM channel 8 */
259  IfxGtm_Tom_Ch_9, /**< \brief TOM channel 9 */
260  IfxGtm_Tom_Ch_10, /**< \brief TOM channel 10 */
261  IfxGtm_Tom_Ch_11, /**< \brief TOM channel 11 */
262  IfxGtm_Tom_Ch_12, /**< \brief TOM channel 12 */
263  IfxGtm_Tom_Ch_13, /**< \brief TOM channel 13 */
264  IfxGtm_Tom_Ch_14, /**< \brief TOM channel 14 */
265  IfxGtm_Tom_Ch_15, /**< \brief TOM channel 15 */
266 } IfxGtm_Tom_Ch;
267 
268 /** \brief Enum for TOM global channel control units
269  */
270 typedef enum
271 {
272  IfxGtm_Tom_Tgc_0 = 0, /**< \brief TOM global channel control unit0 */
273  IfxGtm_Tom_Tgc_1, /**< \brief TOM global channel control unit1 */
275 
276 /** \} */
277 
278 
279 /******************************************************************************/
280 /*-----------------------------Data Structures--------------------------------*/
281 /******************************************************************************/
282 
283 /** \addtogroup IfxLld_Gtm_Impl_Data_Structures
284  * \{ */
285 /** \brief TOM TGC objects
286  */
288 {
289  Ifx_GTM_TOM_TGC0_GLB_CTRL GLB_CTRL; /**< \brief 30, TOM TGC0 Global Control Register */
290  Ifx_GTM_TOM_TGC0_ACT_TB ACT_TB; /**< \brief 34, TOM TGC0 Action Time Base Register */
291  Ifx_GTM_TOM_TGC0_FUPD_CTRL FUPD_CTRL; /**< \brief 38, TOM TGC0 Force Update Control Register */
292  Ifx_GTM_TOM_TGC0_INT_TRIG INT_TRIG; /**< \brief 3C, TOM TGC0 Internal Trigger Control Register */
293  Ifx_GTM_TOM_CH xxxCH1; /**< \brief 40, TOM channel objects */
294  Ifx_GTM_TOM_TGC0_ENDIS_CTRL ENDIS_CTRL; /**< \brief 70, TOM TGC0 Enable/Disable Control Register */
295  Ifx_GTM_TOM_TGC0_ENDIS_STAT ENDIS_STAT; /**< \brief 74, TOM TGC0 Enable/Disable Status Register */
296  Ifx_GTM_TOM_TGC0_OUTEN_CTRL OUTEN_CTRL; /**< \brief 78, TOM TGC0 Output Enable Control Register */
297  Ifx_GTM_TOM_TGC0_OUTEN_STAT OUTEN_STAT; /**< \brief 7C, TOM TGC0 Output Enable Status Register */
298 };
299 
300 /** \} */
301 
302 
303 #endif /* IFXGTM_CFG_H */