35 #define IFXETH_PHY_PEF7071_MDIO_CTRL 0x00
37 #define IFXETH_PHY_PEF7071_MDIO_STAT 0x01
39 #define IFXETH_PHY_PEF7071_MDIO_PHYID1 0x02
41 #define IFXETH_PHY_PEF7071_MDIO_PHYID2 0x03
43 #define IFXETH_PHY_PEF7071_MDIO_AN_ADV 0x04
45 #define IFXETH_PHY_PEF7071_MDIO_AN_LPA 0x05
47 #define IFXETH_PHY_PEF7071_MDIO_AN_EXP 0x06
49 #define IFXETH_PHY_PEF7071_MDIO_AN_NPTX 0x07
51 #define IFXETH_PHY_PEF7071_MDIO_AN_NPRX 0x08
53 #define IFXETH_PHY_PEF7071_MDIO_GCTRL 0x09
55 #define IFXETH_PHY_PEF7071_MDIO_GSTAT 0x0A
57 #define IFXETH_PHY_PEF7071_MDIO_RES11 0x0B
59 #define IFXETH_PHY_PEF7071_MDIO_RES12 0x0C
61 #define IFXETH_PHY_PEF7071_MDIO_MMDCTRL 0x0D
63 #define IFXETH_PHY_PEF7071_MDIO_MMDDATA 0x0E
65 #define IFXETH_PHY_PEF7071_MDIO_XSTAT 0x0F
67 #define IFXETH_PHY_PEF7071_MDIO_PHYPERF 0x10
69 #define IFXETH_PHY_PEF7071_MDIO_PHYSTAT1 0x11
71 #define IFXETH_PHY_PEF7071_MDIO_PHYSTAT2 0x12
73 #define IFXETH_PHY_PEF7071_MDIO_PHYCTL1 0x13
75 #define IFXETH_PHY_PEF7071_MDIO_PHYCTL2 0x14
77 #define IFXETH_PHY_PEF7071_MDIO_ERRCNT 0x15
79 #define IFXETH_PHY_PEF7071_MDIO_EECTRL 0x16
81 #define IFXETH_PHY_PEF7071_MDIO_MIICTRL 0x17
83 #define IFXETH_PHY_PEF7071_MDIO_MIISTAT 0x18
85 #define IFXETH_PHY_PEF7071_MDIO_IMASK 0x19
87 #define IFXETH_PHY_PEF7071_MDIO_ISTAT 0x1A
89 #define IFXETH_PHY_PEF7071_MDIO_LED 0x1B
91 #define IFXETH_PHY_PEF7071_MDIO_TPGCTRL 0x1C
93 #define IFXETH_PHY_PEF7071_MDIO_TPGDATA 0x1D
95 #define IFXETH_PHY_PEF7071_MDIO_FWV 0x1E
97 #define IFXETH_PHY_PEF7071_MDIO_RES1F 0x1F
99 #define IFXETH_PHY_PEF7071_WAIT_GMII_READY() while (ETH_GMII_ADDRESS.B.GB) {}
111 static void IfxEth_Phy_Pef7071_read_mdio_reg(
uint32 layeraddr,
uint32 regaddr,
uint32 *pdata);
116 static void IfxEth_Phy_Pef7071_write_mdio_reg(
uint32 layeraddr,
uint32 regaddr,
uint32 data);
149 }
while (value & 0x8000);
170 boolean linkEstablished =
FALSE;
176 linkEstablished = ((value & (1 << 2)) != 0) ?
TRUE :
FALSE;
179 return linkEstablished;
183 static void IfxEth_Phy_Pef7071_read_mdio_reg(
uint32 layeraddr,
uint32 regaddr,
uint32 *pdata)
186 ETH_GMII_ADDRESS.U = (layeraddr << 11) | (regaddr << 6) | (0 << 2) | (0 << 1) | (1 << 0);
191 *pdata = ETH_GMII_DATA.U;
195 static void IfxEth_Phy_Pef7071_write_mdio_reg(
uint32 layeraddr,
uint32 regaddr,
uint32 data)
198 ETH_GMII_DATA.U = data;
201 ETH_GMII_ADDRESS.U = (layeraddr << 11) | (regaddr << 6) | (0 << 2) | (1 << 1) | (1 << 0);