iLLD_TC27xC
1.0
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In Tricore Cpu the cache enable/ disable are handled by the feature called cache bypass. Cache is enabled if the Bypass is disabled.
Startup sequence of each CPU execute the function to do the cache settings. Ifx_Cpu_StartupSequence The configuration parameters IFX_CFG_CPU_CSTART_ENABLE_TRICOREx_PCACHE and IFX_CFG_CPU_CSTART_ENABLE_TRICOREx_DCACHE control this function.
To modify the default configuration, these macros are to be defined in Ifx_Cfg.h (usually located under ../0_Src/0_AppSw/Config/Common/Ifx_Cfg.h)
Details of configuration parameters:
Enable/Disable program cache of Tricore CPU0 with parameter:
IFX_CFG_CPU_CSTART_ENABLE_TRICORE0_PCACHE
Enable/Disable program cache of Tricore CPU1 with parameter:
IFX_CFG_CPU_CSTART_ENABLE_TRICORE1_PCACHE
Enable/Disable program cache of Tricore CPU2 with parameter:
IFX_CFG_CPU_CSTART_ENABLE_TRICORE2_PCACHE
Enable/Disable data cache of Tricore CPU0 with parameter:
IFX_CFG_CPU_CSTART_ENABLE_TRICORE0_DCACHE
Enable/Disable data cache of Tricore CPU1 with parameter:
IFX_CFG_CPU_CSTART_ENABLE_TRICORE1_DCACHE
Enable/Disable data cache of Tricore CPU2 with parameter:
IFX_CFG_CPU_CSTART_ENABLE_TRICORE2_DCACHE
Following example shows, how to enable program cache of all available cores and disable data cache of all the available cores.
To control the the caches during runtime, refer for the details of APIs: Ifx_Cpu_Cache