30 #include "_Reg/IfxGtm_bf.h"
38 #define IFXGTM_ATOM_AGC_CHANNEL_COUNT (8)
65 uint32 mask = enableMask | (disableMask << 16);
70 uint8 shift = (i * 2) + bitfieldOffset;
95 value = IfxGtm_Atom_Agc_buildFeature(enableMask, disableMask, IFX_GTM_ATOM_AGC_ENDIS_CTRL_ENDIS_CTRL0_OFF);
99 agc->ENDIS_CTRL.U = value;
100 agc->ENDIS_STAT.U = value;
104 agc->ENDIS_CTRL.U = value;
113 value = IfxGtm_Atom_Agc_buildFeature(enableMask, disableMask, IFX_GTM_ATOM_AGC_OUTEN_CTRL_OUTEN_CTRL0_OFF);
117 agc->OUTEN_CTRL.U = value;
118 agc->OUTEN_STAT.U = value;
122 agc->OUTEN_CTRL.U = value;
129 agc->INT_TRIG.U = IfxGtm_Atom_Agc_buildFeature(enableMask, disableMask, IFX_GTM_ATOM_AGC_INT_TRIG_INT_TRIG0_OFF);
135 agc->GLB_CTRL.U = IfxGtm_Atom_Agc_buildFeature(enableMask, disableMask, IFX_GTM_ATOM_AGC_GLB_CTRL_UPEN_CTRL0_OFF);
141 agc->ACT_TB.B.TB_TRIG = enabled ? 1 : 0;
157 resetMask = resetMask >> 1;
160 agc->GLB_CTRL.U = reg << IFX_GTM_ATOM_AGC_GLB_CTRL_RST_CH0_OFF;
166 uint32 regEnable, regReset;
168 regEnable = IfxGtm_Atom_Agc_buildFeature(enableMask, disableMask, IFX_GTM_ATOM_AGC_FUPD_CTRL_FUPD_CTRL0_OFF);
170 IfxGtm_Atom_Agc_buildFeature(resetEnableMask, resetDisableMask, IFX_GTM_ATOM_AGC_FUPD_CTRL_RSTCN0_CH0_OFF);
171 agc->FUPD_CTRL.U = regEnable | regReset;
177 Ifx_GTM_ATOM_AGC_ACT_TB act_tb;
179 act_tb.U = agc->ACT_TB.U;
180 act_tb.B.TBU_SEL = base;
181 act_tb.B.ACT_TB = value;
182 agc->ACT_TB.U = act_tb.U;
188 agc->GLB_CTRL.U = 1 << IFX_GTM_ATOM_AGC_GLB_CTRL_HOST_TRIG_OFF;
194 Ifx_GTM_ATOM_CH *atomCh = (Ifx_GTM_ATOM_CH *)((
uint32)&atom->CH0.RDADDR.U + 0x80 * channel);
196 atomCh->IRQ_NOTIFY.B.CCU1TC = 1;
202 Ifx_GTM_ATOM_CH *atomCh = (Ifx_GTM_ATOM_CH *)((
uint32)&atom->CH0.RDADDR.U + 0x80 * channel);
203 atomCh->IRQ_NOTIFY.B.CCU0TC = 1;
209 Ifx_GTM_ATOM_CH_CTRL_Bits ctrl = {
212 .RST_CCU0 = resetEvent,
216 Ifx_GTM_ATOM_CH *atomCh = (Ifx_GTM_ATOM_CH *)((
uint32)&atom->CH0.RDADDR.U + 0x80 * channel);
218 atomCh->CTRL.B = ctrl;
235 Ifx_GTM_ATOM_CH *atomCh = (Ifx_GTM_ATOM_CH *)((
uint32)&atom->CH0.RDADDR.U + 0x80 * channel);
237 clock = atomCh->CTRL.B.CLK_SRC;
246 Ifx_GTM_ATOM_CH *atomCh = (Ifx_GTM_ATOM_CH *)((
uint32)&atom->CH0.RDADDR.U + 0x80 * channel);
248 result = atomCh->STAT.B.OL == 1;
256 return &MODULE_SRC.GTM.GTM[0].ATOM[atom][channel / 2];
262 return (
volatile uint32 *)((
uint32)&(atom->CH0.CN0.U) + channel * (offsetof(Ifx_GTM_ATOM, CH1) - offsetof(Ifx_GTM_ATOM, CH0)));
269 Ifx_GTM_ATOM_CH *atomCh = (Ifx_GTM_ATOM_CH *)((
uint32)&atom->CH0.RDADDR.U + 0x80 * channel);
271 result = atomCh->IRQ_NOTIFY.B.CCU1TC != 0;
280 Ifx_GTM_ATOM_CH *atomCh = (Ifx_GTM_ATOM_CH *)((
uint32)&atom->CH0.RDADDR.U + 0x80 * channel);
282 result = atomCh->IRQ_NOTIFY.B.CCU0TC != 0;
290 Ifx_GTM_ATOM_CH *atomCh = (Ifx_GTM_ATOM_CH *)((
uint32)&atom->CH0.RDADDR.U + 0x80 * channel);
292 atomCh->IRQ_FORCINT.B.TRG_CCU1TC = 1;
298 Ifx_GTM_ATOM_CH *atomCh = (Ifx_GTM_ATOM_CH *)((
uint32)&atom->CH0.RDADDR.U + 0x80 * channel);
300 atomCh->IRQ_FORCINT.B.TRG_CCU0TC = 1;
306 Ifx_GTM_ATOM_CH *atomCh = (Ifx_GTM_ATOM_CH *)((
uint32)&atom->CH0.RDADDR.U + 0x80 * channel);
308 atomCh->CTRL.B.CLK_SRC = clock;
314 Ifx_GTM_ATOM_CH *atomCh = (Ifx_GTM_ATOM_CH *)((
uint32)&atom->CH0.RDADDR.U + 0x80 * channel);
316 atomCh->CM0.U = compareZero;
317 atomCh->CM1.U = compareOne;
323 Ifx_GTM_ATOM_CH *atomCh = (Ifx_GTM_ATOM_CH *)((
uint32)&atom->CH0.RDADDR.U + 0x80 * channel);
325 atomCh->CM1.U = compareOne;
331 Ifx_GTM_ATOM_CH *atomCh = (Ifx_GTM_ATOM_CH *)((
uint32)&atom->CH0.RDADDR.U + 0x80 * channel);
333 atomCh->SR1.U = shadowOne;
339 Ifx_GTM_ATOM_CH *atomCh = (Ifx_GTM_ATOM_CH *)((
uint32)&atom->CH0.RDADDR.U + 0x80 * channel);
341 atomCh->SR0.U = shadowZero;
342 atomCh->SR1.U = shadowOne;
348 Ifx_GTM_ATOM_CH *atomCh = (Ifx_GTM_ATOM_CH *)((
uint32)&atom->CH0.RDADDR.U + 0x80 * channel);
350 atomCh->CM0.U = compareZero;
356 Ifx_GTM_ATOM_CH *atomCh = (Ifx_GTM_ATOM_CH *)((
uint32)&atom->CH0.RDADDR.U + 0x80 * channel);
358 atomCh->SR0.U = shadowZero;
364 Ifx_GTM_ATOM_CH *atomCh = (Ifx_GTM_ATOM_CH *)((
uint32)&atom->CH0.RDADDR.U + 0x80 * channel);
366 atomCh->CN0.U = value;
372 Ifx_GTM_ATOM_CH *atomCh = (Ifx_GTM_ATOM_CH *)((
uint32)&atom->CH0.RDADDR.U + 0x80 * channel);
374 Ifx_GTM_ATOM_CH_IRQ_EN en;
376 en.U = atomCh->IRQ_EN.U;
379 atomCh->IRQ_EN.U =
ZEROS;
380 atomCh->IRQ_MODE.B.IRQ_MODE = mode;
381 atomCh->IRQ_EN.U = en.U;
383 en.B.CCU0TC_IRQ_EN = interruptOnCompareZero ? 1 : 0;
384 en.B.CCU1TC_IRQ_EN = interruptOnCompareOne ? 1 : 0;
385 atomCh->IRQ_EN.U = en.U;
391 Ifx_GTM_ATOM_CH *atomCh = (Ifx_GTM_ATOM_CH *)((
uint32)&atom->CH0.RDADDR.U + 0x80 * channel);
393 atomCh->CTRL.B.OSM = enabled ? 1 : 0;
399 Ifx_GTM_ATOM_CH *atomCh = (Ifx_GTM_ATOM_CH *)((
uint32)&atom->CH0.RDADDR.U + 0x80 * channel);
401 atomCh->CTRL.B.RST_CCU0 = event;
407 Ifx_GTM_ATOM_CH *atomCh = (Ifx_GTM_ATOM_CH *)((
uint32)&atom->CH0.RDADDR.U + 0x80 * channel);
415 Ifx_GTM_ATOM_CH *atomCh = (Ifx_GTM_ATOM_CH *)((
uint32)&atom->CH0.RDADDR.U + 0x80 * channel);
417 atomCh->CTRL.B.TRIGOUT = trigger;