54 #include "IfxDma_bf.h"
1204 return dma->TSR[channelId].B.RST != 0;
1210 dma->TSR[channelId].B.RST = 1;
1216 dma->TSR[channelId].B.CTL = 1;
1222 dma->TSR[channelId].B.DCH = 1;
1228 dma->CH[channelId].ADICR.B.ETRL = 0;
1234 dma->TSR[channelId].B.ECH = 1;
1240 dma->CH[channelId].ADICR.B.ETRL = 1;
1246 return dma->TSR[channelId].B.TRL != 0;
1252 return dma->TSR[channelId].B.HTRE != 0;
1258 return dma->TSR[channelId].B.CH != 0;
1264 dma->CH[channelId].CHCSR.B.SCH = 1;
1278 dma->BLK1.CLRE.U = mask;
1282 dma->BLK0.CLRE.U = mask;
1291 dma->BLK1.EER.B.EDER = 0;
1295 dma->BLK0.EER.B.EDER = 0;
1304 dma->BLK1.EER.B.ESER = 0;
1308 dma->BLK0.EER.B.ESER = 0;
1317 dma->BLK1.EER.B.EDER = 1;
1321 dma->BLK0.EER.B.EDER = 1;
1330 dma->BLK1.EER.B.ESER = 1;
1334 dma->BLK0.EER.B.ESER = 1;
1343 return dma->BLK1.ERRSR.U;
1347 return dma->BLK0.ERRSR.U;
1354 return dma->CH[channelId].DADR.U;
1360 return dma->CH[channelId].SADR.U;
1366 return dma->CH[channelId].CHCSR.B.TCOUNT;
1378 dma->CH[channelId].CHCFGR.B.BLKM = blockMode;
1384 dma->CH[channelId].CHCFGR.B.CHMODE = 1;
1390 dma->CH[channelId].DADR.U = (
uint32)address;
1396 Ifx_DMA_CH_ADICR adicr;
1397 adicr.U = dma->CH[channelId].ADICR.U;
1398 adicr.B.DMF = incStep;
1399 adicr.B.INCD = direction;
1400 adicr.B.CBLD = size;
1401 dma->CH[channelId].ADICR.U = adicr.U;
1407 dma->CH[channelId].CHCFGR.B.CHDW = moveSize;
1413 dma->CH[channelId].ADICR.B.SHCT = shadow;
1419 dma->CH[channelId].CHCFGR.B.CHMODE = 0;
1425 dma->CH[channelId].CHCFGR.B.RROAT = 1;
1431 dma->CH[channelId].CHCFGR.B.RROAT = 0;
1437 dma->CH[channelId].SADR.U = (
uint32)address;
1443 Ifx_DMA_CH_ADICR adicr;
1444 adicr.U = dma->CH[channelId].ADICR.U;
1445 adicr.B.SMF = incStep;
1446 adicr.B.INCS = direction;
1447 adicr.B.CBLS = size;
1448 dma->CH[channelId].ADICR.U = adicr.U;
1454 dma->CH[channelId].CHCFGR.B.TREL = transferCount;
1460 dma->CH[channelId].ADICR.B.SHCT &= ~(3 << 2);
1466 dma->CH[channelId].ADICR.B.SHCT |= (1 << 2);
1467 dma->CH[channelId].ADICR.B.SHCT &= ~(1 << 3);
1473 dma->TSR[channelId].B.HLTCLR = 1;
1479 return dma->TSR[channelId].B.HLTACK != 0;
1485 dma->TSR[channelId].B.HLTREQ = 1;
1493 result = dma->CH[channelId].CHCSR.B.FROZEN != 0;
1497 dma->CH[channelId].CHCSR.B.FROZEN =
FALSE;
1506 return dma->CH[channelId].CHCSR.B.BUFFER != 0;
1512 dma->CH[channelId].CHCSR.U = 0U << IFX_DMA_CH_CHCSR_FROZEN_OFF;
1518 dma->CH[channelId].CHCSR.B.SWB = 1;
1524 dma->CH[channelId].CHCSR.B.CICH = 1;
1530 dma->CH[channelId].ADICR.B.INTCT &= ~(1 << 0);
1536 dma->CH[channelId].ADICR.B.INTCT |= (1 << 0);
1544 result = dma->CH[channelId].CHCSR.B.ICH != 0;
1548 dma->CH[channelId].CHCSR.B.CICH =
TRUE;
1559 result = dma->CH[channelId].CHCSR.B.IPM != 0;
1563 dma->CH[channelId].CHCSR.B.CICH =
TRUE;
1574 result = dma->CH[channelId].CHCSR.B.WRPD != 0;
1578 dma->CH[channelId].CHCSR.B.CWRP =
TRUE;
1589 result = dma->CH[channelId].CHCSR.B.WRPS != 0;
1593 dma->CH[channelId].CHCSR.B.CWRP =
TRUE;
1604 result = dma->CH[channelId].CHCSR.B.ICH;
1612 return dma->CH[channelId].CHCSR.B.LXO != 0;
1619 return &MODULE_SRC.DMA.DMA[0].CH[channelId];
1625 dma->CH[channelId].CHCSR.B.SIT = 1;