iLLD_TC27xC  1.0
IfxVadc_PinMap.h
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1 /**
2  * \file IfxVadc_PinMap.h
3  * \brief VADC I/O map
4  * \ingroup IfxLld_Vadc
5  *
6  * \version iLLD_0_1_0_10
7  * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
8  *
9  *
10  * IMPORTANT NOTICE
11  *
12  *
13  * Infineon Technologies AG (Infineon) is supplying this file for use
14  * exclusively with Infineon's microcontroller products. This file can be freely
15  * distributed within development tools that are supporting such microcontroller
16  * products.
17  *
18  * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
19  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
20  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
21  * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
22  * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
23  *
24  * \defgroup IfxLld_Vadc_pinmap VADC Pin Mapping
25  * \ingroup IfxLld_Vadc
26  */
27 
28 #ifndef IFXVADC_PINMAP_H
29 #define IFXVADC_PINMAP_H
30 
31 #include <_Reg/IfxVadc_reg.h>
32 #include <_Impl/IfxVadc_cfg.h>
33 #include <Port/Std/IfxPort.h>
34 
35 /** \addtogroup IfxLld_Vadc_pinmap
36  * \{ */
37 
38 /** \brief VADC Boundary Flag pin mapping structure */
39 typedef const struct
40 {
41  Ifx_VADC* module; /**< \brief Base address */
42  IfxVadc_GroupId groupId; /**< \brief Group ID */
43  IfxPort_Pin pin; /**< \brief Port pin */
44  IfxPort_OutputIdx select; /**< \brief Port control code */
46 
47 /** \brief VADC External Mux pin mapping structure */
48 typedef const struct
49 {
50  Ifx_VADC* module; /**< \brief Base address */
51  IfxPort_Pin pin; /**< \brief Port pin */
52  IfxPort_OutputIdx select; /**< \brief Port control code */
54 
55 /** \brief VADC Analog Input */
56 typedef const struct
57 {
58  Ifx_VADC* module; /**< \brief Base address */
59  IfxVadc_GroupId groupId; /**< \brief Group ID */
60  IfxPort_Pin pin; /**< \brief Port pin */
61  uint8 channelId; /**< \brief Channel ID */
63 
64 IFX_EXTERN IfxVadc_Emux_Out IfxVadc_EMUX00_P02_6_OUT; /**< \brief VADC_EMUX00: VADC output */
65 IFX_EXTERN IfxVadc_Emux_Out IfxVadc_EMUX00_P33_3_OUT; /**< \brief VADC_EMUX00: VADC output */
66 IFX_EXTERN IfxVadc_Emux_Out IfxVadc_EMUX01_P02_7_OUT; /**< \brief VADC_EMUX01: VADC output */
67 IFX_EXTERN IfxVadc_Emux_Out IfxVadc_EMUX01_P33_2_OUT; /**< \brief VADC_EMUX01: VADC output */
68 IFX_EXTERN IfxVadc_Emux_Out IfxVadc_EMUX02_P02_8_OUT; /**< \brief VADC_EMUX02: VADC output */
69 IFX_EXTERN IfxVadc_Emux_Out IfxVadc_EMUX02_P33_1_OUT; /**< \brief VADC_EMUX02: VADC output */
70 IFX_EXTERN IfxVadc_Emux_Out IfxVadc_EMUX10_P00_6_OUT; /**< \brief VADC_EMUX10: VADC output */
71 IFX_EXTERN IfxVadc_Emux_Out IfxVadc_EMUX10_P33_6_OUT; /**< \brief VADC_EMUX10: VADC output */
72 IFX_EXTERN IfxVadc_Emux_Out IfxVadc_EMUX11_P00_7_OUT; /**< \brief VADC_EMUX11: VADC output */
73 IFX_EXTERN IfxVadc_Emux_Out IfxVadc_EMUX11_P33_5_OUT; /**< \brief VADC_EMUX11: VADC output */
74 IFX_EXTERN IfxVadc_Emux_Out IfxVadc_EMUX12_P00_8_OUT; /**< \brief VADC_EMUX12: VADC output */
75 IFX_EXTERN IfxVadc_Emux_Out IfxVadc_EMUX12_P33_4_OUT; /**< \brief VADC_EMUX12: VADC output */
76 IFX_EXTERN IfxVadc_GxBfl_Out IfxVadc_G0BFL0_P33_4_OUT; /**< \brief VADC_G0BFL0: VADC output */
77 IFX_EXTERN IfxVadc_GxBfl_Out IfxVadc_G0BFL1_P33_5_OUT; /**< \brief VADC_G0BFL1: VADC output */
78 IFX_EXTERN IfxVadc_GxBfl_Out IfxVadc_G1BFL0_P33_6_OUT; /**< \brief VADC_G1BFL0: VADC output */
79 IFX_EXTERN IfxVadc_GxBfl_Out IfxVadc_G1BFL1_P33_7_OUT; /**< \brief VADC_G1BFL1: VADC output */
80 IFX_EXTERN IfxVadc_GxBfl_Out IfxVadc_G2BFL0_P33_0_OUT; /**< \brief VADC_G2BFL0: VADC output */
81 IFX_EXTERN IfxVadc_GxBfl_Out IfxVadc_G2BFL1_P33_1_OUT; /**< \brief VADC_G2BFL1: VADC output */
82 IFX_EXTERN IfxVadc_GxBfl_Out IfxVadc_G2BFL2_P33_2_OUT; /**< \brief VADC_G2BFL2: VADC output */
83 IFX_EXTERN IfxVadc_GxBfl_Out IfxVadc_G2BFL3_P33_3_OUT; /**< \brief VADC_G2BFL3: VADC output */
84 IFX_EXTERN IfxVadc_GxBfl_Out IfxVadc_G4BFL0_P00_4_OUT; /**< \brief VADC_G4BFL0: VADC output */
85 IFX_EXTERN IfxVadc_GxBfl_Out IfxVadc_G4BFL1_P00_5_OUT; /**< \brief VADC_G4BFL1: VADC output */
86 IFX_EXTERN IfxVadc_GxBfl_Out IfxVadc_G4BFL2_P00_6_OUT; /**< \brief VADC_G4BFL2: VADC output */
87 IFX_EXTERN IfxVadc_GxBfl_Out IfxVadc_G4BFL3_P00_7_OUT; /**< \brief VADC_G4BFL3: VADC output */
88 IFX_EXTERN IfxVadc_GxBfl_Out IfxVadc_G6BFL0_P10_0_OUT; /**< \brief VADC_G6BFL0: VADC output */
89 IFX_EXTERN IfxVadc_GxBfl_Out IfxVadc_G6BFL1_P10_1_OUT; /**< \brief VADC_G6BFL1: VADC output */
90 IFX_EXTERN IfxVadc_GxBfl_Out IfxVadc_G6BFL2_P10_2_OUT; /**< \brief VADC_G6BFL2: VADC output */
91 IFX_EXTERN IfxVadc_GxBfl_Out IfxVadc_G6BFL3_P10_3_OUT; /**< \brief VADC_G6BFL3: VADC output */
92 IFX_EXTERN IfxVadc_GxBfl_Out IfxVadc_G7BFL0_P10_6_OUT; /**< \brief VADC_G7BFL0: VADC output */
93 IFX_EXTERN IfxVadc_GxBfl_Out IfxVadc_G7BFL1_P10_7_OUT; /**< \brief VADC_G7BFL1: VADC output */
94 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G0_0_AN0_IN; /**< \brief VADC_G0_0: VADC input channel 0 of group 0 */
95 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G0_1_AN1_IN; /**< \brief VADC_G0_1: VADC input channel 1 of group 0 */
96 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G0_2_AN2_IN; /**< \brief VADC_G0_2: VADC input channel 2 of group 0 */
97 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G0_3_AN3_IN; /**< \brief VADC_G0_3: VADC input channel 3 of group 0 */
98 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G0_4_AN4_IN; /**< \brief VADC_G0_4: VADC input channel 4 of group 0 */
99 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G0_5_AN5_IN; /**< \brief VADC_G0_5: VADC input channel 5 of group 0 */
100 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G0_6_AN6_IN; /**< \brief VADC_G0_6: VADC input channel 6 of group 0 */
101 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G0_7_AN7_IN; /**< \brief VADC_G0_7: VADC input channel 7 of group 0 */
102 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G1_0_AN8_IN; /**< \brief VADC_G1_0: VADC input channel 0 of group 1 */
103 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G1_1_AN9_IN; /**< \brief VADC_G1_1: VADC input channel 1 of group 1 */
104 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G1_2_AN10_IN; /**< \brief VADC_G1_2: VADC input channel 2 of group 1 */
105 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G1_3_AN11_IN; /**< \brief VADC_G1_3: VADC input channel 3 of group 1 */
106 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G1_4_AN12_IN; /**< \brief VADC_G1_4: VADC input channel 4 of group 1 */
107 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G1_5_AN13_IN; /**< \brief VADC_G1_5: VADC input channel 5 of group 1 */
108 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G1_6_AN14_IN; /**< \brief VADC_G1_6: VADC input channel 6 of group 1 */
109 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G1_7_AN15_IN; /**< \brief VADC_G1_7: VADC input channel 7 of group 1 */
110 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G2_0_AN16_IN; /**< \brief VADC_G2_0: VADC input channel 0 of group 2 */
111 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G2_1_AN17_IN; /**< \brief VADC_G2_1: VADC input channel 1 of group 2 */
112 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G2_2_AN18_IN; /**< \brief VADC_G2_2: VADC input channel 2 of group 2 */
113 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G2_3_AN19_IN; /**< \brief VADC_G2_3: VADC input channel 3 of group 2 */
114 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G2_4_AN20_IN; /**< \brief VADC_G2_4: VADC input channel 4 of group 2 */
115 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G2_5_AN21_IN; /**< \brief VADC_G2_5: VADC input channel 5 of group 2 */
116 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G2_6_AN22_IN; /**< \brief VADC_G2_6: VADC input channel 6 of group 2 */
117 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G2_7_AN23_IN; /**< \brief VADC_G2_7: VADC input channel 7 of group 2 */
118 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G3_0_AN24_IN; /**< \brief VADC_G3_0: VADC input channel 0 of group 3 */
119 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G3_0_P40_0_IN; /**< \brief VADC_G3_0: VADC input channel 0 of group 3 */
120 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G3_1_AN25_IN; /**< \brief VADC_G3_1: VADC input channel 1 of group 3 */
121 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G3_1_P40_1_IN; /**< \brief VADC_G3_1: VADC input channel 1 of group 3 */
122 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G3_2_AN26_IN; /**< \brief VADC_G3_2: VADC input channel 2 of group 3 */
123 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G3_2_P40_2_IN; /**< \brief VADC_G3_2: VADC input channel 2 of group 3 */
124 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G3_3_AN27_IN; /**< \brief VADC_G3_3: VADC input channel 3 of group 3 */
125 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G3_3_P40_3_IN; /**< \brief VADC_G3_3: VADC input channel 3 of group 3 */
126 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G3_4_AN28_IN; /**< \brief VADC_G3_4: VADC input channel 4 of group 3 */
127 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G3_5_AN29_IN; /**< \brief VADC_G3_5: VADC input channel 5 of group 3 */
128 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G3_6_AN30_IN; /**< \brief VADC_G3_6: VADC input channel 6 of group 3 */
129 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G3_7_AN31_IN; /**< \brief VADC_G3_7: VADC input channel 7 of group 3 */
130 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G4_0_AN32_IN; /**< \brief VADC_G4_0: VADC input channel 0 of group 4 */
131 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G4_0_P40_4_IN; /**< \brief VADC_G4_0: VADC input channel 0 of group 4 */
132 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G4_1_AN33_IN; /**< \brief VADC_G4_1: VADC input channel 1 of group 4 */
133 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G4_1_P40_5_IN; /**< \brief VADC_G4_1: VADC input channel 1 of group 4 */
134 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G4_2_AN34_IN; /**< \brief VADC_G4_2: VADC input channel 2 of group 4 */
135 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G4_3_AN35_IN; /**< \brief VADC_G4_3: VADC input channel 3 of group 4 */
136 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G4_4_AN36_IN; /**< \brief VADC_G4_4: VADC input channel 4 of group 4 */
137 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G4_4_P40_6_IN; /**< \brief VADC_G4_4: VADC input channel 4 of group 4 */
138 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G4_5_AN37_IN; /**< \brief VADC_G4_5: VADC input channel 5 of group 4 */
139 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G4_5_P40_7_IN; /**< \brief VADC_G4_5: VADC input channel 5 of group 4 */
140 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G4_6_AN38_IN; /**< \brief VADC_G4_6: VADC input channel 6 of group 4 */
141 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G4_6_P40_8_IN; /**< \brief VADC_G4_6: VADC input channel 6 of group 4 */
142 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G4_7_AN39_IN; /**< \brief VADC_G4_7: VADC input channel 7 of group 4 */
143 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G4_7_P40_9_IN; /**< \brief VADC_G4_7: VADC input channel 7 of group 4 */
144 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G5_0_AN40_IN; /**< \brief VADC_G5_0: VADC input channel 0 of group 5 */
145 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G5_1_AN41_IN; /**< \brief VADC_G5_1: VADC input channel 1 of group 5 */
146 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G5_2_AN42_IN; /**< \brief VADC_G5_2: VADC input channel 2 of group 5 */
147 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G5_3_AN43_IN; /**< \brief VADC_G5_3: VADC input channel 3 of group 5 */
148 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G5_4_AN44_IN; /**< \brief VADC_G5_4: VADC input channel 4 of group 5 */
149 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G5_5_AN45_IN; /**< \brief VADC_G5_5: VADC input channel 5 of group 5 */
150 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G5_6_AN46_IN; /**< \brief VADC_G5_6: VADC input channel 6 of group 5 */
151 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G5_7_AN47_IN; /**< \brief VADC_G5_7: VADC input channel 7 of group 5 */
152 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G6_0_P00_12_IN; /**< \brief VADC_G6_0: VADC input */
153 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G6_1_P00_11_IN; /**< \brief VADC_G6_1: VADC input */
154 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G6_2_P00_10_IN; /**< \brief VADC_G6_2: VADC input */
155 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G6_3_P00_9_IN; /**< \brief VADC_G6_3: VADC input */
156 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G6_4_P00_8_IN; /**< \brief VADC_G6_4: VADC input */
157 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G6_5_P00_7_IN; /**< \brief VADC_G6_5: VADC input */
158 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G7_0_P00_6_IN; /**< \brief VADC_G7_0: VADC input */
159 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G7_1_P00_5_IN; /**< \brief VADC_G7_1: VADC input */
160 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G7_2_P00_4_IN; /**< \brief VADC_G7_2: VADC input */
161 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G7_3_P00_3_IN; /**< \brief VADC_G7_3: VADC input */
162 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G7_4_P00_2_IN; /**< \brief VADC_G7_4: VADC input */
163 IFX_EXTERN IfxVadc_Vadcg_In IfxVadc_G7_5_P00_1_IN; /**< \brief VADC_G7_5: VADC input */
164 
165 /** \brief Table dimensions */
166 #define IFXVADC_PINMAP_NUM_MODULES 1
167 #define IFXVADC_PINMAP_NUM_GROUPS 8
168 #define IFXVADC_PINMAP_EMUX_OUT_NUM_ITEMS 12
169 #define IFXVADC_PINMAP_GXBFL_OUT_NUM_ITEMS 4
170 #define IFXVADC_PINMAP_VADCG_IN_NUM_ITEMS 8
171 
172 
173 /** \brief IfxVadc_Emux_Out table */
175 
176 /** \brief IfxVadc_GxBfl_Out table */
178 
179 /** \brief IfxVadc_Vadcg_In table */
181 
182 /** \} */
183 
184 #endif /* IFXVADC_PINMAP_H */