EDP Basic Concepts

The EDP Baseboard (or “motherboard”) consists of 4 ‘stations’ with the minimum configuration of the motherboard with a single plug-in processor module. All 4 stations are identical, and there are many permutations of CPU modules and Application modules possible. Even with just the minimum configuration of Motherboard and CPU module for example, you can easily run a web-server through the standard onboard Ethernet connection. There are various application modules; we have introduced an initial starter range consisting of basic digital and analogue I/O, a motor control module and a communications module. The more advanced user will discover that it is possible to run more than one processor module on the motherboard in a Master and Slave configuration.
The motherboard is an Extended Euro card size (220 x 100 mm) fitted with rubber feet to lay flat on the bench, but able to be used in a standard rack system. Add a 64-way DIN (RS 381-8696) connector and you can plug the EDP into a backplane. Connectors for four module stations are supplied, arranged to ensure correct module fitting. There are also fitted +3.3V and +5V voltage regulators, a back-up battery, an RJ45 Ethernet connector, a mini-USB connector, +12 volt power-supply jack, I/O breakout header and eight DIP switches ported onto the system I2C bus.
The DIP switches allow the user software running on a processor module to read a configuration setting, enabling I/O ports to be set up correctly, for example, or for CAN or TCP/IP addresses to be set. Depending on the capability of the particular processor module in use, up to three I2C buses and two CAN networks are available. Many of the application modules use an I2C bus for primary communication with the processor providing maximum flexibility. Some processor chips will require +5 volts, others +3.3 volts. A factory link on the module selects the correct supply from the connector. This supply is linked to a further connector pin on all the other module stations providing a correct voltage reference or bus pull-up for the application modules. There is also duplication of an analogue input unit, to give a very large number of inputs.
Reusable Components
The EDP baseboard is designed to be used and reused with new CPU and application modules being introduced on a regular basis. Its robust design has been rigorously tested, and every effort has been made at the design stage to protect the EDP from the most common human errors: the motherboard will have a significantly longer life than the average development board and is suitable for use in specialist one-off and low-volume products. Typical applications might be industrial controllers, scientific instrument controllers, datalogging and remote monitoring. For these reasons the EDP will prove attractive to all design engineers looking for a cost effective solution which allows them to significantly improve their development process and thus deliver products in reduced time. Design engineers, consultants, educators and trainers will quickly realise the benefits and recognise the potential of the development platform modules system as an effective solution.
Bread-Boarding Platform
With the difficulty in applying traditional “bread-boarding” techniques to today’s tiny SMT components, evaluating new active devices has become major problem. There is usually no alternative to creating a special “try-out” PCB using rapid PCB production houses just to get a new device up and running. The EDP has been designed to host such experimental and trial designs, providing “clean” 5 and 3V3 supplies and instant access to a range of standard microcontrollers and IO blocks and devices. The design information necessary to allow you to create your own module for experimenting with new devices is available free of charge but in many cases, RS will already have such a module available to save you the effort.
The EDP represents the start of a continuous launch process which will see the introduction of new processor and application modules on a monthly basis.
EDP Modules Available Now
Command Module: ST Microelectronics STR912
Command Module: Infineon XC167
Command Module: PIC PIM
Command Module: MBED
Application Module: Analogue Input
Application Module: Digital Input/Output
Application Module: Brushed DC Motor Control
Application Module: Basic Communications
Basic EDP Concepts
The EDP allows microcontrollers and IO devices to communicate through a standardised interface. To some extent this interface is analogous to PC104 or STE busses where a connector pinout is defined that allows the interconnection of address and data-bus connected devices. Such busses tend to include only power line, data and address busses plus control signals such as chipselects and interrupt request lines.
For microcontroller systems, such a collection of signals is of very limited use, especially for single-chip CPUs that use no external bus. It also takes no account of the specialist pin functions available on microcontrollers such as CAN, I2C, SPI, signal measurement and signal generation peripherals.

Standardised Signal Set for Embedded Microcontrollers
The EDPCON1 and 2 connectors thus defines a set of signals on a standardised format that are relevant to typical 8, 16 and 32-bit microcontrollers. In addition to address bus, data bus and chip select signals, they include 3 I2C channels, 2 CAN channels, groups of pins able to create interrupts in response to external events, groups of pins able to create pulsetrains, others dedicated to motor control, I2S, memory cards and many other common microcontroller IO types.
All of these signals are contained within two 0.8mm dual-row connectors of 140 and 100 pins each.

EDP Signal Names
The generic signals present on the connectors have names which indicate their primary and secondary functions.
EDPCON1 Signal Description
EDPCON1 Signal | Signal Description |
ANx | Analog signals |
VAGND | Analog ground, referenced to CPU and Analog application analog signal grounds |
GPIOx | Pins that can only be set to 1 or 0 by a CPU instruction. It has no special or alternate function. |
GPIOx_MCIxxx | Pins that have basic IO function like “GPIOx” but which also form an SM/MMC card interface |
GPIOx_I2S_XXX | Pins that have basic IO function like “GPIOx” but which also form an I2S interface. |
IRQx_GPIOx_X_I2C_INT | Pins that are used by the three I2C busses to request a CPU interrupt. Note IRQ_GPIO16_CNTRL_I2C_INT should always be reserved for use by the I2C CNTRL I2C bus. |
CPU_DACx_GPIOx | Pins where CPUs with true digital to analog converter outputs are always connected. Alternatively, PWM will be available if there is no DAC. |
EVMx_GPIOx | Pins which have basic IO function but which also can measure timed events, pulse times and durations e.g. CAPCOM input. |
GPIOx_ADx | Pins with basic IO function but which also can form a multiplexed address and data bus. |
EVGx_GPIOx | Pins which have basic IO function but which also can generate events like timed pulses and transitions e.g. CAPCOM output. |
EVM2_GPIO41_CAPADC | Pins which have basic IO function but which also can measure pulse times and durations e.g. CAPCOM input. If the CPU supports the triggering of ADC readings on an edge, the function will be on this pin. |
ASC0_RX_TTL | Logic level connection to CPU module’s serial port 0 receive pin. |
ASC0_TX_TTL | Logic level connection to CPU module’s serial port 0 transmit pin. |
ASC1_RX_TTL | Logic level connection to CPU module’s serial port 1 receive pin. |
ASC1_TX_TTL | Logic level connection to CPU module’s serial port 1 transmit pin. |
ETH_xxx | Pins connected to an Ethernet PHY on CPU module, where available. |
MOTOR_XXXX | Pins required for driving three-phase AC and DC brushless motors, including inputs for Hall sensors and tachometers or other speed-related signals. |
EMRG_TRP | Emergency stop/trip function for motor control. |
CAN1_RX/TX | Logic level connection to CPU module’s second CAN module (where fitted). |
VCC_CM | Peripheral operating voltage of CPU module currently fitted. |
+3V3 | +3V3 supply from baseboard voltage regulator |
+5V | +5V supply from baseboard voltage regulator |
+12V | Raw 12V from power input to baseboard |
12VGND | Ground connection to power supply. |
SGND | Digital logic ground (connects to 12VGND at star point in baseboard |
3V3 Vbatt | Permanent 3V3 supply from Lithium cell on baseboard (where fitted) |
EDPCON2 Signal Description
EDPCON2 Signal | Signal Description |
#RESIN | Reset input to CPU module |
#RESEOUT | Reset out signal from CPU module (where available) |
I2C_GEN0_SDA/SCL | Secondary I2C bus data and clock (where available) |
Axx_ADxx | 16 bit multiplexed address/data bus when enabled by jumpers on |
CPU module. | |
ALE | CPU module’s address latch enable signal |
#RD | CPU module’s READ signal |
#WR | CPU module’s WRITE (or WRITELOW) signal |
#WRH | CPU module’s WRITE (or WRITEHIGH) signal |
#PSEN_A16 | CPU module’s PSEN signal (8051) or A16, where available |
#CS0 | CPU module’s first chipselect signal |
#CS1 | CPU module’s second chipselect signal |
#CS2 | CPU module’s third chipselect signal |
CPU module’s fourth chipselect signal | |
CAN0_RX/TX | Logic level connection to CPU module’s first CAN module (where fitted). |
USB-DEBUG+/- | USB signals connected to FTDI USB-JTAG device on CPU module |
CNTRL_SPI_XX | Signals connected to CPU module’s first SPI peripheral |
CNTRL_I2C_SDA/SCL | Signals connected to CPU module’s first or primary I2C channel. (This is the I2C control backbone for the EDP baseboard). |
CANH0/CANL0 | CPU module’s first CAN module via physical layer drivers. |
VCC_CM | Peripheral operating voltage of CPU module currently fitted. |
+3V3 | +3V3 supply from baseboard voltage regulator |
+5V | +5V supply from baseboard voltage regulator |
SGND | Digital logic ground (connects to 12VGND at star point in baseboard |
The EDP Virtual CPU Concept
A microcontroller that has its IO pins mapped appropriately onto the EDPCON1 and EDPCON2 connectors appears to be a virtual CPU to other IO devices fitted on the bus. Thus for example, a 14-bit ADC device on the EDPCON baseboard will see a CPU module also on the bus, as a virtual CPU whose pinout is defined by the EDP bus. Currently two popular microcontrollers (Infineon XC167 and ST STR9) have had their IO pins mapped onto the EDPCON system. These two devices have some features in common -UARTs, capture and compare pins, ADC, CAN but the STR9 also has USB device. Thus the pin mapping to the EDPCON is not 100% in that on the XC167 version, the USB device pins are unused. Both devices have dedicated motor control peripherals which although they have different pin names, have virtually the same functionality. Hence for example, a brushless DC motor control module with half-bridges can be designed to interface to the motor control region of the EDPCON bus without any regard for the CPU type to be ultimately used. The net result is that subject some limitations, a range of modules bearing different CPUs can be freely connected to a range of IO modules.
The EDPCON has been designed to accommodate all the common peripherals found on current microcontrollers, including advanced interfaces like SD/MMC and I2S. Thus it is possible to map almost any microcontroller to this format.
Example Of Real CPU To EDPCON Mapping
This is the mapping developed for the Infineon XC167 and used on the RS-EDPCM-XC167 module.
Inter-Module Communication
With up to 4 modules on the EDPCON bus, some form of communication is required. With a limited number of CPU pins available, it is necessary to use a serial communications protocol to for example, take readings from a high-precision ADC that might be present on an IO module at the same time as read a serial EEPROM on another module. The I2C protocol is used as the main communication channel for such actions, although provision is made for SPI or even a CAN physical layer.
Default I2C Addresses Used In The EDP System
There are three possible I2C channels available although in most cases the default one (I2C_CTRL) will be sufficient. EDP modules that carry I2C device do, where possible, allow the user to configure the I2C addresses. This allows for example, up to three digital IO modules to be fitted, with the GPIO devices on each module given an unique address. Where the address space of a particular I2C channel becomes full, devices can be connected to an alternative channel to get access to a completely new address space.

Inter-EDP System Communications
In a situation where there are multiple EDP baseboards, each with their own CPU modules in a complete system, I2C can still be used to allow the CPUs to communicate but it is strongly recommended to use CAN. EDP IO signals that are intended to be taken off-board are brought out on a standard DIN414162 64-way connector.

